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-rw-r--r--src/gallium/drivers/r600/r600_context.h3
-rw-r--r--src/gallium/drivers/r600/r600_state.c55
-rw-r--r--src/gallium/drivers/r600/radeon.h2
3 files changed, 60 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index eb370698bb..76a05f81fc 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -119,6 +119,9 @@ struct r600_context_hw_states {
struct radeon_state scissor;
struct radeon_state dsa;
struct radeon_state cb_cntl;
+
+ struct radeon_state db_flush;
+ struct radeon_state cb_flush;
};
#define R600_MAX_CONSTANT 256 /* magic */
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 93b0cf1a53..28c686a494 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -595,6 +595,54 @@ static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shad
}
}
+
+static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
+{
+ struct r600_screen *rscreen = rctx->screen;
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ struct pipe_surface *surf;
+ int i;
+
+ radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
+
+ for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+ surf = rctx->framebuffer->state.framebuffer.cbufs[i];
+
+ rtex = (struct r600_resource_texture*)surf->texture;
+ rbuffer = &rtex->resource;
+ /* just need to the bo to the flush list */
+ flush->bo[i] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
+ }
+ flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
+ return radeon_state_pm4(flush);
+}
+
+static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
+{
+ struct r600_screen *rscreen = rctx->screen;
+ struct r600_resource_texture *rtex;
+ struct r600_resource *rbuffer;
+ struct pipe_surface *surf;
+ int i;
+
+ surf = rctx->framebuffer->state.framebuffer.zsbuf;
+
+ if (!surf)
+ return 0;
+
+ radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
+ rtex = (struct r600_resource_texture*)surf->texture;
+ rbuffer = &rtex->resource;
+ /* just need to the bo to the flush list */
+ flush->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+ flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+
+ flush->nbo = 1;
+ return radeon_state_pm4(flush);
+}
+
int r600_context_hw_states(struct pipe_context *ctx)
{
struct r600_context *rctx = r600_context(ctx);
@@ -605,6 +653,10 @@ int r600_context_hw_states(struct pipe_context *ctx)
rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
+
+ /* setup flushes */
+ setup_db_flush(rctx, &rctx->hw_states.db_flush);
+ setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
/* bind states */
radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
@@ -614,6 +666,9 @@ int r600_context_hw_states(struct pipe_context *ctx)
radeon_draw_bind(&rctx->draw, &rctx->config);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
+ radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
+
if (rctx->viewport) {
radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 0a8cb73e7d..5759f363ea 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -212,6 +212,8 @@ enum r600_stype {
R600_STATE_UCP,
R600_STATE_VGT,
R600_STATE_DRAW,
+ R600_STATE_CB_FLUSH,
+ R600_STATE_DB_FLUSH,
};
#include "r600_states_inc.h"