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Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_context.c')
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c111
1 files changed, 50 insertions, 61 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 50c1964d87..5fa9d95e11 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -59,7 +59,7 @@
#include "intel_buffer_objects.h"
#include "intel_fbo.h"
#include "intel_decode.h"
-#include "intel_bufmgr.h"
+#include "intel_bufmgr_ttm.h"
#include "drirenderbuffer.h"
#include "vblank.h"
@@ -96,13 +96,11 @@ int INTEL_DEBUG = (0);
#include "extension_helper.h"
-#define DRIVER_DATE "20080716"
-#define DRIVER_DATE_GEM "GEM " DRIVER_DATE
+#define DRIVER_DATE "20061102"
static const GLubyte *
intelGetString(GLcontext * ctx, GLenum name)
{
- const struct intel_context *const intel = intel_context(ctx);
const char *chipset;
static char buffer[128];
@@ -112,7 +110,7 @@ intelGetString(GLcontext * ctx, GLenum name)
break;
case GL_RENDERER:
- switch (intel->intelScreen->deviceID) {
+ switch (intel_context(ctx)->intelScreen->deviceID) {
case PCI_CHIP_845_G:
chipset = "Intel(R) 845G";
break;
@@ -185,9 +183,7 @@ intelGetString(GLcontext * ctx, GLenum name)
break;
}
- (void) driGetRendererString(buffer, chipset,
- (intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE,
- 0);
+ (void) driGetRendererString(buffer, chipset, DRIVER_DATE, 0);
return (GLubyte *) buffer;
default:
@@ -371,34 +367,22 @@ intelFlush(GLcontext * ctx)
if (!IS_965(intel->intelScreen->deviceID))
INTEL_FIREVERTICES(intel);
- /* Emit a flush so that any frontbuffer rendering that might have occurred
- * lands onscreen in a timely manner, even if the X Server doesn't trigger
- * a flush for us.
- */
- intel_batchbuffer_emit_mi_flush(intel->batch);
-
if (intel->batch->map != intel->batch->ptr)
intel_batchbuffer_flush(intel->batch);
+
+ /* XXX: Need to do an MI_FLUSH here.
+ */
}
void
intelFinish(GLcontext * ctx)
{
- struct gl_framebuffer *fb = ctx->DrawBuffer;
- int i;
-
+ struct intel_context *intel = intel_context(ctx);
intelFlush(ctx);
-
- for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
- struct intel_renderbuffer *irb;
-
- irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]);
-
- if (irb->region)
- dri_bo_wait_rendering(irb->region->buffer);
- }
- if (fb->_DepthBuffer) {
- /* XXX: Wait on buffer idle */
+ if (intel->batch->last_fence) {
+ dri_fence_wait(intel->batch->last_fence);
+ dri_fence_unreference(intel->batch->last_fence);
+ intel->batch->last_fence = NULL;
}
}
@@ -464,32 +448,28 @@ static GLboolean
intel_init_bufmgr(struct intel_context *intel)
{
intelScreenPrivate *intelScreen = intel->intelScreen;
- GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL;
- int gem_kernel = 0;
- GLboolean gem_supported;
- struct drm_i915_getparam gp;
-
- gp.param = I915_PARAM_HAS_GEM;
- gp.value = &gem_kernel;
+ GLboolean ttm_disable = getenv("INTEL_NO_TTM") != NULL;
+ GLboolean ttm_supported;
- (void) drmCommandWriteRead(intel->driFd, DRM_I915_GETPARAM, &gp, sizeof(gp));
-
- /* If we've got a new enough DDX that's initializing GEM and giving us
+ /* If we've got a new enough DDX that's initializing TTM and giving us
* object handles for the shared buffers, use that.
*/
intel->ttm = GL_FALSE;
if (intel->intelScreen->driScrnPriv->dri2.enabled)
- gem_supported = GL_TRUE;
+ ttm_supported = GL_TRUE;
else if (intel->intelScreen->driScrnPriv->ddx_version.minor >= 9 &&
- gem_kernel &&
+ intel->intelScreen->drmMinor >= 11 &&
intel->intelScreen->front.bo_handle != -1)
- gem_supported = GL_TRUE;
+ ttm_supported = GL_TRUE;
else
- gem_supported = GL_FALSE;
+ ttm_supported = GL_FALSE;
- if (!gem_disable && gem_supported) {
+ if (!ttm_disable && ttm_supported) {
int bo_reuse_mode;
- intel->bufmgr = intel_bufmgr_gem_init(intel->driFd,
+ intel->bufmgr = intel_bufmgr_ttm_init(intel->driFd,
+ DRM_FENCE_TYPE_EXE,
+ DRM_FENCE_TYPE_EXE |
+ DRM_I915_FENCE_TYPE_RW,
BATCH_SZ);
if (intel->bufmgr != NULL)
intel->ttm = GL_TRUE;
@@ -499,16 +479,16 @@ intel_init_bufmgr(struct intel_context *intel)
case DRI_CONF_BO_REUSE_DISABLED:
break;
case DRI_CONF_BO_REUSE_ALL:
- intel_bufmgr_gem_enable_reuse(intel->bufmgr);
+ intel_ttm_enable_bo_reuse(intel->bufmgr);
break;
}
}
/* Otherwise, use the classic buffer manager. */
if (intel->bufmgr == NULL) {
- if (gem_disable) {
- fprintf(stderr, "GEM disabled. Using classic.\n");
+ if (ttm_disable) {
+ fprintf(stderr, "TTM buffer manager disabled. Using classic.\n");
} else {
- fprintf(stderr, "Failed to initialize GEM. "
+ fprintf(stderr, "Failed to initialize TTM buffer manager. "
"Falling back to classic.\n");
}
@@ -518,17 +498,14 @@ intel_init_bufmgr(struct intel_context *intel)
return GL_FALSE;
}
- intel->bufmgr = intel_bufmgr_fake_init(intelScreen->tex.offset,
- intelScreen->tex.map,
- intelScreen->tex.size,
- intel_fence_emit,
- intel_fence_wait,
- intel);
+ intel->bufmgr = dri_bufmgr_fake_init(intelScreen->tex.offset,
+ intelScreen->tex.map,
+ intelScreen->tex.size,
+ intel_fence_emit,
+ intel_fence_wait,
+ intel);
}
- /* XXX bufmgr should be per-screen, not per-context */
- intelScreen->ttm = intel->ttm;
-
return GL_TRUE;
}
@@ -696,6 +673,8 @@ intelInitContext(struct intel_context *intel,
intel_recreate_static_regions(intel);
intel->batch = intel_batchbuffer_alloc(intel);
+ intel->last_swap_fence = NULL;
+ intel->first_swap_fence = NULL;
intel_bufferobj_init(intel);
intel_fbo_init(intel);
@@ -713,6 +692,7 @@ intelInitContext(struct intel_context *intel,
/* Force all software fallbacks */
if (driQueryOptionb(&intel->optionCache, "no_rast")) {
fprintf(stderr, "disabling 3D rasterization\n");
+ FALLBACK(intel, INTEL_FALLBACK_USER, 1);
intel->no_rast = 1;
}
@@ -747,7 +727,17 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv)
intel->Fallback = 0; /* don't call _swrast_Flush later */
intel_batchbuffer_free(intel->batch);
- free(intel->prim.vb);
+
+ if (intel->last_swap_fence) {
+ dri_fence_wait(intel->last_swap_fence);
+ dri_fence_unreference(intel->last_swap_fence);
+ intel->last_swap_fence = NULL;
+ }
+ if (intel->first_swap_fence) {
+ dri_fence_wait(intel->first_swap_fence);
+ dri_fence_unreference(intel->first_swap_fence);
+ intel->first_swap_fence = NULL;
+ }
if (release_texture_heaps) {
/* This share group is about to go away, free our private
@@ -899,7 +889,7 @@ intelContendedLock(struct intel_context *intel, GLuint flags)
*/
if (!intel->ttm && sarea->texAge != intel->hHWContext) {
sarea->texAge = intel->hHWContext;
- intel_bufmgr_fake_contended_lock_take(intel->bufmgr);
+ dri_bufmgr_fake_contended_lock_take(intel->bufmgr);
if (INTEL_DEBUG & DEBUG_BATCH)
intel_decode_context_reset();
if (INTEL_DEBUG & DEBUG_BUFMGR)
@@ -1027,7 +1017,6 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
* Nothing should be left in batch outside of LOCK/UNLOCK which references
* cliprects.
*/
- if (intel->batch->cliprect_mode == REFERENCES_CLIPRECTS)
- intel_batchbuffer_flush(intel->batch);
+ assert(intel->batch->cliprect_mode != REFERENCES_CLIPRECTS);
}