1 files changed, 111 insertions, 51 deletions

diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 35ab46afea..ddfdce3835 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -39,13 +39,17 @@
  * last moment.
  */
 
+#include <sys/ioctl.h>
+#include <errno.h>
+
 #include "intel_context.h"
 #include "intel_regions.h"
 #include "intel_blit.h"
 #include "intel_buffer_objects.h"
 #include "dri_bufmgr.h"
-#include "intel_bufmgr_ttm.h"
+#include "intel_bufmgr.h"
 #include "intel_batchbuffer.h"
+#include "intel_chipset.h"
 
 #define FILE_DEBUG_FLAG DEBUG_REGION
 
@@ -76,10 +80,34 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region)
    }
 }
 
+static int
+intel_set_region_tiling_gem(struct intel_context *intel,
+			    struct intel_region *region,
+			    uint32_t bo_handle)
+{
+   struct drm_i915_gem_get_tiling get_tiling;
+   int ret;
+
+   memset(&get_tiling, 0, sizeof(get_tiling));
+
+   get_tiling.handle = bo_handle;
+   ret = ioctl(intel->driFd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
+   if (ret != 0) {
+      fprintf(stderr, "Failed to get tiling state for region: %s\n",
+	      strerror(errno));
+      return ret;
+   }
+
+   region->tiling = get_tiling.tiling_mode;
+   region->bit_6_swizzle = get_tiling.swizzle_mode;
+
+   return 0;
+}
+
 static struct intel_region *
 intel_region_alloc_internal(struct intel_context *intel,
 			    GLuint cpp, GLuint pitch, GLuint height,
-			    GLuint tiled, dri_bo *buffer)
+			    dri_bo *buffer)
 {
    struct intel_region *region;
 
@@ -93,9 +121,12 @@ intel_region_alloc_internal(struct intel_context *intel,
    region->pitch = pitch;
    region->height = height;     /* needed? */
    region->refcount = 1;
-   region->tiled = tiled;
    region->buffer = buffer;
 
+   /* Default to no tiling */
+   region->tiling = I915_TILING_NONE;
+   region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
+
    return region;
 }
 
@@ -106,25 +137,28 @@ intel_region_alloc(struct intel_context *intel,
    dri_bo *buffer;
 
    buffer = dri_bo_alloc(intel->bufmgr, "region",
-			 pitch * cpp * height, 64,
-			 DRM_BO_FLAG_MEM_LOCAL |
-			 DRM_BO_FLAG_CACHED |
-			 DRM_BO_FLAG_CACHED_MAPPED);
+			 pitch * cpp * height, 64);
 
-   return intel_region_alloc_internal(intel, cpp, pitch, height, 0, buffer);
+   return intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
 }
 
 struct intel_region *
 intel_region_alloc_for_handle(struct intel_context *intel,
 			      GLuint cpp, GLuint pitch, GLuint height,
-			      GLuint tiled, GLuint handle)
+			      GLuint handle)
 {
+   struct intel_region *region;
    dri_bo *buffer;
 
-   buffer = intel_ttm_bo_create_from_handle(intel->bufmgr, "region", handle);
+   buffer = intel_bo_gem_create_from_name(intel->bufmgr, "dri2 region", handle);
 
-   return intel_region_alloc_internal(intel,
-				      cpp, pitch, height, tiled, buffer);
+   region = intel_region_alloc_internal(intel, cpp, pitch, height, buffer);
+   if (region == NULL)
+      return region;
+
+   intel_set_region_tiling_gem(intel, region, handle);
+
+   return region;
 }
 
 void
@@ -138,26 +172,34 @@ intel_region_reference(struct intel_region **dst, struct intel_region *src)
 }
 
 void
-intel_region_release(struct intel_region **region)
+intel_region_release(struct intel_region **region_handle)
 {
-   if (!*region)
+   struct intel_region *region = *region_handle;
+
+   if (region == NULL)
       return;
 
-   DBG("%s %d\n", __FUNCTION__, (*region)->refcount - 1);
+   DBG("%s %d\n", __FUNCTION__, region->refcount - 1);
+
+   ASSERT(region->refcount > 0);
+   region->refcount--;
 
-   ASSERT((*region)->refcount > 0);
-   (*region)->refcount--;
+   if (region->refcount == 0) {
+      assert(region->map_refcount == 0);
 
-   if ((*region)->refcount == 0) {
-      assert((*region)->map_refcount == 0);
+      if (region->pbo)
+	 region->pbo->region = NULL;
+      region->pbo = NULL;
+      dri_bo_unreference(region->buffer);
+
+      if (region->classic_map != NULL) {
+	 drmUnmap(region->classic_map,
+			region->pitch * region->cpp * region->height);
+      }
 
-      if ((*region)->pbo)
-	 (*region)->pbo->region = NULL;
-      (*region)->pbo = NULL;
-      dri_bo_unreference((*region)->buffer);
-      free(*region);
+      free(region);
    }
-   *region = NULL;
+   *region_handle = NULL;
 }
 
 /*
@@ -272,8 +314,8 @@ intel_region_copy(struct intel_context *intel,
 
    intelEmitCopyBlit(intel,
                      dst->cpp,
-                     src->pitch, src->buffer, src_offset, src->tiled,
-                     dst->pitch, dst->buffer, dst_offset, dst->tiled,
+                     src->pitch, src->buffer, src_offset, src->tiling,
+                     dst->pitch, dst->buffer, dst_offset, dst->tiling,
                      srcx, srcy, dstx, dsty, width, height,
 		     GL_COPY);
 }
@@ -303,7 +345,7 @@ intel_region_fill(struct intel_context *intel,
 
    intelEmitFillBlit(intel,
                      dst->cpp,
-                     dst->pitch, dst->buffer, dst_offset, dst->tiled,
+                     dst->pitch, dst->buffer, dst_offset, dst->tiling,
                      dstx, dsty, width, height, color);
 }
 
@@ -355,10 +397,7 @@ intel_region_release_pbo(struct intel_context *intel,
 
    region->buffer = dri_bo_alloc(intel->bufmgr, "region",
 				 region->pitch * region->cpp * region->height,
-				 64,
-				 DRM_BO_FLAG_MEM_LOCAL |
-				 DRM_BO_FLAG_CACHED |
-				 DRM_BO_FLAG_CACHED_MAPPED);
+				 64);
 }
 
 /* Break the COW tie to the pbo.  Both the pbo and the region end up
@@ -382,23 +421,19 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region)
    /* Now blit from the texture buffer to the new buffer: 
     */
 
-   intel_batchbuffer_flush(intel->batch);
-
    was_locked = intel->locked;
-   if (intel->locked)
+   if (!was_locked)
       LOCK_HARDWARE(intel);
 
    intelEmitCopyBlit(intel,
 		     region->cpp,
-		     region->pitch, region->buffer, 0, region->tiled,
-		     region->pitch, pbo->buffer, 0, region->tiled,
+		     region->pitch, region->buffer, 0, region->tiling,
+		     region->pitch, pbo->buffer, 0, region->tiling,
 		     0, 0, 0, 0,
 		     region->pitch, region->height,
 		     GL_COPY);
 
-   intel_batchbuffer_flush(intel->batch);
-
-   if (was_locked)
+   if (!was_locked)
       UNLOCK_HARDWARE(intel);
 }
 
@@ -423,6 +458,7 @@ intel_recreate_static(struct intel_context *intel,
 		      intelRegion *region_desc)
 {
    intelScreenPrivate *intelScreen = intel->intelScreen;
+   int ret;
 
    if (region == NULL) {
       region = calloc(sizeof(*region), 1);
@@ -435,21 +471,45 @@ intel_recreate_static(struct intel_context *intel,
       region->cpp = intel->ctx.Visual.rgbBits / 8;
    region->pitch = intelScreen->pitch;
    region->height = intelScreen->height;     /* needed? */
-   region->tiled = region_desc->tiled;
 
    if (intel->ttm) {
       assert(region_desc->bo_handle != -1);
-      region->buffer = intel_ttm_bo_create_from_handle(intel->bufmgr,
-						       name,
-						       region_desc->bo_handle);
+      region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
+						     name,
+						     region_desc->bo_handle);
+
+      intel_set_region_tiling_gem(intel, region, region_desc->bo_handle);
    } else {
-      region->buffer = dri_bo_alloc_static(intel->bufmgr,
-					   name,
-					   region_desc->offset,
-					   intelScreen->pitch *
-					   intelScreen->height,
-					   region_desc->map,
-					   DRM_BO_FLAG_MEM_TT);
+      ret = drmMap(intel->driFd, region_desc->handle,
+		   region->pitch * region->cpp * region->height,
+		   &region->classic_map);
+      if (ret != 0) {
+	 fprintf(stderr, "Failed to drmMap %s buffer\n", name);
+	 free(region);
+	 return NULL;
+      }
+
+      region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
+						  name,
+						  region_desc->offset,
+						  region->pitch * region->cpp *
+						  region->height,
+						  region->classic_map);
+
+      /* The sarea just gives us a boolean for whether it's tiled or not,
+       * instead of which tiling mode it is.  Guess.
+       */
+      if (region_desc->tiled) {
+	 if (IS_965(intel->intelScreen->deviceID) &&
+	     region_desc == &intelScreen->depth)
+	    region->tiling = I915_TILING_Y;
+	 else
+	    region->tiling = I915_TILING_X;
+      } else {
+	 region->tiling = I915_TILING_NONE;
+      }
+
+      region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
    }
 
    assert(region->buffer != NULL);