diff options
Diffstat (limited to 'src/mesa/drivers/dri/r600/r600_ioctl.c')
-rw-r--r-- | src/mesa/drivers/dri/r600/r600_ioctl.c | 206 |
1 files changed, 52 insertions, 154 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_ioctl.c b/src/mesa/drivers/dri/r600/r600_ioctl.c index 7e180a1a6e..f93970e9f5 100644 --- a/src/mesa/drivers/dri/r600/r600_ioctl.c +++ b/src/mesa/drivers/dri/r600/r600_ioctl.c @@ -215,16 +215,8 @@ static void r600EmitClearState(GLcontext * ctx) BATCH_LOCALS(&r600->radeon); __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; int i; - int has_tcl = 1; - int is_r500 = 0; GLuint vap_cntl; - if (!(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) - has_tcl = 0; - - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - is_r500 = 1; - /* State atom dirty tracking is a little subtle here. * * On the one hand, we need to make sure base state is emitted @@ -243,12 +235,9 @@ static void r600EmitClearState(GLcontext * ctx) */ BEGIN_BATCH(31); OUT_BATCH_REGSEQ(R600_VAP_PROG_STREAM_CNTL_0, 1); - if (!has_tcl) - OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | - ((R600_LAST_VEC | (2 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); - else - OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | - ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); + + OUT_BATCH(((((0 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_0_SHIFT) | + ((R600_LAST_VEC | (1 << R600_DST_VEC_LOC_SHIFT) | R600_DATA_TYPE_FLOAT_4) << R600_DATA_TYPE_1_SHIFT))); OUT_BATCH_REGVAL(R600_FG_FOG_BLEND, 0); OUT_BATCH_REGVAL(R600_VAP_PROG_STREAM_CNTL_EXT_0, @@ -314,13 +303,11 @@ static void r600EmitClearState(GLcontext * ctx) R600_STATECHANGE(r600, bld); R600_STATECHANGE(r600, ps); - if (has_tcl) { - R600_STATECHANGE(r600, vap_clip_cntl); + R600_STATECHANGE(r600, vap_clip_cntl); - BEGIN_BATCH_NO_AUTOSTATE(2); - OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE); - END_BATCH(); - } + BEGIN_BATCH_NO_AUTOSTATE(2); + OUT_BATCH_REGVAL(R600_VAP_CLIP_CNTL, R600_PS_UCP_MODE_CLIP_AS_TRIFAN | R600_CLIP_DISABLE); + END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(2); OUT_BATCH_REGVAL(R600_GA_POINT_SIZE, @@ -328,146 +315,57 @@ static void r600EmitClearState(GLcontext * ctx) ((dPriv->h * 6) << R600_POINTSIZE_Y_SHIFT)); END_BATCH(); - if (!is_r500) { - R600_STATECHANGE(r600, ri); - R600_STATECHANGE(r600, rc); - R600_STATECHANGE(r600, rr); - - BEGIN_BATCH(14); - OUT_BATCH_REGSEQ(R600_RS_IP_0, 8); - for (i = 0; i < 8; ++i) - OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3)); - OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); - OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); - OUT_BATCH(0x0); + R600_STATECHANGE(r600, ri); + R600_STATECHANGE(r600, rc); + R600_STATECHANGE(r600, rr); - OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE); - END_BATCH(); - } else { - R600_STATECHANGE(r600, ri); - R600_STATECHANGE(r600, rc); - R600_STATECHANGE(r600, rr); - - BEGIN_BATCH(14); - OUT_BATCH_REGSEQ(R500_RS_IP_0, 8); - for (i = 0; i < 8; ++i) { - OUT_BATCH((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); - } + BEGIN_BATCH(14); + OUT_BATCH_REGSEQ(R600_RS_IP_0, 8); + for (i = 0; i < 8; ++i) + OUT_BATCH(R600_RS_SEL_T(1) | R600_RS_SEL_R(2) | R600_RS_SEL_Q(3)); - OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); - OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); - OUT_BATCH(0x0); - - OUT_BATCH_REGVAL(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); - END_BATCH(); - } + OUT_BATCH_REGSEQ(R600_RS_COUNT, 2); + OUT_BATCH((1 << R600_IC_COUNT_SHIFT) | R600_HIRES_EN); + OUT_BATCH(0x0); - if (!is_r500) { - R600_STATECHANGE(r600, fp); - R600_STATECHANGE(r600, fpi[0]); - R600_STATECHANGE(r600, fpi[1]); - R600_STATECHANGE(r600, fpi[2]); - R600_STATECHANGE(r600, fpi[3]); - - BEGIN_BATCH(17); - OUT_BATCH_REGSEQ(R600_US_CONFIG, 3); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(0x0); - OUT_BATCH(R600_RGBA_OUT); - - OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0, - FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); - OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0, - FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); - OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0, - FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); - OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0, - FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); - END_BATCH(); - } else { - struct radeon_state_atom r500fp; - uint32_t _cmd[10]; + OUT_BATCH_REGVAL(R600_RS_INST_0, R600_RS_INST_COL_CN_WRITE); + END_BATCH(); - R600_STATECHANGE(r600, fp); - R600_STATECHANGE(r600, r500fp); - - BEGIN_BATCH(7); - OUT_BATCH_REGSEQ(R500_US_CONFIG, 2); - OUT_BATCH(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); - OUT_BATCH(0x0); - OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3); - OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); - OUT_BATCH(R500_US_CODE_OFFSET_ADDR(0)); - END_BATCH(); + R600_STATECHANGE(r600, fp); + R600_STATECHANGE(r600, fpi[0]); + R600_STATECHANGE(r600, fpi[1]); + R600_STATECHANGE(r600, fpi[2]); + R600_STATECHANGE(r600, fpi[3]); - r500fp.check = check_r500fp; - r500fp.cmd = _cmd; - r500fp.cmd[0] = cmdr500fp(r600->radeon.radeonScreen, 0, 1, 0, 0); - r500fp.cmd[1] = R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP; - r500fp.cmd[2] = R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST; - r500fp.cmd[3] = R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST; - r500fp.cmd[4] = R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B; - r500fp.cmd[5] = R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A; - r500fp.cmd[6] = R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0; - - r500fp.cmd[7] = 0; - emit_r500fp(ctx, &r500fp); - } + BEGIN_BATCH(17); + OUT_BATCH_REGSEQ(R600_US_CONFIG, 3); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH_REGSEQ(R600_US_CODE_ADDR_0, 4); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(0x0); + OUT_BATCH(R600_RGBA_OUT); + + OUT_BATCH_REGVAL(R600_US_ALU_RGB_INST_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); + OUT_BATCH_REGVAL(R600_US_ALU_RGB_ADDR_0, + FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_INST_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); + OUT_BATCH_REGVAL(R600_US_ALU_ALPHA_ADDR_0, + FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); + END_BATCH(); BEGIN_BATCH(2); OUT_BATCH_REGVAL(R600_VAP_PVS_STATE_FLUSH_REG, 0); END_BATCH(); - if (has_tcl) { - vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | - (5 << R600_PVS_NUM_CNTLRS_SHIFT) | - (12 << R600_VF_MAX_VTX_NUM_SHIFT)); - if (r600->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) - vap_cntl |= R500_TCL_STATE_OPTIMIZATION; - } else { - vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | - (5 << R600_PVS_NUM_CNTLRS_SHIFT) | - (5 << R600_VF_MAX_VTX_NUM_SHIFT)); - } + vap_cntl = ((10 << R600_PVS_NUM_SLOTS_SHIFT) | + (5 << R600_PVS_NUM_CNTLRS_SHIFT) | + (12 << R600_VF_MAX_VTX_NUM_SHIFT)); if (r600->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV515) vap_cntl |= (2 << R600_PVS_NUM_FPUS_SHIFT); @@ -490,9 +388,9 @@ static void r600EmitClearState(GLcontext * ctx) OUT_BATCH_REGVAL(R600_VAP_CNTL, vap_cntl); END_BATCH(); - if (has_tcl) { - struct radeon_state_atom vpu; - uint32_t _cmd[10]; + { + struct radeon_state_atom vpu; + uint32_t _cmd[10]; R600_STATECHANGE(r600, pvs); R600_STATECHANGE(r600, vpi); @@ -542,7 +440,7 @@ static void r600EmitClearState(GLcontext * ctx) } static void r600KernelClear(GLcontext *ctx, GLuint flags) -{ +{ r600ContextPtr r600 = R600_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = r600->radeon.dri.drawable; struct radeon_framebuffer *rfb = dPriv->driverPrivate; @@ -566,7 +464,7 @@ static void r600KernelClear(GLcontext *ctx, GLuint flags) r600ClearBuffer(r600, CLEARBUFFER_COLOR, rrb, NULL); bits = 0; } - + if (flags & BUFFER_BIT_FRONT_LEFT) { rrb = radeon_get_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT); r600ClearBuffer(r600, bits | CLEARBUFFER_COLOR, rrb, rrbd); |