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Diffstat (limited to 'src/mesa/drivers/dri/r600/r600_tex.c')
-rw-r--r--src/mesa/drivers/dri/r600/r600_tex.c21
1 files changed, 5 insertions, 16 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 20965bb3c8..f745fe3e8a 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -305,23 +305,14 @@ static void r600TexParameter(GLcontext * ctx, GLenum target,
break;
case GL_TEXTURE_BORDER_COLOR:
- r600SetTexBorderColor(t, texObj->BorderColor);
+ r600SetTexBorderColor(t, texObj->BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
case GL_TEXTURE_MAX_LEVEL:
case GL_TEXTURE_MIN_LOD:
case GL_TEXTURE_MAX_LOD:
- /* This isn't the most efficient solution but there doesn't appear to
- * be a nice alternative. Since there's no LOD clamping,
- * we just have to rely on loading the right subset of mipmap levels
- * to simulate a clamped LOD.
- */
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- t->validated = GL_FALSE;
- }
+ t->validated = GL_FALSE;
break;
case GL_DEPTH_TEXTURE_MODE:
@@ -369,10 +360,8 @@ static void r600DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
t->bo = NULL;
}
- if (t->mt) {
- radeon_miptree_unreference(t->mt);
- t->mt = 0;
- }
+ radeon_miptree_unreference(&t->mt);
+
_mesa_delete_texture_object(ctx, texObj);
}
@@ -402,7 +391,7 @@ static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx,
r600SetTexDefaultState(t);
r600UpdateTexWrap(t);
r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy);
- r600SetTexBorderColor(t, t->base.BorderColor);
+ r600SetTexBorderColor(t, t->base.BorderColor.f);
return &t->base;
}