diff options
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_maos_verts.c')
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_maos_verts.c | 134 |
1 files changed, 98 insertions, 36 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c index 3d004adda6..57aa90321c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_maos_verts.c +++ b/src/mesa/drivers/dri/radeon/radeon_maos_verts.c @@ -51,7 +51,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "radeon_maos.h" -#define RADEON_TCL_MAX_SETUP 13 +#define RADEON_TCL_MAX_SETUP 19 union emit_union { float f; GLuint ui; radeon_color_t rgba; }; @@ -67,10 +67,10 @@ static struct { #define DO_FOG (IND & RADEON_CP_VC_FRMT_PKSPEC) #define DO_TEX0 (IND & RADEON_CP_VC_FRMT_ST0) #define DO_TEX1 (IND & RADEON_CP_VC_FRMT_ST1) +#define DO_TEX2 (IND & RADEON_CP_VC_FRMT_ST2) #define DO_PTEX (IND & RADEON_CP_VC_FRMT_Q0) #define DO_NORM (IND & RADEON_CP_VC_FRMT_N0) -#define DO_TEX2 0 #define DO_TEX3 0 #define GET_TEXSOURCE(n) n @@ -202,6 +202,77 @@ static struct { #define TAG(x) x##_w_rgba_spec_stq_stq_n #include "radeon_maos_vbtmp.h" +#define IDX 13 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2) +#define TAG(x) x##_rgba_st_st_st +#include "radeon_maos_vbtmp.h" + +#define IDX 14 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2) +#define TAG(x) x##_rgba_spec_st_st_st +#include "radeon_maos_vbtmp.h" + +#define IDX 15 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_st_st_st_n +#include "radeon_maos_vbtmp.h" + +#define IDX 16 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_rgba_spec_st_st_st_n +#include "radeon_maos_vbtmp.h" + +#define IDX 17 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_Q0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_Q1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_Q2) +#define TAG(x) x##_rgba_stq_stq_stq +#include "radeon_maos_vbtmp.h" + +#define IDX 18 +#define IND (RADEON_CP_VC_FRMT_XY| \ + RADEON_CP_VC_FRMT_Z| \ + RADEON_CP_VC_FRMT_W0| \ + RADEON_CP_VC_FRMT_PKCOLOR| \ + RADEON_CP_VC_FRMT_PKSPEC| \ + RADEON_CP_VC_FRMT_ST0| \ + RADEON_CP_VC_FRMT_Q0| \ + RADEON_CP_VC_FRMT_ST1| \ + RADEON_CP_VC_FRMT_Q1| \ + RADEON_CP_VC_FRMT_ST2| \ + RADEON_CP_VC_FRMT_Q2| \ + RADEON_CP_VC_FRMT_N0) +#define TAG(x) x##_w_rgba_spec_stq_stq_stq_n +#include "radeon_maos_vbtmp.h" @@ -226,6 +297,12 @@ static void init_tcl_verts( void ) init_rgba_stq(); init_rgba_stq_stq(); init_w_rgba_spec_stq_stq_n(); + init_rgba_st_st_st(); + init_rgba_spec_st_st_st(); + init_st_st_st_n(); + init_rgba_spec_st_st_st_n(); + init_rgba_stq_stq_stq(); + init_w_rgba_spec_stq_stq_stq_n(); } @@ -234,8 +311,9 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) radeonContextPtr rmesa = RADEON_CONTEXT(ctx); struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb; GLuint req = 0; + GLuint unit; GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] & - ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1)); + ~(RADEON_TCL_VTX_Q0|RADEON_TCL_VTX_Q1|RADEON_TCL_VTX_Q2)); int i; static int firsttime = 1; @@ -263,39 +341,23 @@ void radeonEmitArrays( GLcontext *ctx, GLuint inputs ) req |= RADEON_CP_VC_FRMT_PKSPEC; } - if (inputs & VERT_BIT_TEX0) { - req |= RADEON_CP_VC_FRMT_ST0; - /* assume we need the 3rd coord if texgen is active for r/q OR at least 3 - coords are submitted. This may not be 100% correct */ - if (VB->TexCoordPtr[0]->size >= 3) { - req |= RADEON_CP_VC_FRMT_Q0; - vtx |= RADEON_TCL_VTX_Q0; - } - if ( (ctx->Texture.Unit[0].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q0; - else if (VB->TexCoordPtr[0]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[0]->size - 3); - if ((rmesa->NeedTexMatrix & 1) && - (swaptexmatcol != (rmesa->TexMatColSwap & 1))) - radeonUploadTexMatrix( rmesa, 0, swaptexmatcol ) ; - } - } - - - if (inputs & VERT_BIT_TEX1) { - req |= RADEON_CP_VC_FRMT_ST1; - - if (VB->TexCoordPtr[1]->size >= 3) { - req |= RADEON_CP_VC_FRMT_Q1; - vtx |= RADEON_TCL_VTX_Q1; - } - if ( (ctx->Texture.Unit[1].TexGenEnabled & (R_BIT | Q_BIT)) ) - vtx |= RADEON_TCL_VTX_Q1; - else if (VB->TexCoordPtr[1]->size >= 3) { - GLuint swaptexmatcol = (VB->TexCoordPtr[1]->size - 3); - if (((rmesa->NeedTexMatrix >> 1) & 1) && - (swaptexmatcol != ((rmesa->TexMatColSwap >> 1) & 1))) - radeonUploadTexMatrix( rmesa, 1, swaptexmatcol ) ; + for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) { + if (inputs & VERT_BIT_TEX(unit)) { + req |= RADEON_ST_BIT(unit); + /* assume we need the 3rd coord if texgen is active for r/q OR at least + 3 coords are submitted. This may not be 100% correct */ + if (VB->TexCoordPtr[unit]->size >= 3) { + req |= RADEON_Q_BIT(unit); + vtx |= RADEON_Q_BIT(unit); + } + if ( (ctx->Texture.Unit[unit].TexGenEnabled & (R_BIT | Q_BIT)) ) + vtx |= RADEON_Q_BIT(unit); + else if (VB->TexCoordPtr[unit]->size >= 3) { + GLuint swaptexmatcol = (VB->TexCoordPtr[unit]->size - 3); + if (((rmesa->NeedTexMatrix >> unit) & 1) && + (swaptexmatcol != ((rmesa->TexMatColSwap >> unit) & 1))) + radeonUploadTexMatrix( rmesa, unit, swaptexmatcol ) ; + } } } |