summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/radeon
diff options
context:
space:
mode:
Diffstat (limited to 'src/mesa/drivers/dri/radeon')
-rw-r--r--src/mesa/drivers/dri/radeon/Makefile.solo2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_compat.c16
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.c6
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_context.h15
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_ioctl.c86
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_lock.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_sanity.c30
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_sanity.h2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.c26
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_screen.h3
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state.c20
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_state_init.c8
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_texmem.c10
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_dri.c37
-rw-r--r--src/mesa/drivers/dri/radeon/server/radeon_dri.h3
15 files changed, 135 insertions, 137 deletions
diff --git a/src/mesa/drivers/dri/radeon/Makefile.solo b/src/mesa/drivers/dri/radeon/Makefile.solo
index a5430b23b2..c5387f025b 100644
--- a/src/mesa/drivers/dri/radeon/Makefile.solo
+++ b/src/mesa/drivers/dri/radeon/Makefile.solo
@@ -7,7 +7,7 @@ TOP = ../../../../..
default: linux-solo
-SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver
+SHARED_INCLUDES = $(INCLUDE_DIRS) -I. -I../common -Iserver -I../drm/shared
MINIGLX_INCLUDES = -I$(TOP)/src/glx/mini
ifeq ($(EMBEDDED),true)
diff --git a/src/mesa/drivers/dri/radeon/radeon_compat.c b/src/mesa/drivers/dri/radeon/radeon_compat.c
index 0c32641530..857d6edc39 100644
--- a/src/mesa/drivers/dri/radeon/radeon_compat.c
+++ b/src/mesa/drivers/dri/radeon/radeon_compat.c
@@ -73,15 +73,15 @@ static struct {
static void radeonCompatEmitPacket( radeonContextPtr rmesa,
struct radeon_state_atom *state )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
- radeon_context_regs_t *ctx = &sarea->ContextState;
- radeon_texture_regs_t *tex0 = &sarea->TexState[0];
- radeon_texture_regs_t *tex1 = &sarea->TexState[1];
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
+ drm_radeon_context_regs_t *ctx = &sarea->context_state;
+ drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
+ drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
int i;
int *buf = state->cmd;
for ( i = 0 ; i < state->cmd_size ; ) {
- drmRadeonCmdHeader *header = (drmRadeonCmdHeader *)&buf[i++];
+ drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
if (RADEON_DEBUG & DEBUG_STATE)
fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
@@ -229,15 +229,15 @@ static void radeonCompatEmitStateLocked( radeonContextPtr rmesa )
static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
GLuint hw_primitive,
GLuint nverts,
- XF86DRIClipRectPtr pbox,
+ drm_clip_rect_t *pbox,
GLuint nbox )
{
int i;
for ( i = 0 ; i < nbox ; ) {
int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonVertex vtx;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_vertex_t vtx;
rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
rmesa->sarea->nbox = nr - i;
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c
index 0424ffc84a..2889a7d104 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -274,7 +274,7 @@ radeonCreateContext( const __GLcontextModes *glVisual,
rmesa->dri.drmMinor = sPriv->drmMinor;
rmesa->radeonScreen = screen;
- rmesa->sarea = (RADEONSAREAPrivPtr)((GLubyte *)sPriv->pSAREA +
+ rmesa->sarea = (drm_radeon_sarea_t *)((GLubyte *)sPriv->pSAREA +
screen->sarea_priv_offset);
@@ -289,8 +289,8 @@ radeonCreateContext( const __GLcontextModes *glVisual,
screen->texSize[i],
12,
RADEON_NR_TEX_REGIONS,
- rmesa->sarea->texList[i],
- & rmesa->sarea->texAge[i],
+ (drmTextureRegionPtr)rmesa->sarea->tex_list[i],
+ & rmesa->sarea->tex_age[i],
& rmesa->swapped,
sizeof( radeonTexObj ),
(destroy_texture_object_t *) radeonDestroyTexObj );
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h
index 3ce67044f9..45b5a50418 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_context.h
@@ -42,7 +42,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <inttypes.h>
#include "dri_util.h"
-#include "radeon_common.h"
#include "texmem.h"
#include "macros.h"
@@ -111,12 +110,12 @@ struct radeon_pixel_state {
};
struct radeon_scissor_state {
- XF86DRIClipRectRec rect;
+ drm_clip_rect_t rect;
GLboolean enabled;
GLuint numClipRects; /* Cliprects active */
GLuint numAllocedClipRects; /* Cliprects available */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
};
struct radeon_stencilbuffer_state {
@@ -151,7 +150,7 @@ struct radeon_tex_obj {
brought into the
texunit. */
- drmRadeonTexImage image[6][RADEON_MAX_TEXTURE_LEVELS];
+ drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS];
/* Six, for the cube faces */
GLuint pp_txfilter; /* hardware register values */
@@ -483,7 +482,7 @@ struct radeon_dri_mirror {
__DRIdrawablePrivate *drawable; /* DRI drawable bound to this ctx */
drmContext hwContext;
- drmLock *hwLock;
+ drm_hw_lock_t *hwLock;
int fd;
int drmMinor;
};
@@ -723,16 +722,16 @@ struct radeon_context {
GLuint do_usleeps;
GLuint do_irqs;
GLuint irqsEmitted;
- drmRadeonIrqWait iw;
+ drm_radeon_irq_wait_t iw;
/* Drawable, cliprect and scissor information
*/
GLuint numClipRects; /* Cliprects for the draw buffer */
- XF86DRIClipRectPtr pClipRects;
+ drm_clip_rect_t *pClipRects;
unsigned int lastStamp;
GLboolean lost_context;
radeonScreenPtr radeonScreen; /* Screen private DRI data */
- RADEONSAREAPrivPtr sarea; /* Private SAREA data */
+ drm_radeon_sarea_t *sarea; /* Private SAREA data */
/* TCL stuff
*/
diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
index 7b27d3f766..631f140d05 100644
--- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c
+++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c
@@ -192,7 +192,7 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
GLuint primitive,
GLuint vertex_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert(!(primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
@@ -204,7 +204,7 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
rmesa->store.cmd_used/4);
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 6 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
cmd[1].i = RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM | (3 << 16);
@@ -222,7 +222,7 @@ extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
__FUNCTION__,
cmd[1].i, cmd[2].i, cmd[4].i, cmd[5].i);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 4 * sizeof(*cmd),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3_CLIP;
@@ -280,7 +280,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
GLuint primitive,
GLuint min_nr )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
GLushort *retval;
if (RADEON_DEBUG & DEBUG_IOCTL)
@@ -291,7 +291,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
radeonEmitState( rmesa );
#if RADEON_OLD_PACKETS
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
24 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
@@ -307,7 +307,7 @@ GLushort *radeonAllocEltsOpenEnded( radeonContextPtr rmesa,
retval = (GLushort *)(cmd+6);
#else
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa,
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa,
16 + min_nr*2,
__FUNCTION__ );
cmd[0].i = 0;
@@ -347,13 +347,13 @@ void radeonEmitVertexAOS( radeonContextPtr rmesa,
rmesa->ioctl.vertex_size = vertex_size;
rmesa->ioctl.vertex_offset = offset;
#else
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_PRIMS|DEBUG_IOCTL))
fprintf(stderr, "%s: vertex_size 0x%x offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 5 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
@@ -378,7 +378,7 @@ void radeonEmitAOS( radeonContextPtr rmesa,
rmesa->ioctl.vertex_offset =
(component[0]->aos_start + offset * component[0]->aos_stride * 4);
#else
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
int sz = 3 + (nr/2 * 3) + (nr & 1) * 2;
int i;
int *tmp;
@@ -387,7 +387,7 @@ void radeonEmitAOS( radeonContextPtr rmesa,
fprintf(stderr, "%s\n", __FUNCTION__);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sz * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].header.cmd_type = RADEON_CMD_PACKET3;
@@ -431,7 +431,7 @@ void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is require
GLint dstx, GLint dsty,
GLuint w, GLuint h )
{
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & DEBUG_IOCTL)
fprintf(stderr, "%s src %x/%x %d,%d dst: %x/%x %d,%d sz: %dx%d\n",
@@ -447,7 +447,7 @@ void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is require
assert( w < (1<<16) );
assert( h < (1<<16) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 8 * sizeof(int),
__FUNCTION__ );
@@ -475,11 +475,11 @@ void radeonEmitBlit( radeonContextPtr rmesa, /* FIXME: which drmMinor is require
void radeonEmitWait( radeonContextPtr rmesa, GLuint flags )
{
if (rmesa->dri.drmMinor >= 6) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
assert( !(flags & ~(RADEON_WAIT_2D|RADEON_WAIT_3D)) );
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, 1 * sizeof(int),
__FUNCTION__ );
cmd[0].i = 0;
cmd[0].wait.cmd_type = RADEON_CMD_WAIT;
@@ -492,7 +492,7 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
const char * caller )
{
int ret, i;
- drmRadeonCmdBuffer cmd;
+ drm_radeon_cmd_buffer_t cmd;
if (RADEON_DEBUG & DEBUG_IOCTL) {
fprintf(stderr, "%s from %s\n", __FUNCTION__, caller);
@@ -529,10 +529,10 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
if (rmesa->state.scissor.enabled) {
cmd.nbox = rmesa->state.scissor.numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->state.scissor.pClipRects;
+ cmd.boxes = rmesa->state.scissor.pClipRects;
} else {
cmd.nbox = rmesa->numClipRects;
- cmd.boxes = (drmClipRect *)rmesa->pClipRects;
+ cmd.boxes = rmesa->pClipRects;
}
ret = drmCommandWrite( rmesa->dri.fd,
@@ -567,7 +567,7 @@ void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
UNLOCK_HARDWARE( rmesa );
if (ret) {
- fprintf(stderr, "drmRadeonCmdBuffer: %d (exiting)\n", ret);
+ fprintf(stderr, "drm_radeon_cmd_buffer_t: %d (exiting)\n", ret);
exit(ret);
}
}
@@ -666,13 +666,13 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa,
rmesa->dma.flush( rmesa );
if (--region->buf->refcount == 0) {
- drmRadeonCmdHeader *cmd;
+ drm_radeon_cmd_header_t *cmd;
if (RADEON_DEBUG & (DEBUG_IOCTL|DEBUG_DMA))
fprintf(stderr, "%s -- DISCARD BUF %d\n", __FUNCTION__,
region->buf->buf->idx);
- cmd = (drmRadeonCmdHeader *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
+ cmd = (drm_radeon_cmd_header_t *)radeonAllocCmdBuf( rmesa, sizeof(*cmd),
__FUNCTION__ );
cmd->dma.cmd_type = RADEON_CMD_DMA_DISCARD;
cmd->dma.buf_idx = region->buf->buf->idx;
@@ -740,7 +740,7 @@ static CARD32 radeonGetLastFrame (radeonContextPtr rmesa)
CARD32 frame;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_FRAME;
gp.value = (int *)&frame;
@@ -757,7 +757,7 @@ static CARD32 radeonGetLastFrame (radeonContextPtr rmesa)
}
#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
@@ -766,14 +766,14 @@ static CARD32 radeonGetLastFrame (radeonContextPtr rmesa)
static void radeonEmitIrqLocked( radeonContextPtr rmesa )
{
- drmRadeonIrqEmit ie;
+ drm_radeon_irq_emit_t ie;
int ret;
ie.irq_seq = &rmesa->iw.irq_seq;
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_IRQ_EMIT,
&ie, sizeof(ie) );
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonIrqEmit: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_irq_emit_t: %d\n", __FUNCTION__, ret );
exit(1);
}
}
@@ -797,7 +797,7 @@ static void radeonWaitIrq( radeonContextPtr rmesa )
static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
{
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
if (rmesa->do_irqs) {
if (radeonGetLastFrame(rmesa) < sarea->last_frame) {
@@ -835,7 +835,7 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv )
radeonContextPtr rmesa;
GLint nbox, i, ret;
GLboolean missed_target;
- uint64_t ust;
+ int64_t ust;
assert(dPriv);
assert(dPriv->driContextPriv);
@@ -862,8 +862,8 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv )
for ( i = 0 ; i < nbox ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS , nbox );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
GLint n = 0;
for ( ; i < nr ; i++ ) {
@@ -916,8 +916,8 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
*/
if (dPriv->numClipRects)
{
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
b[0] = box[0];
rmesa->sarea->nbox = 1;
}
@@ -971,7 +971,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
CARD32 clear;
GLuint flags = 0;
@@ -1034,7 +1034,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
int ret;
if (rmesa->dri.screen->drmMinor >= 4) {
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_LAST_CLEAR;
gp.value = (int *)&clear;
@@ -1050,7 +1050,7 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
}
#endif
if ( ret ) {
- fprintf( stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, ret );
+ fprintf( stderr, "%s: drm_radeon_getparam_t: %d\n", __FUNCTION__, ret );
exit(1);
}
if ( RADEON_DEBUG & DEBUG_IOCTL ) {
@@ -1071,10 +1071,10 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
for ( i = 0 ; i < dPriv->numClipRects ; ) {
GLint nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, dPriv->numClipRects );
- XF86DRIClipRectPtr box = dPriv->pClipRects;
- XF86DRIClipRectPtr b = rmesa->sarea->boxes;
- drmRadeonClearType clear;
- drmRadeonClearRect depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
+ drm_clip_rect_t *box = dPriv->pClipRects;
+ drm_clip_rect_t *b = rmesa->sarea->boxes;
+ drm_radeon_clear_t clear;
+ drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
GLint n = 0;
if ( !all ) {
@@ -1117,16 +1117,16 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
n--;
b = rmesa->sarea->boxes;
for ( ; n >= 0 ; n-- ) {
- depth_boxes[n].f[RADEON_CLEAR_X1] = (float)b[n].x1;
- depth_boxes[n].f[RADEON_CLEAR_Y1] = (float)b[n].y1;
- depth_boxes[n].f[RADEON_CLEAR_X2] = (float)b[n].x2;
- depth_boxes[n].f[RADEON_CLEAR_Y2] = (float)b[n].y2;
- depth_boxes[n].f[RADEON_CLEAR_DEPTH] =
+ depth_boxes[n].f[CLEAR_X1] = (float)b[n].x1;
+ depth_boxes[n].f[CLEAR_Y1] = (float)b[n].y1;
+ depth_boxes[n].f[CLEAR_X2] = (float)b[n].x2;
+ depth_boxes[n].f[CLEAR_Y2] = (float)b[n].y2;
+ depth_boxes[n].f[CLEAR_DEPTH] =
(float)rmesa->state.depth.clear;
}
ret = drmCommandWrite( rmesa->dri.fd, DRM_RADEON_CLEAR,
- &clear, sizeof(drmRadeonClearType));
+ &clear, sizeof(drm_radeon_clear_t));
if ( ret ) {
UNLOCK_HARDWARE( rmesa );
diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c
index fb285157ab..033a45efb2 100644
--- a/src/mesa/drivers/dri/radeon/radeon_lock.c
+++ b/src/mesa/drivers/dri/radeon/radeon_lock.c
@@ -54,7 +54,7 @@ radeonUpdatePageFlipping( radeonContextPtr rmesa )
int use_back;
- rmesa->doPageFlip = rmesa->sarea->pfAllowPageFlip;
+ rmesa->doPageFlip = rmesa->sarea->pfState;
use_back = (rmesa->glCtx->Color._DrawDestMask == BACK_LEFT_BIT);
use_back ^= (rmesa->sarea->pfCurrentPage == 1);
@@ -92,7 +92,7 @@ void radeonGetLock( radeonContextPtr rmesa, GLuint flags )
{
__DRIdrawablePrivate *dPriv = rmesa->dri.drawable;
__DRIscreenPrivate *sPriv = rmesa->dri.screen;
- RADEONSAREAPrivPtr sarea = rmesa->sarea;
+ drm_radeon_sarea_t *sarea = rmesa->sarea;
drmGetLock( rmesa->dri.fd, rmesa->dri.hwContext, flags );
@@ -116,9 +116,9 @@ void radeonGetLock( radeonContextPtr rmesa, GLuint flags )
rmesa->lastStamp = dPriv->lastStamp;
}
- if ( sarea->ctxOwner != rmesa->dri.hwContext ) {
+ if ( sarea->ctx_owner != rmesa->dri.hwContext ) {
int i;
- sarea->ctxOwner = rmesa->dri.hwContext;
+ sarea->ctx_owner = rmesa->dri.hwContext;
for ( i = 0 ; i < rmesa->nr_heaps ; i++ ) {
DRI_AGE_TEXTURES( rmesa->texture_heaps[ i ] );
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 451c73cf25..11d0a33ce4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -487,8 +487,8 @@ static void dump_state( void )
static int radeon_emit_packets(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int id = (int)header.packet.packet_id;
int sz = packet[id].len;
@@ -523,8 +523,8 @@ static int radeon_emit_packets(
static int radeon_emit_scalars(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
@@ -551,8 +551,8 @@ static int radeon_emit_scalars(
static int radeon_emit_scalars2(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.scalars.count;
int *data = (int *)cmdbuf->buf;
@@ -585,8 +585,8 @@ static int radeon_emit_scalars2(
* Check: table start, end, nr, etc.
*/
static int radeon_emit_vectors(
- drmRadeonCmdHeader header,
- drmRadeonCmdBuffer *cmdbuf )
+ drm_radeon_cmd_header_t header,
+ drm_radeon_cmd_buffer_t *cmdbuf )
{
int sz = header.vectors.count;
int *data = (int *)cmdbuf->buf;
@@ -746,7 +746,7 @@ static int print_prim_and_flags( int prim )
/* build in knowledge about each packet type
*/
-static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf )
{
int cmdsz;
int *cmd = (int *)cmdbuf->buf;
@@ -907,9 +907,9 @@ static int radeon_emit_packet3( drmRadeonCmdBuffer *cmdbuf )
/* Check cliprects for bounds, then pass on to above:
*/
-static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
+static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf )
{
- XF86DRIClipRectRec *boxes = (XF86DRIClipRectRec *)cmdbuf->boxes;
+ drm_clip_rect_t *boxes = cmdbuf->boxes;
int i = 0;
if (VERBOSE && total_changed) {
@@ -937,11 +937,11 @@ static int radeon_emit_packet3_cliprect( drmRadeonCmdBuffer *cmdbuf )
int radeonSanityCmdBuffer( radeonContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes )
+ drm_clip_rect_t *boxes )
{
int idx;
- drmRadeonCmdBuffer cmdbuf;
- drmRadeonCmdHeader header;
+ drm_radeon_cmd_buffer_t cmdbuf;
+ drm_radeon_cmd_header_t header;
static int inited = 0;
if (!inited) {
@@ -951,7 +951,7 @@ int radeonSanityCmdBuffer( radeonContextPtr rmesa,
cmdbuf.buf = rmesa->store.cmd_buf;
cmdbuf.bufsz = rmesa->store.cmd_used;
- cmdbuf.boxes = (drmClipRect *)boxes;
+ cmdbuf.boxes = boxes;
cmdbuf.nbox = nbox;
while ( cmdbuf.bufsz >= sizeof(header) ) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.h b/src/mesa/drivers/dri/radeon/radeon_sanity.h
index 58e8335dd6..1ec06bc586 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.h
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.h
@@ -3,6 +3,6 @@
extern int radeonSanityCmdBuffer( radeonContextPtr rmesa,
int nbox,
- XF86DRIClipRectRec *boxes );
+ drm_clip_rect_t *boxes );
#endif
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index f9d29fc348..8552f2a73d 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -272,7 +272,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
{
int ret;
- drmRadeonGetParam gp;
+ drm_radeon_getparam_t gp;
gp.param = RADEON_PARAM_GART_BUFFER_OFFSET;
gp.value = &screen->gart_buffer_offset;
@@ -281,7 +281,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
&gp, sizeof(gp));
if (ret) {
FREE( screen );
- fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
+ fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret);
return NULL;
}
@@ -293,7 +293,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
&gp, sizeof(gp));
if (ret) {
FREE( screen );
- fprintf(stderr, "drmRadeonGetParam (RADEON_PARAM_IRQ_NR): %d\n", ret);
+ fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret);
return NULL;
}
}
@@ -385,7 +385,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16;
if ( sPriv->drmMinor >= 10 ) {
- drmRadeonSetParam sp;
+ drm_radeon_setparam_t sp;
sp.param = RADEON_SETPARAM_FB_LOCATION;
sp.value = screen->fbLocation;
@@ -401,23 +401,23 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
screen->depthOffset = dri_priv->depthOffset;
screen->depthPitch = dri_priv->depthPitch;
- screen->texOffset[RADEON_CARD_HEAP] = dri_priv->textureOffset
+ screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset
+ screen->fbLocation;
- screen->texSize[RADEON_CARD_HEAP] = dri_priv->textureSize;
- screen->logTexGranularity[RADEON_CARD_HEAP] =
+ screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize;
+ screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] =
dri_priv->log2TexGran;
if ( !screen->gartTextures.map
|| getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1;
- screen->texOffset[RADEON_GART_HEAP] = 0;
- screen->texSize[RADEON_GART_HEAP] = 0;
- screen->logTexGranularity[RADEON_GART_HEAP] = 0;
+ screen->texOffset[RADEON_GART_TEX_HEAP] = 0;
+ screen->texSize[RADEON_GART_TEX_HEAP] = 0;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0;
} else {
screen->numTexHeaps = RADEON_NR_TEX_HEAPS;
- screen->texOffset[RADEON_GART_HEAP] = screen->gart_texture_offset;
- screen->texSize[RADEON_GART_HEAP] = dri_priv->gartTexMapSize;
- screen->logTexGranularity[RADEON_GART_HEAP] =
+ screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset;
+ screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize;
+ screen->logTexGranularity[RADEON_GART_TEX_HEAP] =
dri_priv->log2GARTTexGran;
}
#ifndef _SOLO
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 4a0f6d47f2..c440b56265 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -44,10 +44,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* definitions that we need.
*/
#include "dri_util.h"
-#include "radeon_common.h"
#include "radeon_dri.h"
#include "radeon_reg.h"
-#include "radeon_sarea.h"
+#include "drm_sarea.h"
#include "xmlconfig.h"
diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c
index c4ce6b1007..700e3f2c52 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state.c
@@ -418,9 +418,9 @@ static void radeonFogfv( GLcontext *ctx, GLenum pname, const GLfloat *param )
*/
-static GLboolean intersect_rect( XF86DRIClipRectPtr out,
- XF86DRIClipRectPtr a,
- XF86DRIClipRectPtr b )
+static GLboolean intersect_rect( drm_clip_rect_t *out,
+ drm_clip_rect_t *a,
+ drm_clip_rect_t *b )
{
*out = *a;
if ( b->x1 > out->x1 ) out->x1 = b->x1;
@@ -435,7 +435,7 @@ static GLboolean intersect_rect( XF86DRIClipRectPtr out,
void radeonRecalcScissorRects( radeonContextPtr rmesa )
{
- XF86DRIClipRectPtr out;
+ drm_clip_rect_t *out;
int i;
/* Grow cliprect store?
@@ -451,7 +451,7 @@ void radeonRecalcScissorRects( radeonContextPtr rmesa )
rmesa->state.scissor.pClipRects =
MALLOC( rmesa->state.scissor.numAllocedClipRects *
- sizeof(XF86DRIClipRectRec) );
+ sizeof(drm_clip_rect_t) );
if ( rmesa->state.scissor.pClipRects == NULL ) {
rmesa->state.scissor.numAllocedClipRects = 0;
@@ -641,7 +641,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
GLuint i;
- drmRadeonStipple stipple;
+ drm_radeon_stipple_t stipple;
/* Must flip pattern upside down.
*/
@@ -658,7 +658,7 @@ static void radeonPolygonStipple( GLcontext *ctx, const GLubyte *mask )
*/
stipple.mask = rmesa->state.stipple.mask;
drmCommandWrite( rmesa->dri.fd, DRM_RADEON_STIPPLE,
- &stipple, sizeof(drmRadeonStipple) );
+ &stipple, sizeof(drm_radeon_stipple_t) );
UNLOCK_HARDWARE( rmesa );
}
@@ -1575,18 +1575,18 @@ void radeonSetCliprects( radeonContextPtr rmesa, GLenum mode )
switch ( mode ) {
case GL_FRONT_LEFT:
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
break;
case GL_BACK_LEFT:
/* Can't ignore 2d windows if we are page flipping.
*/
if ( dPriv->numBackClipRects == 0 || rmesa->doPageFlip ) {
rmesa->numClipRects = dPriv->numClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pClipRects;
+ rmesa->pClipRects = dPriv->pClipRects;
}
else {
rmesa->numClipRects = dPriv->numBackClipRects;
- rmesa->pClipRects = (XF86DRIClipRectPtr)dPriv->pBackClipRects;
+ rmesa->pClipRects = dPriv->pBackClipRects;
}
break;
default:
diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c
index c84f5fd833..f842e430e1 100644
--- a/src/mesa/drivers/dri/radeon/radeon_state_init.c
+++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c
@@ -68,7 +68,7 @@ void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
static int cmdpkt( int id )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.packet.cmd_type = RADEON_CMD_PACKET;
h.packet.packet_id = id;
@@ -77,7 +77,7 @@ static int cmdpkt( int id )
static int cmdvec( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.vectors.cmd_type = RADEON_CMD_VECTORS;
h.vectors.offset = offset;
@@ -88,7 +88,7 @@ static int cmdvec( int offset, int stride, int count )
static int cmdscl( int offset, int stride, int count )
{
- drmRadeonCmdHeader h;
+ drm_radeon_cmd_header_t h;
h.i = 0;
h.scalars.cmd_type = RADEON_CMD_SCALARS;
h.scalars.offset = offset;
@@ -443,7 +443,7 @@ void radeonInitState( radeonContextPtr rmesa )
/* Initialize the texture offset to the start of the card texture heap */
rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
- rmesa->radeonScreen->texOffset[RADEON_CARD_HEAP];
+ rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
diff --git a/src/mesa/drivers/dri/radeon/radeon_texmem.c b/src/mesa/drivers/dri/radeon/radeon_texmem.c
index c985267d6b..61f187762c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texmem.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texmem.c
@@ -183,8 +183,8 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
GLuint offset;
GLint imageWidth, imageHeight;
GLint ret;
- drmRadeonTexture tex;
- drmRadeonTexImage tmp;
+ drm_radeon_texture_t tex;
+ drm_radeon_tex_image_t tmp;
const int level = hwlevel + t->base.firstLevel;
if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
@@ -245,7 +245,7 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
t->image[face][hwlevel].data = texImage->Data;
- /* Init the DRM_RADEON_TEXTURE command / drmRadeonTexture struct.
+ /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
* NOTE: we're always use a 1KB-wide blit and I8 texture format.
* We used to use 1, 2 and 4-byte texels and used to use the texture
* width to dictate the blit width - but that won't work for compressed
@@ -267,12 +267,12 @@ static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
tex.image = &tmp;
/* copy (x,y,width,height,data) */
- memcpy( &tmp, &t->image[face][hwlevel], sizeof(drmRadeonTexImage) );
+ memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
LOCK_HARDWARE( rmesa );
do {
ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
- &tex, sizeof(drmRadeonTexture) );
+ &tex, sizeof(drm_radeon_texture_t) );
} while ( ret && errno == EAGAIN );
UNLOCK_HARDWARE( rmesa );
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.c b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
index e7414077ed..381fa658b1 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.c
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.c
@@ -21,8 +21,7 @@
#include "radeon_dri.h"
#include "radeon_macros.h"
#include "radeon_reg.h"
-#include "radeon_sarea.h"
-#include "sarea.h"
+#include "drm_sarea.h"
/* HACK - for now, put this here... */
@@ -243,14 +242,14 @@ static int RADEONEngineRestore( const DRIDriverContext *ctx )
*/
static int RADEONEngineShutdown( const DRIDriverContext *ctx )
{
- drmRadeonCPStop stop;
+ drm_radeon_cp_stop_t stop;
int ret, i;
stop.flush = 1;
stop.idle = 1;
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
if (ret == 0) {
return 0;
@@ -263,7 +262,7 @@ static int RADEONEngineShutdown( const DRIDriverContext *ctx )
i = 0;
do {
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP, &stop,
- sizeof(drmRadeonCPStop));
+ sizeof(drm_radeon_cp_stop_t));
} while (ret && errno == EBUSY && i++ < 10);
if (ret == 0) {
@@ -275,7 +274,7 @@ static int RADEONEngineShutdown( const DRIDriverContext *ctx )
stop.idle = 0;
if (drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_STOP,
- &stop, sizeof(drmRadeonCPStop))) {
+ &stop, sizeof(drm_radeon_cp_stop_t))) {
return -errno;
} else {
return 0;
@@ -441,27 +440,27 @@ static int RADEONDRIAgpInit( const DRIDriverContext *ctx, RADEONInfoPtr info)
* \return non-zero on success, or zero on failure.
*
* This function is a wrapper around the DRM_RADEON_CP_INIT command, passing
- * all the parameters in a drmRadeonInit structure.
+ * all the parameters in a drm_radeon_init_t structure.
*/
static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
RADEONInfoPtr info)
{
int cpp = ctx->bpp / 8;
- drmRadeonInit drmInfo;
+ drm_radeon_init_t drmInfo;
int ret;
- memset(&drmInfo, 0, sizeof(drmRadeonInit));
+ memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
if ( (info->ChipFamily == CHIP_FAMILY_R200) ||
(info->ChipFamily == CHIP_FAMILY_RV250) ||
(info->ChipFamily == CHIP_FAMILY_M9) ||
(info->ChipFamily == CHIP_FAMILY_RV280) )
- drmInfo.func = DRM_RADEON_INIT_R200_CP;
+ drmInfo.func = RADEON_INIT_R200_CP;
else
- drmInfo.func = DRM_RADEON_INIT_CP;
+ drmInfo.func = RADEON_INIT_CP;
/* This is the struct passed to the kernel module for its initialization */
- drmInfo.sarea_priv_offset = sizeof(XF86DRISAREARec);
+ drmInfo.sarea_priv_offset = sizeof(drm_sarea_t);
drmInfo.is_pci = 0;
drmInfo.cp_mode = RADEON_DEFAULT_CP_BM_MODE;
drmInfo.gart_size = info->gartSize*1024*1024;
@@ -483,7 +482,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
drmInfo.gart_textures_offset = info->gartTexHandle;
ret = drmCommandWrite(ctx->drmFD, DRM_RADEON_CP_INIT, &drmInfo,
- sizeof(drmRadeonInit));
+ sizeof(drm_radeon_init_t));
return ret >= 0;
}
@@ -501,7 +500,7 @@ static int RADEONDRIKernelInit( const DRIDriverContext *ctx,
static void RADEONDRIAgpHeapInit(const DRIDriverContext *ctx,
RADEONInfoPtr info)
{
- drmRadeonMemInitHeap drmHeap;
+ drm_radeon_mem_init_heap_t drmHeap;
/* Start up the simple memory manager for gart space */
drmHeap.region = RADEON_MEM_REGION_GART;
@@ -889,11 +888,11 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
/* Initialize the SAREA private data structure */
{
- RADEONSAREAPrivPtr pSAREAPriv;
- pSAREAPriv = (RADEONSAREAPrivPtr)(((char*)ctx->pSAREA) +
- sizeof(XF86DRISAREARec));
+ drm_radeon_sarea_t *pSAREAPriv;
+ pSAREAPriv = (drm_radeon_sarea_t *)(((char*)ctx->pSAREA) +
+ sizeof(drm_sarea_t));
memset(pSAREAPriv, 0, sizeof(*pSAREAPriv));
- pSAREAPriv->pfAllowPageFlip = 1;
+ pSAREAPriv->pfState = 1;
}
@@ -938,7 +937,7 @@ static int RADEONScreenInit( DRIDriverContext *ctx, RADEONInfoPtr info )
pRADEONDRI->gartTexMapSize = info->gartTexMapSize;
pRADEONDRI->log2GARTTexGran = info->log2GARTTexGran;
pRADEONDRI->gartTexOffset = info->gartTexStart;
- pRADEONDRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
+ pRADEONDRI->sarea_priv_offset = sizeof(drm_sarea_t);
/* Don't release the lock now - let the VT switch handler do it. */
diff --git a/src/mesa/drivers/dri/radeon/server/radeon_dri.h b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
index fc96deb102..9938fafa42 100644
--- a/src/mesa/drivers/dri/radeon/server/radeon_dri.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_dri.h
@@ -40,7 +40,8 @@
#define _RADEON_DRI_
#include "xf86drm.h"
-#include "radeon_common.h"
+#include "drm.h"
+#include "radeon_drm.h"
/* DRI Driver defaults */
#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 08:05:03 +0000