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Diffstat (limited to 'src/mesa/pipe/cell/spu/spu_tri.c')
-rw-r--r--src/mesa/pipe/cell/spu/spu_tri.c138
1 files changed, 94 insertions, 44 deletions
diff --git a/src/mesa/pipe/cell/spu/spu_tri.c b/src/mesa/pipe/cell/spu/spu_tri.c
index ddd5e662d2..1d73c5171c 100644
--- a/src/mesa/pipe/cell/spu/spu_tri.c
+++ b/src/mesa/pipe/cell/spu/spu_tri.c
@@ -217,8 +217,8 @@ static INLINE void
eval_z( struct setup_stage *setup,
float x, float y, float result[4])
{
- uint slot = 0;
- uint i = 2;
+ const uint slot = 0;
+ const uint i = 2;
const float *dadx = setup->coef[slot].dadx;
const float *dady = setup->coef[slot].dady;
@@ -252,78 +252,128 @@ pack_color(const float color[4])
}
-/**
- * Emit a quad (pass to next stage). No clipping is done.
- */
-static INLINE void
-emit_quad( struct setup_stage *setup, int x, int y, unsigned mask )
+static uint
+do_depth_test(struct setup_stage *setup, int x, int y, unsigned mask)
{
-#if 0
- struct softpipe_context *sp = setup->softpipe;
- setup->quad.x0 = x;
- setup->quad.y0 = y;
- setup->quad.mask = mask;
- sp->quad.first->run(sp->quad.first, &setup->quad);
-#else
- /* Cell: "write" quad fragments to the tile by setting prim color */
int ix = x - setup->cliprect_minx;
int iy = y - setup->cliprect_miny;
- float colors[4][4];
- uint z;
+ float zvals[4];
+
+ eval_z(setup, (float) x, (float) y, zvals);
+
+ if (tile_status_z[setup->ty][setup->tx] == TILE_STATUS_CLEAR) {
+ /* now, _really_ clear the tile */
+ clear_z_tile(&ztile);
+ }
+ else {
+ /* make sure we've got the tile from main mem */
+ wait_on_mask(1 << TAG_READ_TILE_Z);
+ }
+ tile_status_z[setup->ty][setup->tx] = TILE_STATUS_DIRTY;
- eval_coeff(setup, 1, (float) x, (float) y, colors);
if (spu.fb.depth_format == PIPE_FORMAT_Z16_UNORM) {
- float zvals[4];
- eval_z(setup, (float) x, (float) y, zvals);
+ const float zscale = 65535.0;
+ if (mask & MASK_TOP_LEFT) {
+ uint z = (uint) (zvals[0] * zscale);
+ if (z < ztile.t16[iy][ix])
+ ztile.t16[iy][ix] = z;
+ else
+ mask &= ~MASK_TOP_LEFT;
+ }
- if (tile_status_z[setup->ty][setup->tx] == TILE_STATUS_CLEAR) {
- /* now, _really_ clear the tile */
- clear_tile_z(ztile, spu.fb.depth_clear_value);
+ if (mask & MASK_TOP_RIGHT) {
+ uint z = (uint) (zvals[1] * zscale);
+ if (z < ztile.t16[iy][ix+1])
+ ztile.t16[iy][ix+1] = z;
+ else
+ mask &= ~MASK_TOP_RIGHT;
}
- else {
- /* make sure we've got the tile from main mem */
- wait_on_mask(1 << TAG_READ_TILE_Z);
+
+ if (mask & MASK_BOTTOM_LEFT) {
+ uint z = (uint) (zvals[2] * zscale);
+ if (z < ztile.t16[iy+1][ix])
+ ztile.t16[iy+1][ix] = z;
+ else
+ mask &= ~MASK_BOTTOM_LEFT;
}
- tile_status_z[setup->ty][setup->tx] = TILE_STATUS_DIRTY;
+ if (mask & MASK_BOTTOM_RIGHT) {
+ uint z = (uint) (zvals[3] * zscale);
+ if (z < ztile.t16[iy+1][ix+1])
+ ztile.t16[iy+1][ix+1] = z;
+ else
+ mask &= ~MASK_BOTTOM_RIGHT;
+ }
+ }
+ else {
+ const float zscale = (float) 0xffffffff;
+ ASSERT(spu.fb.depth_format == PIPE_FORMAT_Z32_UNORM);
if (mask & MASK_TOP_LEFT) {
- z = (uint) (zvals[0] * 65535.0);
- if (z < ztile[iy][ix])
- ztile[iy][ix] = z;
+ uint z = (uint) (zvals[0] * zscale);
+ if (z < ztile.t32[iy][ix])
+ ztile.t32[iy][ix] = z;
else
mask &= ~MASK_TOP_LEFT;
}
if (mask & MASK_TOP_RIGHT) {
- z = (uint) (zvals[1] * 65535.0);
- if (z < ztile[iy][ix+1])
- ztile[iy][ix+1] = z;
+ uint z = (uint) (zvals[1] * zscale);
+ if (z < ztile.t32[iy][ix+1])
+ ztile.t32[iy][ix+1] = z;
else
mask &= ~MASK_TOP_RIGHT;
}
if (mask & MASK_BOTTOM_LEFT) {
- z = (uint) (zvals[2] * 65535.0);
- if (z < ztile[iy+1][ix])
- ztile[iy+1][ix] = z;
+ uint z = (uint) (zvals[2] * zscale);
+ if (z < ztile.t32[iy+1][ix])
+ ztile.t32[iy+1][ix] = z;
else
mask &= ~MASK_BOTTOM_LEFT;
}
if (mask & MASK_BOTTOM_RIGHT) {
- z = (uint) (zvals[3] * 65535.0);
- if (z < ztile[iy+1][ix+1])
- ztile[iy+1][ix+1] = z;
+ uint z = (uint) (zvals[3] * zscale);
+ if (z < ztile.t32[iy+1][ix+1])
+ ztile.t32[iy+1][ix+1] = z;
else
mask &= ~MASK_BOTTOM_RIGHT;
}
}
+ return mask;
+}
+
+
+/**
+ * Emit a quad (pass to next stage). No clipping is done.
+ */
+static INLINE void
+emit_quad( struct setup_stage *setup, int x, int y, unsigned mask )
+{
+#if 0
+ struct softpipe_context *sp = setup->softpipe;
+ setup->quad.x0 = x;
+ setup->quad.y0 = y;
+ setup->quad.mask = mask;
+ sp->quad.first->run(sp->quad.first, &setup->quad);
+#else
+ /* Cell: "write" quad fragments to the tile by setting prim color */
+ const int ix = x - setup->cliprect_minx;
+ const int iy = y - setup->cliprect_miny;
+ float colors[4][4];
+
+ eval_coeff(setup, 1, (float) x, (float) y, colors);
+
+ if (spu.depth_stencil.depth.enabled) {
+ mask &= do_depth_test(setup, x, y, mask);
+ }
+
if (mask) {
if (tile_status[setup->ty][setup->tx] == TILE_STATUS_CLEAR) {
/* now, _really_ clear the tile */
- clear_tile(ctile, spu.fb.color_clear_value);
+ clear_c_tile(&ctile);
}
else {
/* make sure we've got the tile from main mem */
@@ -332,13 +382,13 @@ emit_quad( struct setup_stage *setup, int x, int y, unsigned mask )
tile_status[setup->ty][setup->tx] = TILE_STATUS_DIRTY;
if (mask & MASK_TOP_LEFT)
- ctile[iy][ix] = pack_color(colors[QUAD_TOP_LEFT]);
+ ctile.t32[iy][ix] = pack_color(colors[QUAD_TOP_LEFT]);
if (mask & MASK_TOP_RIGHT)
- ctile[iy][ix+1] = pack_color(colors[QUAD_TOP_RIGHT]);
+ ctile.t32[iy][ix+1] = pack_color(colors[QUAD_TOP_RIGHT]);
if (mask & MASK_BOTTOM_LEFT)
- ctile[iy+1][ix] = pack_color(colors[QUAD_BOTTOM_LEFT]);
+ ctile.t32[iy+1][ix] = pack_color(colors[QUAD_BOTTOM_LEFT]);
if (mask & MASK_BOTTOM_RIGHT)
- ctile[iy+1][ix+1] = pack_color(colors[QUAD_BOTTOM_RIGHT]);
+ ctile.t32[iy+1][ix+1] = pack_color(colors[QUAD_BOTTOM_RIGHT]);
}
#endif
}
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