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-rw-r--r--src/mesa/pipe/i965simple/brw_batch.h2
-rw-r--r--src/mesa/pipe/i965simple/brw_clip.c5
-rw-r--r--src/mesa/pipe/i965simple/brw_context.h5
-rw-r--r--src/mesa/pipe/i965simple/brw_curbe.c36
-rw-r--r--src/mesa/pipe/i965simple/brw_flush.c20
-rw-r--r--src/mesa/pipe/i965simple/brw_misc_state.c115
-rw-r--r--src/mesa/pipe/i965simple/brw_sf.c4
-rw-r--r--src/mesa/pipe/i965simple/brw_sf_emit.c2
-rw-r--r--src/mesa/pipe/i965simple/brw_sf_state.c8
-rw-r--r--src/mesa/pipe/i965simple/brw_state.h6
-rw-r--r--src/mesa/pipe/i965simple/brw_state_upload.c7
-rw-r--r--src/mesa/pipe/i965simple/brw_urb.c3
-rw-r--r--src/mesa/pipe/i965simple/brw_vs_emit.c49
-rw-r--r--src/mesa/pipe/i965simple/brw_wm_decl.c2
-rw-r--r--src/mesa/pipe/i965simple/brw_wm_glsl.c4
-rw-r--r--src/mesa/pipe/i965simple/brw_wm_sampler_state.c3
-rw-r--r--src/mesa/pipe/i965simple/brw_wm_surface_state.c48
17 files changed, 209 insertions, 110 deletions
diff --git a/src/mesa/pipe/i965simple/brw_batch.h b/src/mesa/pipe/i965simple/brw_batch.h
index bef69ac871..8605d7c108 100644
--- a/src/mesa/pipe/i965simple/brw_batch.h
+++ b/src/mesa/pipe/i965simple/brw_batch.h
@@ -53,4 +53,6 @@
brw->hardware_dirty = ~0; \
} while (0)
+#define BRW_BATCH_STRUCT(brw, s) brw_batchbuffer_data( brw->winsys, (s), sizeof(*(s)))
+
#endif
diff --git a/src/mesa/pipe/i965simple/brw_clip.c b/src/mesa/pipe/i965simple/brw_clip.c
index fc86e0a446..268124cc53 100644
--- a/src/mesa/pipe/i965simple/brw_clip.c
+++ b/src/mesa/pipe/i965simple/brw_clip.c
@@ -154,6 +154,8 @@ static void upload_clip_prog(struct brw_context *brw)
key.do_flat_shading = (brw->attribs.Raster->flatshade);
/* BRW_NEW_CLIP */
key.nr_userclip = brw->attribs.Clip.nr; /* XXX */
+
+#if 0
key.clip_mode = BRW_CLIPMODE_NORMAL;
if (key.primitive == PIPE_PRIM_TRIANGLES) {
@@ -185,6 +187,9 @@ static void upload_clip_prog(struct brw_context *brw)
}
}
}
+#else
+ key.clip_mode = BRW_CLIPMODE_ACCEPT_ALL;
+#endif
if (!search_cache(brw, &key))
compile_clip_prog( brw, &key );
diff --git a/src/mesa/pipe/i965simple/brw_context.h b/src/mesa/pipe/i965simple/brw_context.h
index fc2cb055e9..139f13ad4e 100644
--- a/src/mesa/pipe/i965simple/brw_context.h
+++ b/src/mesa/pipe/i965simple/brw_context.h
@@ -327,6 +327,9 @@ struct brw_vs_prog_data {
unsigned max_const;
+ float imm_buf[PIPE_MAX_CONSTANT][4];
+ unsigned num_imm;
+
/* Used for calculating urb partitions:
*/
unsigned urb_entry_size;
@@ -666,8 +669,6 @@ void brwUpdateTextureState( struct brw_context *brw );
void brw_upload_urb_fence(struct brw_context *brw);
void brw_upload_constant_buffer_state(struct brw_context *brw);
-void brw_upload_polygon_stipple(struct brw_context *brw);
-void brw_upload_line_stipple(struct brw_context *brw);
void brw_init_surface_functions(struct brw_context *brw);
void brw_init_state_functions(struct brw_context *brw);
diff --git a/src/mesa/pipe/i965simple/brw_curbe.c b/src/mesa/pipe/i965simple/brw_curbe.c
index 66a04b9c38..603116c863 100644
--- a/src/mesa/pipe/i965simple/brw_curbe.c
+++ b/src/mesa/pipe/i965simple/brw_curbe.c
@@ -34,9 +34,11 @@
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
+#include "brw_batch.h"
#include "brw_util.h"
#include "brw_wm.h"
#include "pipe/p_state.h"
+#include "pipe/p_winsys.h"
#include "pipe/p_util.h"
#define FILE_DEBUG_FLAG DEBUG_FALLBACKS
@@ -174,7 +176,7 @@ static void upload_constant_buffer(struct brw_context *brw)
{
struct brw_mem_pool *pool = &brw->pool[BRW_GS_POOL];
unsigned sz = brw->curbe.total_size;
- unsigned bufsz = sz * 16 * sizeof(float);
+ unsigned bufsz = sz * sizeof(float);
float *buf;
unsigned i;
@@ -246,17 +248,31 @@ static void upload_constant_buffer(struct brw_context *brw)
if (brw->curbe.vs_size) {
-// unsigned offset = brw->curbe.vs_start * 16;
-// unsigned nr = vp->max_const;
-
- /* map the vertex constant buffer and copy to curbe: */
-
-// assert(nr == 0);
- assert(0);
+ unsigned offset = brw->curbe.vs_start * 16;
+ /*unsigned nr = vp->max_const;*/
+ const struct pipe_constant_buffer *cbuffer = brw->attribs.Constants[0];
+ struct pipe_winsys *ws = brw->pipe.winsys;
+ if (cbuffer->size) {
+ /* map the vertex constant buffer and copy to curbe: */
+ ws->buffer_map(ws, cbuffer->buffer, 0);
+ ws->buffer_get_subdata(ws, cbuffer->buffer,
+ 0,
+ cbuffer->size,
+ &buf[offset]);
+ ws->buffer_unmap(ws, cbuffer->buffer);
+ offset += cbuffer->size;
+ }
+ /*immediates*/
+#if 0
+ if (brw->vs.prog_data->num_imm) {
+ memcpy(&buf[offset], brw->vs.prog_data->imm_buf,
+ brw->vs.prog_data->num_imm * 4 * sizeof(float));
+ }
+#endif
}
- if (0) {
- for (i = 0; i < sz*16; i+=4)
+ if (1) {
+ for (i = 0; i < sz; i+=4)
_mesa_printf("curbe %d.%d: %f %f %f %f\n", i/8, i&4,
buf[i+0], buf[i+1], buf[i+2], buf[i+3]);
diff --git a/src/mesa/pipe/i965simple/brw_flush.c b/src/mesa/pipe/i965simple/brw_flush.c
index 1f11c5f164..5216c680cf 100644
--- a/src/mesa/pipe/i965simple/brw_flush.c
+++ b/src/mesa/pipe/i965simple/brw_flush.c
@@ -49,22 +49,18 @@ static void brw_flush( struct pipe_context *pipe,
* caches?
*/
if (flags & (PIPE_FLUSH_RENDER_CACHE | PIPE_FLUSH_TEXTURE_CACHE)) {
- unsigned flush = CMD_MI_FLUSH;
-
-#if 0
+ struct brw_mi_flush flush;
+
+ memset(&flush, 0, sizeof(flush));
+ flush.opcode = CMD_MI_FLUSH;
+
if (!(flags & PIPE_FLUSH_RENDER_CACHE))
- flush |= INHIBIT_FLUSH_RENDER_CACHE;
+ flush.flags |= BRW_INHIBIT_FLUSH_RENDER_CACHE;
if (flags & PIPE_FLUSH_TEXTURE_CACHE)
- flush |= FLUSH_MAP_CACHE;
-#endif
+ flush.flags |= BRW_FLUSH_READ_CACHE;
- if (!BEGIN_BATCH(1, 0)) {
- FLUSH_BATCH( &fence );
- assert(BEGIN_BATCH(1, 0));
- }
- OUT_BATCH( flush );
- ADVANCE_BATCH();
+ BRW_BATCH_STRUCT(brw, &flush);
}
/* If there are no flags, just flush pending commands to hardware:
diff --git a/src/mesa/pipe/i965simple/brw_misc_state.c b/src/mesa/pipe/i965simple/brw_misc_state.c
index e600e9d8de..13b3b1671d 100644
--- a/src/mesa/pipe/i965simple/brw_misc_state.c
+++ b/src/mesa/pipe/i965simple/brw_misc_state.c
@@ -42,7 +42,7 @@
* Blend color
*/
-void brw_upload_blend_constant_color(struct brw_context *brw)
+static void upload_blend_constant_color(struct brw_context *brw)
{
struct brw_blend_constant_color bcc;
@@ -58,6 +58,46 @@ void brw_upload_blend_constant_color(struct brw_context *brw)
}
+const struct brw_tracked_state brw_blend_constant_color = {
+ .dirty = {
+ .brw = BRW_NEW_BLEND,
+ .cache = 0
+ },
+ .update = upload_blend_constant_color
+};
+
+
+/***********************************************************************
+ * Drawing rectangle
+ */
+static void upload_drawing_rect(struct brw_context *brw)
+{
+ struct brw_drawrect bdr;
+
+ memset(&bdr, 0, sizeof(bdr));
+ bdr.header.opcode = CMD_DRAW_RECT;
+ bdr.header.length = sizeof(bdr)/4 - 2;
+ bdr.xmin = 0;
+ bdr.ymin = 0;
+ bdr.xmax = brw->attribs.FrameBuffer.cbufs[0]->width;
+ bdr.ymax = brw->attribs.FrameBuffer.cbufs[0]->height;
+ bdr.xorg = 0;
+ bdr.yorg = 0;
+
+ /* Can't use BRW_CACHED_BATCH_STRUCT because this is also emitted
+ * uncached in brw_draw.c:
+ */
+ BRW_BATCH_STRUCT(brw, &bdr);
+}
+
+const struct brw_tracked_state brw_drawing_rect = {
+ .dirty = {
+ .brw = BRW_NEW_SCENE,
+ .cache = 0
+ },
+ .update = upload_drawing_rect
+};
+
/**
* Upload the binding table pointers, which point each stage's array of surface
* state pointers.
@@ -117,7 +157,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw )
psp.gs.enable = 1;
}
- {
+ if (0) {
psp.clp.offset = brw->clip.state_gs_offset >> 5;
psp.clp.enable = 1;
}
@@ -216,7 +256,7 @@ static void upload_depthbuffer(struct brw_context *brw)
const struct brw_tracked_state brw_depthbuffer = {
.dirty = {
- .brw = 0,
+ .brw = BRW_NEW_SCENE,
.cache = 0
},
.update = upload_depthbuffer,
@@ -224,50 +264,43 @@ const struct brw_tracked_state brw_depthbuffer = {
-/***********************************************************************
- * Polygon stipple offset packet
- */
-
-static void upload_polygon_stipple_offset(struct brw_context *brw)
-{
- struct brw_polygon_stipple_offset bpso;
-
- memset(&bpso, 0, sizeof(bpso));
- bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
- bpso.header.length = sizeof(bpso)/4-2;
-
- bpso.bits0.x_offset = 0;
- bpso.bits0.y_offset = 0;
-
- BRW_CACHED_BATCH_STRUCT(brw, &bpso);
-}
/***********************************************************************
* Polygon stipple packet
*/
-void brw_upload_polygon_stipple(struct brw_context *brw)
+static void upload_polygon_stipple(struct brw_context *brw)
{
struct brw_polygon_stipple bps;
unsigned i;
- /*update the offset at the same time it will always be 0*/
- upload_polygon_stipple_offset(brw);
memset(&bps, 0, sizeof(bps));
bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
bps.header.length = sizeof(bps)/4-2;
- for (i = 0; i < 32; i++)
- bps.stipple[i] = brw->attribs.PolygonStipple->stipple[31 - i]; /* invert */
+ /* XXX: state tracker should send *all* state down initially!
+ */
+ if (brw->attribs.PolygonStipple)
+ for (i = 0; i < 32; i++)
+ bps.stipple[i] = brw->attribs.PolygonStipple->stipple[31 - i]; /* invert */
BRW_CACHED_BATCH_STRUCT(brw, &bps);
}
+const struct brw_tracked_state brw_polygon_stipple = {
+ .dirty = {
+ .brw = BRW_NEW_STIPPLE,
+ .cache = 0
+ },
+ .update = upload_polygon_stipple
+};
+
+
/***********************************************************************
* Line stipple packet
*/
-void brw_upload_line_stipple(struct brw_context *brw)
+static void upload_line_stipple(struct brw_context *brw)
{
struct brw_line_stipple bls;
float tmp;
@@ -289,6 +322,14 @@ void brw_upload_line_stipple(struct brw_context *brw)
BRW_CACHED_BATCH_STRUCT(brw, &bls);
}
+const struct brw_tracked_state brw_line_stipple = {
+ .dirty = {
+ .brw = BRW_NEW_STIPPLE,
+ .cache = 0
+ },
+ .update = upload_line_stipple
+};
+
/***********************************************************************
* Misc constant state packets
@@ -329,6 +370,15 @@ const struct brw_tracked_state brw_pipe_control = {
static void upload_invarient_state( struct brw_context *brw )
{
{
+ struct brw_mi_flush flush;
+
+ memset(&flush, 0, sizeof(flush));
+ flush.opcode = CMD_MI_FLUSH;
+ flush.flags = BRW_FLUSH_STATE_CACHE | BRW_FLUSH_READ_CACHE;
+ BRW_BATCH_STRUCT(brw, &flush);
+ }
+
+ {
/* 0x61040000 Pipeline Select */
/* PipelineSelect : 0 */
struct brw_pipeline_select ps;
@@ -376,6 +426,19 @@ static void upload_invarient_state( struct brw_context *brw )
BRW_BATCH_STRUCT(brw, &vfs);
}
+
+
+ {
+ struct brw_polygon_stipple_offset bpso;
+
+ memset(&bpso, 0, sizeof(bpso));
+ bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
+ bpso.header.length = sizeof(bpso)/4-2;
+ bpso.bits0.x_offset = 0;
+ bpso.bits0.y_offset = 0;
+
+ BRW_BATCH_STRUCT(brw, &bpso);
+ }
}
const struct brw_tracked_state brw_invarient_state = {
diff --git a/src/mesa/pipe/i965simple/brw_sf.c b/src/mesa/pipe/i965simple/brw_sf.c
index e7c02beda5..7b6fd3fff6 100644
--- a/src/mesa/pipe/i965simple/brw_sf.c
+++ b/src/mesa/pipe/i965simple/brw_sf.c
@@ -128,6 +128,10 @@ static void upload_sf_prog( struct brw_context *brw )
/* CACHE_NEW_VS_PROG */
key.vp_output_count = brw->vs.prog_data->outputs_written;
+ /* BRW_NEW_FS */
+ key.fp_input_count = brw->attribs.FragmentProgram->info.nr_regs[TGSI_FILE_INPUT];
+
+
/* BRW_NEW_REDUCED_PRIMITIVE */
switch (brw->reduced_primitive) {
case PIPE_PRIM_TRIANGLES:
diff --git a/src/mesa/pipe/i965simple/brw_sf_emit.c b/src/mesa/pipe/i965simple/brw_sf_emit.c
index 834b5efdfe..0fa61f14b6 100644
--- a/src/mesa/pipe/i965simple/brw_sf_emit.c
+++ b/src/mesa/pipe/i965simple/brw_sf_emit.c
@@ -148,7 +148,7 @@ static boolean calculate_masks( struct brw_sf_compile *c,
/* Maybe only processs one attribute on the final round:
*/
- if (reg*2+1 < c->nr_setup_attrs) {
+ if (1 || reg*2+1 < c->nr_setup_attrs) {
*pc |= 0xf0;
// if (persp_mask & (1 << c->idx_to_attr[reg*2+1]))
diff --git a/src/mesa/pipe/i965simple/brw_sf_state.c b/src/mesa/pipe/i965simple/brw_sf_state.c
index 0de6e7240e..9acd3ea61b 100644
--- a/src/mesa/pipe/i965simple/brw_sf_state.c
+++ b/src/mesa/pipe/i965simple/brw_sf_state.c
@@ -58,9 +58,9 @@ static void upload_sf_vp(struct brw_context *brw)
/* _NEW_SCISSOR */
sfv.scissor.xmin = brw->attribs.Scissor.minx;
- sfv.scissor.xmax = brw->attribs.Scissor.maxx;
+ sfv.scissor.xmax = brw->attribs.Scissor.maxx - 1;
sfv.scissor.ymin = brw->attribs.Scissor.miny;
- sfv.scissor.ymax = brw->attribs.Scissor.maxy;
+ sfv.scissor.ymax = brw->attribs.Scissor.maxy - 1;
brw->sf.vp_gs_offset = brw_cache_data( &brw->cache[BRW_SF_VP], &sfv );
}
@@ -133,7 +133,7 @@ static void upload_sf_unit( struct brw_context *brw )
else
sf.sf6.cull_mode = BRW_CULLMODE_NONE;
#else
- sf.sf5.front_winding = BRW_FRONTWINDING_CW;
+ sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
sf.sf6.cull_mode = BRW_CULLMODE_NONE;
#endif
@@ -149,7 +149,7 @@ static void upload_sf_unit( struct brw_context *brw )
sf.sf7.sprite_point = brw->attribs.Raster->point_sprite;
sf.sf7.point_size = CLAMP(brw->attribs.Raster->line_width, 1.0, 255.0) * (1<<3);
- sf.sf7.use_point_size_state = brw->attribs.Raster->point_size_per_vertex;
+ sf.sf7.use_point_size_state = !brw->attribs.Raster->point_size_per_vertex;
/* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
*/
diff --git a/src/mesa/pipe/i965simple/brw_state.h b/src/mesa/pipe/i965simple/brw_state.h
index d09711f6f0..8b4d7aabf0 100644
--- a/src/mesa/pipe/i965simple/brw_state.h
+++ b/src/mesa/pipe/i965simple/brw_state.h
@@ -65,7 +65,6 @@ const struct brw_tracked_state brw_urb_fence;
const struct brw_tracked_state brw_vertex_state;
const struct brw_tracked_state brw_vs_prog;
const struct brw_tracked_state brw_vs_unit;
-const struct brw_tracked_state brw_wm_input_sizes;
const struct brw_tracked_state brw_wm_prog;
const struct brw_tracked_state brw_wm_samplers;
const struct brw_tracked_state brw_wm_surfaces;
@@ -116,7 +115,6 @@ static inline struct pipe_buffer_handle *brw_cache_buffer(struct brw_context *br
/***********************************************************************
* brw_state_batch.c
*/
-#define BRW_BATCH_STRUCT(brw, s) brw_batchbuffer_data( brw->winsys, (s), sizeof(*(s)))
#define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) )
boolean brw_cached_batch_struct( struct brw_context *brw,
@@ -149,10 +147,6 @@ void brw_clear_all_caches( struct brw_context *brw );
void brw_invalidate_pools( struct brw_context *brw );
void brw_clear_batch_cache_flush( struct brw_context *brw );
-void brw_upload_cc_unit(struct brw_context *brw);
-void brw_upload_clip_prog(struct brw_context *brw);
-void brw_upload_blend_constant_color(struct brw_context *brw);
-void brw_upload_wm_samplers(struct brw_context *brw);
/* brw_shader_info.c
*/
diff --git a/src/mesa/pipe/i965simple/brw_state_upload.c b/src/mesa/pipe/i965simple/brw_state_upload.c
index 2502e54929..e727601e1e 100644
--- a/src/mesa/pipe/i965simple/brw_state_upload.c
+++ b/src/mesa/pipe/i965simple/brw_state_upload.c
@@ -43,7 +43,6 @@
*/
const struct brw_tracked_state *atoms[] =
{
- &brw_wm_input_sizes,
&brw_vs_prog,
&brw_gs_prog,
&brw_clip_prog,
@@ -84,8 +83,6 @@ const struct brw_tracked_state *atoms[] =
&brw_depthbuffer,
&brw_polygon_stipple,
- &brw_polygon_stipple_offset,
-
&brw_line_stipple,
&brw_psp_urb_cbs,
@@ -192,6 +189,10 @@ void brw_validate_state( struct brw_context *brw )
for (i = 0; i < Elements(atoms); i++) {
const struct brw_tracked_state *atom = atoms[i];
+ assert(atom->dirty.brw ||
+ atom->dirty.cache);
+ assert(atom->update);
+
if (check_state(state, &atom->dirty))
atom->update( brw );
}
diff --git a/src/mesa/pipe/i965simple/brw_urb.c b/src/mesa/pipe/i965simple/brw_urb.c
index 8cc86e26a3..b284526aa6 100644
--- a/src/mesa/pipe/i965simple/brw_urb.c
+++ b/src/mesa/pipe/i965simple/brw_urb.c
@@ -31,7 +31,8 @@
#include "brw_context.h"
-#include "brw_state.h"
+//#include "brw_state.h"
+#include "brw_batch.h"
#include "brw_defines.h"
#define VS 0
diff --git a/src/mesa/pipe/i965simple/brw_vs_emit.c b/src/mesa/pipe/i965simple/brw_vs_emit.c
index f4d61eade0..f3507f60f7 100644
--- a/src/mesa/pipe/i965simple/brw_vs_emit.c
+++ b/src/mesa/pipe/i965simple/brw_vs_emit.c
@@ -38,6 +38,7 @@
struct brw_prog_info {
unsigned num_temps;
unsigned num_addrs;
+ unsigned num_consts;
unsigned writes_psize;
@@ -74,25 +75,21 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c,
/* Vertex program parameters from curbe:
*/
- nr_params = c->vp->program.num_inputs; /*FIXME: i think this is wrong... */
+ nr_params = c->prog_data.max_const;
for (i = 0; i < nr_params; i++) {
- c->regs[TGSI_FILE_INPUT][i] = stride( brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1);
+ c->regs[TGSI_FILE_CONSTANT][i] = stride(brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1);
}
reg += (nr_params+1)/2;
-
c->prog_data.curb_read_length = reg - 1;
/* Allocate input regs:
*/
- c->nr_inputs = 0;
- for (i = 0; i < PIPE_ATTRIB_MAX; i++) {
- if (c->prog_data.inputs_read & (1<<i)) {
- c->nr_inputs++;
+ c->nr_inputs = c->vp->program.num_inputs;
+ for (i = 0; i < c->nr_inputs; i++) {
c->regs[TGSI_FILE_INPUT][i] = brw_vec8_grf(reg, 0);
reg++;
- }
}
@@ -119,9 +116,14 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c,
mrf++;
}
#else
- /* for now stuff everything in grf */
- c->regs[TGSI_FILE_OUTPUT][i] = brw_vec8_grf(reg, 0);
- reg++;
+ /*treat pos differently for now */
+ if (i == info->pos_idx) {
+ c->regs[TGSI_FILE_OUTPUT][i] = brw_vec8_grf(reg, 0);
+ reg++;
+ } else {
+ c->regs[TGSI_FILE_OUTPUT][i] = brw_message_reg(mrf);
+ mrf++;
+ }
#endif
}
@@ -625,9 +627,12 @@ static struct brw_reg get_reg( struct brw_vs_compile *c,
case TGSI_FILE_TEMPORARY:
case TGSI_FILE_INPUT:
case TGSI_FILE_OUTPUT:
- case TGSI_FILE_CONSTANT:
assert(c->regs[file][index].nr != 0);
return c->regs[file][index];
+ case TGSI_FILE_CONSTANT:
+ case TGSI_FILE_IMMEDIATE:
+ assert(c->regs[TGSI_FILE_CONSTANT][index].nr != 0);
+ return c->regs[TGSI_FILE_CONSTANT][index];
case TGSI_FILE_ADDRESS:
assert(index == 0);
return c->regs[file][index];
@@ -983,6 +988,13 @@ static void process_declaration(const struct tgsi_full_declaration *decl,
{
switch(decl->Declaration.File) {
case TGSI_FILE_CONSTANT: {
+ if (decl->Declaration.Declare == TGSI_DECLARE_MASK) {
+ printf("DECLARATION MASK = %d\n",
+ decl->u.DeclarationMask.Mask);
+ assert(0);
+ } else { /*range*/
+ info->num_consts += decl->u.DeclarationRange.Last - decl->u.DeclarationRange.First + 1;
+ }
}
break;
case TGSI_FILE_INPUT: {
@@ -1061,7 +1073,7 @@ static void process_instruction(struct brw_vs_compile *c,
struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
index = src->SrcRegister.Index;
file = src->SrcRegister.File;
- if (file == TGSI_FILE_OUTPUT&&c->output_regs[index].used_in_src)
+ if (file == TGSI_FILE_OUTPUT && c->output_regs[index].used_in_src)
args[i] = c->output_regs[index].reg;
else
args[i] = get_arg(c, &src->SrcRegister);
@@ -1289,6 +1301,14 @@ void brw_vs_emit(struct brw_vs_compile *c)
}
break;
case TGSI_TOKEN_TYPE_IMMEDIATE: {
+ int i;
+ struct tgsi_full_immediate *imm = &parse.FullToken.FullImmediate;
+ /*assert(imm->Immediate.Size == 4);*/
+ c->prog_data.imm_buf[c->prog_data.num_imm][0] = imm->u.ImmediateFloat32[0].Float;
+ c->prog_data.imm_buf[c->prog_data.num_imm][1] = imm->u.ImmediateFloat32[1].Float;
+ c->prog_data.imm_buf[c->prog_data.num_imm][2] = imm->u.ImmediateFloat32[2].Float;
+ c->prog_data.imm_buf[c->prog_data.num_imm][3] = imm->u.ImmediateFloat32[3].Float;
+ c->prog_data.num_imm++;
}
break;
case TGSI_TOKEN_TYPE_INSTRUCTION: {
@@ -1297,12 +1317,12 @@ void brw_vs_emit(struct brw_vs_compile *c)
/* first instruction (declerations finished).
* now that we know what vars are being used allocate
* registers for them.*/
+ c->prog_data.max_const = prog_info.num_consts + c->prog_data.num_imm;
brw_vs_alloc_regs(c, &prog_info);
brw_set_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
brw_set_access_mode(p, BRW_ALIGN_16);
-
allocated_registers = 1;
}
process_instruction(c, inst, &prog_info);
@@ -1315,4 +1335,5 @@ void brw_vs_emit(struct brw_vs_compile *c)
emit_vertex_write(c, &prog_info);
post_vs_emit(c, end_inst);
tgsi_parse_free(&parse);
+
}
diff --git a/src/mesa/pipe/i965simple/brw_wm_decl.c b/src/mesa/pipe/i965simple/brw_wm_decl.c
index 392f17fad6..5b1abb9d48 100644
--- a/src/mesa/pipe/i965simple/brw_wm_decl.c
+++ b/src/mesa/pipe/i965simple/brw_wm_decl.c
@@ -9,7 +9,7 @@
static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
{
c->tmp_index++;
- c->reg_index = MAX2(c->reg_index, c->tmp_index);
+ c->reg_index = MAX2(c->reg_index, c->tmp_start + c->tmp_index);
return brw_vec8_grf(c->tmp_start + c->tmp_index, 0);
}
diff --git a/src/mesa/pipe/i965simple/brw_wm_glsl.c b/src/mesa/pipe/i965simple/brw_wm_glsl.c
index 37d5b216b2..f4b5c13c06 100644
--- a/src/mesa/pipe/i965simple/brw_wm_glsl.c
+++ b/src/mesa/pipe/i965simple/brw_wm_glsl.c
@@ -935,6 +935,7 @@ static void brw_wm_emit_instruction( struct brw_wm_compile *c,
break;
case TGSI_OPCODE_RET:
+#if 0
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_ADD(p,
@@ -944,6 +945,9 @@ static void brw_wm_emit_instruction( struct brw_wm_compile *c,
brw_MOV(p, brw_ip_reg(), deref_1ud(c->stack_index, 0));
brw_set_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
+#else
+ emit_fb_write(c, inst);
+#endif
break;
case TGSI_OPCODE_LOOP:
diff --git a/src/mesa/pipe/i965simple/brw_wm_sampler_state.c b/src/mesa/pipe/i965simple/brw_wm_sampler_state.c
index fbeea8c809..cfb430eb09 100644
--- a/src/mesa/pipe/i965simple/brw_wm_sampler_state.c
+++ b/src/mesa/pipe/i965simple/brw_wm_sampler_state.c
@@ -236,7 +236,8 @@ static void upload_wm_samplers(struct brw_context *brw)
/* BRW_NEW_SAMPLER */
for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
- if (brw->attribs.Samplers[unit]) { /* FIXME: correctly detect enabled ones */
+ /* determine unit enable/disable by looking for a bound texture */
+ if (brw->attribs.Texture[unit]) {
const struct pipe_sampler_state *sampler = brw->attribs.Samplers[unit];
unsigned sdc_gs_offset = upload_default_color(brw, sampler->border_color);
diff --git a/src/mesa/pipe/i965simple/brw_wm_surface_state.c b/src/mesa/pipe/i965simple/brw_wm_surface_state.c
index db8f670970..5c7dee5790 100644
--- a/src/mesa/pipe/i965simple/brw_wm_surface_state.c
+++ b/src/mesa/pipe/i965simple/brw_wm_surface_state.c
@@ -155,13 +155,13 @@ void brw_update_texture_surface( struct brw_context *brw,
surf.ss1.base_addr = brw_buffer_offset( brw, tObj->buffer );
surf.ss2.mip_count = tObj->base.last_level - tObj->base.first_level;
- surf.ss2.width = tObj->base.width[0];
- surf.ss2.height = tObj->base.height[0];
+ surf.ss2.width = tObj->base.width[0] - 1;
+ surf.ss2.height = tObj->base.height[0] - 1;
surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
surf.ss3.tiled_surface = 0; /* always zero */
- surf.ss3.pitch = tObj->pitch;
- surf.ss3.depth = tObj->base.depth[0];
+ surf.ss3.pitch = tObj->pitch - 1;
+ surf.ss3.depth = tObj->base.depth[0] - 1;
surf.ss4.min_lod = 0;
@@ -192,25 +192,25 @@ static void upload_wm_surfaces(struct brw_context *brw )
/* BRW_NEW_FRAMEBUFFER
*/
- struct pipe_surface *region = brw->attribs.FrameBuffer.cbufs[0];/*fixme*/
+ struct pipe_surface *pipe_surface = brw->attribs.FrameBuffer.cbufs[0];/*fixme*/
memset(&surf, 0, sizeof(surf));
- if (region != NULL) {
- if (region->cpp == 4)
+ if (pipe_surface != NULL) {
+ if (pipe_surface->cpp == 4)
surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
else
surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
surf.ss0.surface_type = BRW_SURFACE_2D;
- surf.ss1.base_addr = brw_buffer_offset( brw, region->buffer );
+ surf.ss1.base_addr = brw_buffer_offset( brw, pipe_surface->buffer );
- surf.ss2.width = region->width;
- surf.ss2.height = region->height;
+ surf.ss2.width = pipe_surface->width - 1;
+ surf.ss2.height = pipe_surface->height - 1;
surf.ss3.tile_walk = BRW_TILEWALK_XMAJOR;
surf.ss3.tiled_surface = 0;
- surf.ss3.pitch = region->pitch;
+ surf.ss3.pitch = (pipe_surface->pitch * pipe_surface->cpp) - 1;
} else {
surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
surf.ss0.surface_type = BRW_SURFACE_NULL;
@@ -221,10 +221,10 @@ static void upload_wm_surfaces(struct brw_context *brw )
brw->attribs.Blend->blend_enable);
- surf.ss0.writedisable_red = !brw->attribs.BlendColor.color[0];
- surf.ss0.writedisable_green = !brw->attribs.BlendColor.color[1];
- surf.ss0.writedisable_blue = !brw->attribs.BlendColor.color[2];
- surf.ss0.writedisable_alpha = !brw->attribs.BlendColor.color[3];
+ surf.ss0.writedisable_red = !(brw->attribs.Blend->colormask & PIPE_MASK_R);
+ surf.ss0.writedisable_green = !(brw->attribs.Blend->colormask & PIPE_MASK_G);
+ surf.ss0.writedisable_blue = !(brw->attribs.Blend->colormask & PIPE_MASK_B);
+ surf.ss0.writedisable_alpha = !(brw->attribs.Blend->colormask & PIPE_MASK_A);
@@ -235,28 +235,18 @@ static void upload_wm_surfaces(struct brw_context *brw )
}
+ /* BRW_NEW_TEXTURE
+ */
for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
const struct brw_texture *texUnit = brw->attribs.Texture[i];
- if (texUnit == NULL)
- continue;
-
- /* BRW_NEW_TEXTURE
- */
- if (texUnit->base.refcount/*(texUnit->refcount > 0) == really used */) {
+ if (texUnit &&
+ texUnit->base.refcount/*(texUnit->refcount > 0) == really used */) {
brw_update_texture_surface(brw, i);
brw->wm.nr_surfaces = i+2;
}
-#if 0
- else if( texUnit->refcount &&
- texUnit->_Current == intel->frame_buffer_texobj )
- {
- brw->wm.bind.surf_ss_offset[i+1] = brw->wm.bind.surf_ss_offset[0];
- brw->wm.nr_surfaces = i+2;
- }
-#endif
else {
brw->wm.bind.surf_ss_offset[i+1] = 0;
}
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-06 04:35:30 +0000