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-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c6
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c5
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 937f127e7c..ae252c995b 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -91,7 +91,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
FORMAT_COMP_Y_shift, FORMAT_COMP_Y_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
- FORMAT_COMP_X_shift, FORMAT_COMP_Z_mask);
+ FORMAT_COMP_Z_shift, FORMAT_COMP_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_UNSIGNED,
FORMAT_COMP_W_shift, FORMAT_COMP_W_mask);
@@ -731,8 +731,10 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
TEX_HEIGHT_shift, TEX_HEIGHT_mask);
+ t->SQ_TEX_RESOURCE2 = get_base_teximage_offset(t) / 256;
+
if ((t->maxLod - t->minLod) > 0) {
- t->SQ_TEX_RESOURCE3 = t->mt->levels[t->minLod].size / 256;
+ t->SQ_TEX_RESOURCE3 = radeon_miptree_image_offset(t->mt, 0, t->minLod + 1) / 256;
SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask);
SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
}
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index c124e02184..3bc2d2ba02 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -57,14 +57,11 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
for (i = 0; i < R700_TEXTURE_NUMBERUNITS; i++) {
if (ctx->Texture.Unit[i]._ReallyEnabled) {
radeonTexObj *t = r700->textures[i];
- uint32_t offset;
if (t) {
if (!t->image_override) {
bo = t->mt->bo;
- offset = get_base_teximage_offset(t);
} else {
bo = t->bo;
- offset = 0;
}
if (bo) {
@@ -93,7 +90,7 @@ static void r700SendTexState(GLcontext *ctx, struct radeon_state_atom *atom)
R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
bo,
- offset,
+ r700->textures[i]->SQ_TEX_RESOURCE2,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
bo,