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path: root/src/mesa/drivers/dri/i965/brw_eu.h
AgeCommit message (Expand)Author
2010-12-22i965: explicit tell header present for fb write on sandybridgeZhenyu Wang
2010-12-06i965: Add support for the instruction compression bits on gen6.Eric Anholt
2010-12-01i965: Add support for gen6 CONTINUE instruction emit.Eric Anholt
2010-12-01i965: Add support for gen6 BREAK ISA emit.Eric Anholt
2010-10-26i965: Add EU code for dword scattered reads (constant buffer array indexing).Eric Anholt
2010-10-22i965: Add support for pull constants to the new FS backend.Eric Anholt
2010-10-21i965: Add support for register spilling.Eric Anholt
2010-10-19i965: Add EU emit support for gen6's new IF instruction with comparison.Eric Anholt
2010-10-14i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke
2010-10-14i965: Correctly emit the RNDZ instruction.Kenneth Graunke
2010-09-28i965: Add support for POW in gen6 FS.Eric Anholt
2010-08-30i965: Make brw_CONT and brw_BREAK take the pop count.Eric Anholt
2010-08-20i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.Eric Anholt
2010-08-20i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang
2010-08-18i965: Don't set the swizzle on an immediate value in the VS.Eric Anholt
2010-07-26i965: Fix reversed naming of the operations in compute-to-mrf optimization.Eric Anholt
2010-07-26i965: Move the GRF-to-MRF optimizations to brw_optimize.c.Eric Anholt
2010-07-21i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt
2010-07-21i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
2010-06-10mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt
2010-03-12i965: Fix up VS DP4 sequences to avoid dependency control.Eric Anholt
2010-03-10i965: Use the PLN instruction when possible in interpolation.Eric Anholt
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-30i965: use BRW_MAX_GRF, BRW_MAX_MRFBrian Paul
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
2009-05-12i965: increase BRW_EU_MAX_INSNBrian Paul
2009-04-17i915: fix broken indirect constant buffer readsBrian Paul
2009-04-16i965: implement relative addressing for VS constant buffer readsBrian Paul
2009-04-14i965: fix VS constant buffer readsBrian Paul
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
2009-04-03i965: added brw_same_reg()Brian Paul
2009-04-03i965: added new brw_dp_READ_4() functionBrian Paul
2009-03-13i965: more register number assertionsBrian Paul
2009-03-06i965: bump up BRW_EU_MAX_INSNBrian Paul
2009-02-13i965: rewrite the code for handling shader subroutine callsBrian Paul
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
2009-01-01i965: comments, clean-ups, re-order some functionsBrian Paul
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
2008-10-31i965: support destination horiz strides in align1 access mode.Gary Wong
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-04-25[i965] short immediate values must be replicated to both halves of the dwordKeith Packard
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-12-29fix fd.o bug #13847Zou Nan hai
2007-09-30 fragment shader function call fix, gl_FragCoord fixZou Nan hai
2007-09-29 support continue, fix conditionalZou Nan hai
2007-06-21 support branch and loop in pixel shaderZou Nan hai
2007-04-12 Initial 965 GLSL supportZou Nan hai
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