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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
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2010-11-10i965: fix dest type of 'endif' on sandybridgeZhenyu Wang
That should also be immediate value for type W.
2010-10-26i965: Drop the eot argument to read messages, which can never be set.Eric Anholt
2010-10-26i965: Add support for constant buffer loads on gen6.Eric Anholt
Fixes glsl-fs-uniform-array-5.
2010-10-26i965: Use SENDC on the first render target write on gen6.Eric Anholt
This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
2010-10-26i965: Clarify an XXX comment in FB writes with real info.Eric Anholt
2010-10-26i965: Add EU code for dword scattered reads (constant buffer array indexing).Eric Anholt
2010-10-22i965: Add support for pull constants to the new FS backend.Eric Anholt
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-21i965: Don't emit register spill offsets directly into g0.Eric Anholt
g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21i965: Add support for register spilling.Eric Anholt
It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-19i965: Set the source operand types for gen6 if/else/endif to integer.Eric Anholt
I don't think this should matter, but I'm not sure, and it's recommended by a kernel checker in fulsim.
2010-10-19i965: Add EU emit support for gen6's new IF instruction with comparison.Eric Anholt
2010-10-14i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke
2010-10-14i965: Correctly emit the RNDZ instruction.Kenneth Graunke
Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14i965: Fix GS hang on SandybridgeZhenyu Wang
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would smash FFID field in GS payload, that cause later URB write fail. Also not use r0 in any URB write requiring allocate.
2010-10-11i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt
2010-10-08i965: Silence unused variable warning on non-debug builds.Vinson Lee
Fixes this GCC warning. brw_eu_emit.c: In function 'brw_math2': brw_eu_emit.c:1189: warning: unused variable 'intel'
2010-10-06i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt
The jump delta is now in the part of the instruction where the destination fields used to be, and the src args are ignored (or not, for the new non-predicated IF that we don't use yet).
2010-10-06i965: Gen6 no longer has the IFF instruction; always use IF.Eric Anholt
2010-10-04i965: Add support for gen6 FB writes to the new FS.Eric Anholt
This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
2010-09-28i965: Fix sampler on sandybridgeZhenyu Wang
Sandybridge has not much change on texture sampler with Ironlake.
2010-09-28i965: fix jump count on sandybridgeZhenyu Wang
Jump count is for 64bit long each, so one instruction requires 2 like on Ironlake.
2010-09-28i965: ff sync message change for sandybridgeZhenyu Wang
2010-09-28i965: Add support for POW in gen6 FS.Eric Anholt
Fixes glsl-algebraic-pow-2 in brw_wm_glsl.c mode.
2010-09-07i965: Add some validation on BRW_OPCODE_MUL and ADD's arguments.Eric Anholt
Now that we're playing with other types in brw_fs.cpp, it's easy to trip over issues like these.
2010-09-07i965: Add assertion for another requirement about types.Eric Anholt
This catches a failure in the FS backend.
2010-09-07i965: Add a bit of validation for some ISA restrictions in the docs.Eric Anholt
2010-08-30i965: Make brw_CONT and brw_BREAK take the pop count.Eric Anholt
We always need to set it, so pass it in.
2010-08-20i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.Eric Anholt
2010-08-20i965: Add support for FB writes on Sandybridge.Zhenyu Wang
2010-08-20i965: Set the destination horiz stride even for da16, as SNB seems to need it.Zhenyu Wang
2010-07-21i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt
2010-07-21i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt
The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets.
2010-07-21i956: Set the execution size correctly for scratch space writes.Eric Anholt
Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders.
2010-07-21i965: Use the pretty define for 4-oword DP reads.Eric Anholt
2010-07-21i965: Set the send commit bit on register spills as required pre-gen6.Eric Anholt
Otherwise, the subsequent read may not get the written value.
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
When EU executes 'wait' instruction, it stalls and sets notification register state. Host can issue MMIO write to clear notification register state to allow EU continue on executing again. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-06-12i965: Use the new message header format for FF_SYNC on gen6.Zhenyu Wang
2010-06-12i965: Add support for math instructions in the gen6 WM.Zhenyu Wang
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-03-22i965: Ignore execution mask for the mov(m0, g0) of VS URB write header on SNB.Eric Anholt
Otherwise, we may not get the FFTID set up which would break freeing of resources.
2010-03-10i965: Use the PLN instruction when possible in interpolation.Eric Anholt
Saves an instruction in PINTERP, LINTERP, and PIXEL_W from brw_wm_glsl.c For non-GLSL it isn't used yet because the deltas have to be laid out differently.
2010-03-10i965: Set up the execution size before relying on it.Eric Anholt
Fixes hangs with texturing in the non-GLSL path since f6d210c284751ac50a8d6358de7e75a1ff1e4ac7
2010-03-10i965: Fix the response len of masked sampler messages for 8-wide dispatch.Eric Anholt
The bad response length would hang the GPU with a masked sample in a shader using control flow. For 8-wide, the response length is always 4, and masked slots are just not written to. brw_wm_glsl.c already allocates registers in the right locations. Fixes piglit glsl-fs-bug25902 (fd.o bug #25902).
2010-02-25i965: Try to hook up the Sandybridge URB_WRITE SEND message.Eric Anholt
My units still hang when doing this if the VS is enabled.
2010-02-25i965: Add SNB math opcode support.Eric Anholt
This is untested at this point.
2010-02-19Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg
2009-12-31Merge branch 'mesa_7_7_branch'Brian Paul
Conflicts: configs/darwin src/gallium/auxiliary/util/u_clear.h src/gallium/state_trackers/xorg/xorg_exa_tgsi.c src/mesa/drivers/dri/i965/brw_draw_upload.c
2009-12-28intel: Silence compiler warnings.Vinson Lee
2009-12-27Merge branch 'mesa_7_6_branch' into mesa_7_7_branchBrian Paul
Conflicts: src/gallium/auxiliary/util/u_network.c src/gallium/auxiliary/util/u_network.h src/gallium/drivers/i915/i915_state.c src/gallium/drivers/trace/tr_rbug.c src/gallium/state_trackers/vega/bezier.c src/gallium/state_trackers/vega/vg_context.c src/gallium/state_trackers/xorg/xorg_crtc.c src/gallium/state_trackers/xorg/xorg_driver.c src/gallium/winsys/xlib/xlib_brw_context.c src/mesa/main/mtypes.h
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