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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
AgeCommit message (Expand)Author
2010-10-14i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke
2010-10-14i965: Correctly emit the RNDZ instruction.Kenneth Graunke
2010-10-14i965: Fix GS hang on SandybridgeZhenyu Wang
2010-10-11i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt
2010-10-08i965: Silence unused variable warning on non-debug builds.Vinson Lee
2010-10-06i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt
2010-10-06i965: Gen6 no longer has the IFF instruction; always use IF.Eric Anholt
2010-10-04i965: Add support for gen6 FB writes to the new FS.Eric Anholt
2010-09-28i965: Fix sampler on sandybridgeZhenyu Wang
2010-09-28i965: fix jump count on sandybridgeZhenyu Wang
2010-09-28i965: ff sync message change for sandybridgeZhenyu Wang
2010-09-28i965: Add support for POW in gen6 FS.Eric Anholt
2010-09-07i965: Add some validation on BRW_OPCODE_MUL and ADD's arguments.Eric Anholt
2010-09-07i965: Add assertion for another requirement about types.Eric Anholt
2010-09-07i965: Add a bit of validation for some ISA restrictions in the docs.Eric Anholt
2010-08-30i965: Make brw_CONT and brw_BREAK take the pop count.Eric Anholt
2010-08-20i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.Eric Anholt
2010-08-20i965: Add support for FB writes on Sandybridge.Zhenyu Wang
2010-08-20i965: Set the destination horiz stride even for da16, as SNB seems to need it.Zhenyu Wang
2010-07-21i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt
2010-07-21i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt
2010-07-21i956: Set the execution size correctly for scratch space writes.Eric Anholt
2010-07-21i965: Use the pretty define for 4-oword DP reads.Eric Anholt
2010-07-21i965: Set the send commit bit on register spills as required pre-gen6.Eric Anholt
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
2010-06-12i965: Use the new message header format for FF_SYNC on gen6.Zhenyu Wang
2010-06-12i965: Add support for math instructions in the gen6 WM.Zhenyu Wang
2010-05-18i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
2010-03-22i965: Ignore execution mask for the mov(m0, g0) of VS URB write header on SNB.Eric Anholt
2010-03-10i965: Use the PLN instruction when possible in interpolation.Eric Anholt
2010-03-10i965: Set up the execution size before relying on it.Eric Anholt
2010-03-10i965: Fix the response len of masked sampler messages for 8-wide dispatch.Eric Anholt
2010-02-25i965: Try to hook up the Sandybridge URB_WRITE SEND message.Eric Anholt
2010-02-25i965: Add SNB math opcode support.Eric Anholt
2010-02-19Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg
2009-12-31Merge branch 'mesa_7_7_branch'Brian Paul
2009-12-28intel: Silence compiler warnings.Vinson Lee
2009-12-27Merge branch 'mesa_7_6_branch' into mesa_7_7_branchBrian Paul
2009-12-24i965: Fix assert.Vinson Lee
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
2009-08-04i965: Don't set pop_count in the reserved MBZ area of IF statements.Eric Anholt
2009-08-04i965: Spell "conditional" correctly.Eric Anholt
2009-07-15i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNGXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-07-02i965: fixes for JMPIXiang, Haihao
2009-06-30i965: use BRW_MAX_MRFBrian Paul
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
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