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path: root/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
AgeCommit message (Collapse)Author
2011-01-31Convert everything from the talloc API to the ralloc API.Kenneth Graunke
2011-01-21glsl, i965: Remove unnecessary talloc includes.Kenneth Graunke
These are already picked up by ir.h or glsl_types.h.
2011-01-12i965: Clarify when we need to (re-)calculate live intervals.Eric Anholt
The ad-hoc placement of recalculation somewhere between when they got invalidated and when they were next needed was confusing. This should clarify what's going on here.
2010-10-26i965: Disable register spilling on gen6 until it's fixed.Eric Anholt
Avoids GPU hang on glsl-fs-convolution-1.
2010-10-22i965: Add support for pull constants to the new FS backend.Eric Anholt
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-21i965: Add support for register spilling.Eric Anholt
It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-21i965: Split register allocation out of the ever-growing brw_fs.cpp.Eric Anholt