summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
AgeCommit message (Collapse)Author
2009-12-22intel: Replace IS_965 checks with context structure usage.Eric Anholt
Saves another 600 bytes or so of code.
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
Saves ~2KB of code.
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
Saves ~480 bytes of code.
2009-11-13i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt
Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965).
2009-09-02i965: validate sf stateXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-06-23i965: Fix packed depth/stencil textures to be Y-tiled as well.Eric Anholt
Fixes shadowtex.c. And an assert is added to catch this sooner next time.
2009-05-06i965: Disentangle VS constant surface state from WM surface state.Eric Anholt
Also, only create VS surface state if there's a VS constant buffer to be uploaded, and set the contents of the buffer at the same time as creation.
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
2009-03-12i965: fix polygon stipple when rendering to FBORobert Ellison
The polygon stipple pattern, like the viewport and the polygon face orientation, must be inverted on the i965 when rendering to a FBO (which itself has an inverted pixel coordinate system compared to raw Mesa). In addition, the polygon stipple offset, which orients the stipple to the window system, disappears when rendering to an FBO (because the window system offset doesn't apply, and there's no associated FBO offset). With these fixes, the conform triangle and polygon stipple tests pass when rendering to texture.
2009-02-25i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt
2009-02-02i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
2008-10-28i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt
Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
2008-10-28intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt
This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
2008-10-24i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao
This ensures there is an unfilled batchbuffer used for emitting states again. Partial fix for #17964.
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
2008-08-08965: cleanups to state emission from aperture checking and state ordering.Eric Anholt
2008-07-25Merge branch 'master' into drm-gemIan Romanick
Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.c src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
This is an API breakage only.
2008-05-07GEM: Remove already-disabled PIPE_CONTROL command.Eric Anholt
This existed to get the icache flushed. However, GEM handles this for us now for sure, and we had disabled it prematurely anyway.
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
2008-04-18i965: fixup depth buffer checkDave Airlie
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
2008-02-07[965] Flush icache on new batch, not just new context.Eric Anholt
This is required since our buffer manager may now move our instruction-containing buffers at any batchbuffer emit.
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-10[intel] Add more cliprect modes to cover other meanings for batch emits.Eric Anholt
The previous change gave us only two modes, one which looped over the batch per cliprect (3d drawing) and one that didn't (state updeast). However, we really want 4: - Batch doesn't care about cliprects (state updates) - Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing) - Batch needs to be executed just once (region fills, copies, etc.) - Batch already includes cliprect handling, and must be flushed by unlock time (copybuffers, clears). All callers should now be fixed to use one of these states for any batchbuffer emits. Thanks to Keith Whitwell for pointing out the failure.
2008-01-09[965] Replace the always_update dirty flag with BRW_NEW_BATCH.Eric Anholt
This allows us to avoid re-emitting some state when validate_state happens multiple times per batchbuffer. Even though we flush batch per primitive currently, that may still happen already if the primitive changed (this should probably be fixed as well).
2008-01-09[965] Remove drawing rect upload, which is handled (better) by the kernel.Eric Anholt
2007-12-20[965] Enable EXT_framebuffer_object.Eric Anholt
To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
2007-12-17[965] Allow draw or depth regions to be NULL.Eric Anholt
With FBOs, we end up wanting to do 3D metaops against one or the other without having to find the other one to fill in if we're not going to draw to it.
2007-12-14[965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt
The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
2007-12-07[965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt
This is currently believed to work but be a significant performance loss. Performance recovery should be soon to follow. The dri_bo_fake_disable_backing_store() call was added to allow backing store disable like bufmgr_fake.c did, which is a significant performance win (though it's missing the no-fence-subdata part). This commit is a squash merge of the 965-ttm branch, which had some history I wanted to avoid pulling due to noisiness and brokenness at many points for git-bisecting.
2006-12-08fix bug#9237Xiang, Haihao
2006-10-23Emit cliprects in the userspace driver as required, rather thanKeith Whitwell
passing them to the kernel. This works because all drawing commands in the 965 driver are emitted with the lock held and the batchbuffer is always flushed prior to releasing the lock. This allows multiple cliprects to be dealt with, without replaying entire batchbuffers and redundantly re-emitting state.
2006-09-07Make sure bmBufferOffset is called for all active buffers every timeKeith Whitwell
we render. Currenly requires that some state be re-examined after every LOCK_HARDWARE().
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.