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path: root/src/mesa/drivers/dri/i965/brw_structs.h
AgeCommit message (Expand)Author
2010-09-28i965: fix scissor state on sandybridgeZhenyu Wang
2010-09-28i965: Fix sampler on sandybridgeZhenyu Wang
2010-08-31i965: fix depth test on sandybridgeZhenyu Wang
2010-08-20i965: Set the destination horiz stride even for da16, as SNB seems to need it.Zhenyu Wang
2010-08-20i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang
2010-07-08i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt
2010-07-08i965: Add definitions for Sandybridge DP write/read messages.Zhenyu Wang
2010-06-18i965: Fix the name of aa_coverage_slope in the improved AA line params.Eric Anholt
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
2010-02-25i965: Add Sandybridge viewport setup.Eric Anholt
2010-02-25i965: Add Sandybridge scissor state.Eric Anholt
2010-02-25i965: Start adding support for the Sandybridge CC unit.Eric Anholt
2009-09-02i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao
2009-08-04i965: Spell "conditional" correctly.Eric Anholt
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-30i965: move BRW_MAX_GRF, define BRW_MAX_MRFBrian Paul
2009-06-17i965: Fall back or appropriately adjust offsets of drawing to tiled regions.Eric Anholt
2009-02-25i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt
2009-01-28i965: minor commentsBrian Paul
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-12-17[965] Simplify scissor handling by using DrawBuffer values.Eric Anholt
2007-12-14[965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt
2007-01-06i965: Avoid branch instructions while in single program flow mode.Eric Anholt
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt