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path: root/src/mesa/drivers/dri/i965/brw_wm_pass2.c
AgeCommit message (Expand)Author
2010-12-06i965: Fix gen6 interpolation setup for 16-wide.Eric Anholt
2010-12-06i965: Move payload reg setup to compile, not lookup time.Eric Anholt
2010-11-03intel: Annotate debug printout checks with unlikely().Eric Anholt
2010-08-30i965: Align the number of payload regs to 2 again in 16-wide mode.Eric Anholt
2010-08-20i965: Rename nr_depth_regs to nr_payload_regs.Eric Anholt
2009-11-17Merge branch 'outputswritten64'Ian Romanick
2009-05-14i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt
2009-05-14i965: Fix register allocation of GLSL fp inputs.Eric Anholt
2009-01-22i965: whitespace changes and reformattingBrian Paul
2008-02-19 fix compile for previous commitZou Nan hai
2008-02-19[i965] fix broken glsl texdemo1Zou Nan hai
2008-02-14i965: use setup attributes as inputs when allocating registersXiang, Haihao
2007-06-21 support branch and loop in pixel shaderZou Nan hai
2007-02-23Update DRI drivers for new glsl compiler.Brian
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt