| Age | Commit message (Expand) | Author |
|---|
| 2009-08-04 | i965: Fix dangerous warning I let slip in. | Eric Anholt |
| 2009-08-04 | i965: Respect CondSwizzle in OPCODE_IF. | Eric Anholt |
| 2009-08-04 | i965: Emit conditional code updates as required for GLSL VS if statements. | Eric Anholt |
| 2009-08-04 | i965: Don't set pop_count in the reserved MBZ area of IF statements. | Eric Anholt |
| 2009-08-04 | i965: Print out ELSE and ENDIF src1 arguments like IF does. | Eric Anholt |
| 2009-08-04 | intel: Add support for EXT_provoking_vertex. | Eric Anholt |
| 2009-08-04 | i965: Spell "conditional" correctly. | Eric Anholt |
| 2009-08-04 | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}. | Eric Anholt |
| 2009-08-04 | i965: Initial import of disasm code from intel-gen4asm. | Eric Anholt |
| 2009-08-04 | i965: warning fix | Eric Anholt |
| 2009-08-04 | i965: Fix RECT shadow sampling by not losing the other texcoords. | Eric Anholt |
| 2009-08-03 | i965: Assert that the offset in the VBO is below the VBO size. | Eric Anholt |
| 2009-08-03 | i965: Even if no VS inputs are set, still load some amount of URB as required. | Eric Anholt |
| 2009-08-03 | i965: Make sure the VS URB size is big enough to fit a VF VUE. | Eric Anholt |
| 2009-08-03 | i965: Don't emit bad packets when no VBs are referenced. | Eric Anholt |
| 2009-08-03 | i965: Calculate enabled[] and nr_enabled once and re-use the values. | Eric Anholt |
| 2009-07-31 | Rename TGSI LOOP instruction to better match theri usage. | Michal Krol |
| 2009-07-30 | i965: Postpone ff_sync message in CLIP kernel on IGDNG | Xiang, Haihao |
| 2009-07-20 | i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled. | Eric Anholt |
| 2009-07-16 | i965: Add missing state dependency of sf_unit on _NEW_BUFFERS. | Eric Anholt |
| 2009-07-15 | i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNG | Xiang, Haihao |
| 2009-07-13 | i965: add support for new chipsets | Xiang, Haihao |
| 2009-07-07 | i965: Remove BRW_NEW_INPUT_VARYING | Eric Anholt |
| 2009-07-02 | i965: fixes for JMPI | Xiang, Haihao |
| 2009-06-30 | i965: Increase G4X default VS URB allocation to actually allow 32 threads. | Eric Anholt |
| 2009-06-30 | i965: first attempt at handling URB overflow when there's too many vs outputs | Brian Paul |
| 2009-06-30 | i965: use BRW_MAX_MRF | Brian Paul |
| 2009-06-30 | i965: use BRW_MAX_GRF, BRW_MAX_MRF | Brian Paul |
| 2009-06-30 | i965: move BRW_MAX_GRF, define BRW_MAX_MRF | Brian Paul |
| 2009-06-30 | i965: defined BRW_MAX_MRF | Brian Paul |
| 2009-06-30 | i965: comments and a new assertion | Brian Paul |
| 2009-06-29 | intel: Move note_unlock() implementation to the one place it's needed. | Eric Anholt |
| 2009-06-26 | i965: fix fetching constants from constant buffer in glsl path | Roland Scheidegger |
| 2009-06-23 | i965: Set the max index buffer address correctly according to the docs. | Eric Anholt |
| 2009-06-23 | i965: Don't set a reserved bit in MI_FLUSH. | Eric Anholt |
| 2009-06-23 | i965: Fix packed depth/stencil textures to be Y-tiled as well. | Eric Anholt |
| 2009-06-19 | intel: Also get the DRI2 front buffer when doing front buffer reading. | Eric Anholt |
| 2009-06-19 | intel: Update Mesa state before span setup in glReadPixels. | Eric Anholt |
| 2009-06-19 | i965: initial code for loops in vertex programs | Brian Paul |
| 2009-06-19 | i965: asst clean-ups, etc in brw_vs_emit() | Brian Paul |
| 2009-06-19 | i965: asst clean-ups, var renaming in brw_wm_emit_glsl() | Brian Paul |
| 2009-06-17 | i965: Add decode for the G4X x,y offset in surface state. | Eric Anholt |
| 2009-06-17 | i965: Fix up texture layout for small things with wide pitches (tiled) | Eric Anholt |
| 2009-06-17 | i965: Fall back or appropriately adjust offsets of drawing to tiled regions. | Eric Anholt |
| 2009-06-16 | Merge branch 'mesa_7_5_branch' | Brian Paul |
| 2009-06-16 | i965: fix bugs in projective texture coordinates | Brian Paul |
| 2009-06-16 | i965: handle OPCODE_SWZ in the glsl path | Roland Scheidegger |
| 2009-06-12 | i965: interpolate colors with perspective correction by default | Brian Paul |
| 2009-06-04 | intel: Add support for tiled textures. | Eric Anholt |
| 2009-06-02 | i965: Support OPCODE_TRUNC in the brw_wm_fp.c code. | Eric Anholt |
