| Age | Commit message (Expand) | Author |
|---|
| 2011-01-09 | radeon: Include mfeatures.h in files that perform feature tests. | Vinson Lee |
| 2011-01-09 | dri/nouveau: Include mfeatures.h in files that perform feature tests. | Vinson Lee |
| 2011-01-09 | intel: Include mfeatures.h in files that perform feature tests. | Vinson Lee |
| 2011-01-07 | intel: Make renderbuffer tiling choice match texture tiling choice. | Eric Anholt |
| 2011-01-07 | intel: Use the _BaseFormat from MESA_FORMAT_* in renderbuffer setup. | Eric Anholt |
| 2011-01-07 | i915: Drop old checks for the settexoffset hack. | Eric Anholt |
| 2011-01-07 | i915: Don't claim to support AL1616 when neither 830 nor 915 does it. | Eric Anholt |
| 2011-01-07 | intel: Add a vtbl hook for determining if a format is renderable. | Eric Anholt |
| 2011-01-07 | intel: expose ARB_framebuffer_object in the i915 driver. | Eric Anholt |
| 2011-01-07 | i965: Avoid double-negation of immediate values in the VS. | Eric Anholt |
| 2011-01-07 | r600c: fix up SQ setup in blit code for Ontario/NI | Alex Deucher |
| 2011-01-06 | r600c: add support for NI asics | Alex Deucher |
| 2011-01-06 | i965: Rename various gen6 #defines to match the documentation. | Kenneth Graunke |
| 2011-01-06 | mesa: fix build for NetBSD | Pierre Allegraud |
| 2011-01-06 | i965: skip too small size mipmap | Zou Nan hai |
| 2011-01-05 | i915: Fix build for previous commit. | Eric Anholt |
| 2011-01-05 | intel: Always allocate miptrees from level 0, not tObj->BaseLevel. | Eric Anholt |
| 2011-01-05 | intel: Drop unused first/lastlevel args to miptree_create_for_region. | Eric Anholt |
| 2011-01-05 | intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion. | Eric Anholt |
| 2011-01-05 | i915: Enable LOD preclamping on 8xx like on 915/965. | Eric Anholt |
| 2011-01-05 | i915: Implement min/max lod clamping in hardware on 8xx. | Eric Anholt |
| 2011-01-05 | intel: Drop TEXTURE_RECTANGLE check in miptree layout setup. | Eric Anholt |
| 2011-01-05 | intel: Clean up redundant setup of firstLevel. | Eric Anholt |
| 2011-01-05 | intel: Drop a check for GL_TEXTURE_4D_SGIS. | Eric Anholt |
| 2011-01-05 | i965: Simplify the renderbuffer setup code. | Eric Anholt |
| 2011-01-05 | i965: use BLT to clear buffer if possible on Sandybridge | Xiang, Haihao |
| 2011-01-04 | i965: Add support for SRGB DXT1 formats. | Eric Anholt |
| 2011-01-04 | intel: Merge our choosetexformat fallbacks into core. | Eric Anholt |
| 2011-01-04 | r300/compiler: disable the rename_regs pass for loops | Marek Olšák |
| 2011-01-04 | r300/compiler: Fix black terrain in Civ4 | Tom Stellard |
| 2011-01-04 | intel: When validating an FBO's combined depth/stencil, use the given FBO. | Eric Anholt |
| 2011-01-04 | intel: Fix segfaults from trying to use _ColorDrawBuffers in FBO validation. | Eric Anholt |
| 2011-01-04 | i965: Use last vertex convention for quad provoking vertex on sandybridge | Zhenyu Wang |
| 2011-01-04 | i965: Correct comment for gen6 fb write control message setting | Zhenyu Wang |
| 2011-01-04 | i965: Fix provoking vertex select in clip state for sandybridge | Zhenyu Wang |
| 2011-01-03 | intel: Use tri clears when we don't know how to blit clear the format. | Eric Anholt |
| 2011-01-03 | intel: Handle forced swrast clears before other clear bits. | Eric Anholt |
| 2011-01-03 | radeon: fix build on non-KMS systems. | Dave Airlie |
| 2010-12-28 | i965: Do lowering of array indexing of a vector in the FS. | Eric Anholt |
| 2010-12-28 | i965: Fix regression in FS comparisons on original gen4 due to gen6 changes. | Eric Anholt |
| 2010-12-28 | i965: Factor out the ir comparision to BRW_CONDITIONAL_* code. | Eric Anholt |
| 2010-12-28 | i965: Fix occlusion query on sandybridge | Zhenyu Wang |
| 2010-12-28 | Revert "i965: upload multisample state for fragment program change" | Zhenyu Wang |
| 2010-12-27 | i965: Internally enable GL_NV_blend_square on ES2. | Kenneth Graunke |
| 2010-12-27 | i965: don't spawn GS thread for LINELOOP on Sandybridge | Xiang, Haihao |
| 2010-12-27 | i965: Flatten if-statements beyond depth 16 on pre-gen6. | Kenneth Graunke |
| 2010-12-25 | intel: Only do frame throttling at glFlush time when using frontbuffer. | Eric Anholt |
| 2010-12-24 | i965: use align1 access mode for instructions with execSize=1 in VS | Xiang, Haihao |
| 2010-12-24 | i965: fix register region description | Xiang, Haihao |
| 2010-12-23 | intel: Remove unnecessary headers. | Vinson Lee |
