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The fallback was introduced to fix bug #16697, but made the test it was
fixing run excessively long.
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The fallback was introduced to fix bug #16697, but made the test it was
fixing run excessively long.
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Used for SIN, COS, EXP2, LOG2, POW instructions. TEX next.
Fixed some bugs in MIN, MAX, DP3, DP4, DPH instructions.
In rtasm code:
Special-case spe_lqd(), spe_stqd() functions so they take byte offsets but
low-order 4 bits are shifted out. This makes things consistant with SPU
assembly language conventions.
Added spe_get_registers_used() function.
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Don't use register qualifier. Doxygen-ize comments. Remove 'extern'.
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Commit 1680ef869625dc1fe9cf481b180382a34e0738e7 changed the texenv program
to get color from a state register instead of a constant-valued vertex
attribute. This broke program concatenation (so glDraw/CopyPixels broke).
Now check if the second program get's color from a constant register and
handle that case appropriately.
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If the tnl output attributes matches the swsetup input attributes we still
need to check if the desired vertex color type (float vs. chan) has changed
so that we use the right emit functions.
Fixes a conformance failure found with logicop test at pathlevel 3.
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This lets us short-circuit when we're leaving the same cliprects in place,
which becomes quite common with metaops clears, and may be useful for some of
our FBO paths.
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Fixes bug 17800.
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This is a backport of 8e8208d6db8b764568539784a6473d545dec2265 to gallium-0.1
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git+ssh://marcheu@git.freedesktop.org/git/mesa/mesa into gallium-0.2
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Notably, gears doesn't.
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Also, fix up some comments to be doxygen style.
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Besides meaning x86 and x86-64 architecture, it also depends on SSE2
support enabled on gcc.
This fixes the linux-debug build.
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The assertion failed when we ran out of exec memory.
Found with conform texcombine test.
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Fixes glean pointSprite test w/ software rendering
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Fixes vtk crash and others.
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Fixes vtk crash and others.
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Without this, we would reject programs which sampled multiple times from
registers defined in the same phase (block of instructions with the same
texture indirection count), as each sample would count as a new phase
beginning. Instead, keep track of which phases registers were written in,
and only bump phase when we're reading from one generated in this phase.
On the other hand, we failed to count oC or oD texture samples as being new
phases.
Bug #17865.
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This set of code changes are for stencil code generation
support. Both one-sided and two-sided stenciling are supported.
In addition to the raw code generation changes, these changes had
to be made elsewhere in the system:
- Added new "register set" feature to the SPE assembly generation.
A "register set" is a way to allocate multiple registers and free
them all at the same time, delegating register allocation management
to the spe_function unit. It's quite useful in complex register
allocation schemes (like stenciling).
- Added and improved SPE macro calculations.
These are operations between registers and unsigned integer
immediates. In many cases, the calculation can be performed
with a single instruction; the macros will generate the
single instruction if possible, or generate a register load
and register-to-register operation if not. These macro
functions are: spe_load_uint() (which has new ways to
load a value in a single instruction), spe_and_uint(),
spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint().
- Added facing to fragment generation. While rendering, the rasterizer
needs to be able to determine front- and back-facing fragments, in order
to correctly apply two-sided stencil. That requires these changes:
- Added front_winding field to the cell_command_render block, so that
the state tracker could communicate to the rasterizer what it
considered to be the front-facing direction.
- Added fragment facing as an input to the fragment function.
- Calculated facing is passed during emit_quad().
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