blob: 1379c11291f64e87d0f05a652dc3e70a73d4ec6e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
|
/* This file is autogenerated from eg_states.h - do not edit directly */
/* autogenerating script is gen_eg_states.py */
/* EG_CONFIG */
#define EG_CONFIG__SQ_CONFIG 0
#define EG_CONFIG__SPI_CONFIG_CNTL 1
#define EG_CONFIG__SPI_CONFIG_CNTL_1 2
#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1 3
#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2 4
#define EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3 5
#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1 6
#define EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2 7
#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1 8
#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2 9
#define EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3 10
#define EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 11
#define EG_CONFIG__PA_CL_ENHANCE 12
#define EG_CONFIG__SQ_DYN_GPR_RESOURCE_LIMIT_1 13
#define EG_CONFIG__SQ_LDS_ALLOC_PS 14
#define EG_CONFIG__SX_MISC 15
#define EG_CONFIG__SQ_ESGS_RING_ITEMSIZE 16
#define EG_CONFIG__SQ_GSVS_RING_ITEMSIZE 17
#define EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE 18
#define EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE 19
#define EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE 20
#define EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE 21
#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE 22
#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1 23
#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2 24
#define EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3 25
#define EG_CONFIG__VGT_OUTPUT_PATH_CNTL 26
#define EG_CONFIG__VGT_HOS_CNTL 27
#define EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL 28
#define EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL 29
#define EG_CONFIG__VGT_HOS_REUSE_DEPTH 30
#define EG_CONFIG__VGT_GROUP_PRIM_TYPE 31
#define EG_CONFIG__VGT_GROUP_FIRST_DECR 32
#define EG_CONFIG__VGT_GROUP_DECR 33
#define EG_CONFIG__VGT_GROUP_VECT_0_CNTL 34
#define EG_CONFIG__VGT_GROUP_VECT_1_CNTL 35
#define EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL 36
#define EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL 37
#define EG_CONFIG__VGT_GS_MODE 38
#define EG_CONFIG__PA_SC_MODE_CNTL_0 39
#define EG_CONFIG__PA_SC_MODE_CNTL_1 40
#define EG_CONFIG__VGT_REUSE_OFF 41
#define EG_CONFIG__VGT_VTX_CNT_EN 42
#define EG_CONFIG__VGT_SHADER_STAGES_EN 43
#define EG_CONFIG__VGT_STRMOUT_CONFIG 44
#define EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG 45
#define EG_CONFIG_SIZE 46
#define EG_CONFIG_PM4 128
/* EG_CB_CNTL */
#define EG_CB_CNTL__CB_TARGET_MASK 0
#define EG_CB_CNTL__CB_SHADER_MASK 1
#define EG_CB_CNTL__CB_COLOR_CONTROL 2
#define EG_CB_CNTL__PA_SC_AA_CONFIG 3
#define EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX 4
#define EG_CB_CNTL__PA_SC_AA_MASK 5
#define EG_CB_CNTL_SIZE 6
#define EG_CB_CNTL_PM4 128
/* EG_RASTERIZER */
#define EG_RASTERIZER__SPI_INTERP_CONTROL_0 0
#define EG_RASTERIZER__PA_CL_CLIP_CNTL 1
#define EG_RASTERIZER__PA_SU_SC_MODE_CNTL 2
#define EG_RASTERIZER__PA_CL_VS_OUT_CNTL 3
#define EG_RASTERIZER__PA_CL_NANINF_CNTL 4
#define EG_RASTERIZER__PA_SU_POINT_SIZE 5
#define EG_RASTERIZER__PA_SU_POINT_MINMAX 6
#define EG_RASTERIZER__PA_SU_LINE_CNTL 7
#define EG_RASTERIZER__PA_SC_MPASS_PS_CNTL 8
#define EG_RASTERIZER__PA_SC_LINE_CNTL 9
#define EG_RASTERIZER__PA_SU_VTX_CNTL 10
#define EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ 11
#define EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ 12
#define EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ 13
#define EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ 14
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL 15
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP 16
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE 17
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET 18
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE 19
#define EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET 20
#define EG_RASTERIZER_SIZE 21
#define EG_RASTERIZER_PM4 128
/* EG_VIEWPORT */
#define EG_VIEWPORT__PA_SC_VPORT_ZMIN_0 0
#define EG_VIEWPORT__PA_SC_VPORT_ZMAX_0 1
#define EG_VIEWPORT__PA_CL_VPORT_XSCALE_0 2
#define EG_VIEWPORT__PA_CL_VPORT_YSCALE_0 3
#define EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0 4
#define EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0 5
#define EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0 6
#define EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0 7
#define EG_VIEWPORT__PA_CL_VTE_CNTL 8
#define EG_VIEWPORT_SIZE 9
#define EG_VIEWPORT_PM4 128
/* EG_SCISSOR */
#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL 0
#define EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR 1
#define EG_SCISSOR__PA_SC_WINDOW_OFFSET 2
#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL 3
#define EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR 4
#define EG_SCISSOR__PA_SC_CLIPRECT_RULE 5
#define EG_SCISSOR__PA_SC_CLIPRECT_0_TL 6
#define EG_SCISSOR__PA_SC_CLIPRECT_0_BR 7
#define EG_SCISSOR__PA_SC_CLIPRECT_1_TL 8
#define EG_SCISSOR__PA_SC_CLIPRECT_1_BR 9
#define EG_SCISSOR__PA_SC_CLIPRECT_2_TL 10
#define EG_SCISSOR__PA_SC_CLIPRECT_2_BR 11
#define EG_SCISSOR__PA_SC_CLIPRECT_3_TL 12
#define EG_SCISSOR__PA_SC_CLIPRECT_3_BR 13
#define EG_SCISSOR__PA_SC_EDGERULE 14
#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL 15
#define EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR 16
#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL 17
#define EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR 18
#define EG_SCISSOR__PA_SU_HARDWARE_SCREEN_OFFSET 19
#define EG_SCISSOR_SIZE 20
#define EG_SCISSOR_PM4 128
/* EG_BLEND */
#define EG_BLEND__CB_BLEND_RED 0
#define EG_BLEND__CB_BLEND_GREEN 1
#define EG_BLEND__CB_BLEND_BLUE 2
#define EG_BLEND__CB_BLEND_ALPHA 3
#define EG_BLEND__CB_BLEND0_CONTROL 4
#define EG_BLEND__CB_BLEND1_CONTROL 5
#define EG_BLEND__CB_BLEND2_CONTROL 6
#define EG_BLEND__CB_BLEND3_CONTROL 7
#define EG_BLEND__CB_BLEND4_CONTROL 8
#define EG_BLEND__CB_BLEND5_CONTROL 9
#define EG_BLEND__CB_BLEND6_CONTROL 10
#define EG_BLEND__CB_BLEND7_CONTROL 11
#define EG_BLEND_SIZE 12
#define EG_BLEND_PM4 128
/* EG_DSA */
#define EG_DSA__DB_STENCIL_CLEAR 0
#define EG_DSA__DB_DEPTH_CLEAR 1
#define EG_DSA__SX_ALPHA_TEST_CONTROL 2
#define EG_DSA__DB_STENCILREFMASK 3
#define EG_DSA__DB_STENCILREFMASK_BF 4
#define EG_DSA__SX_ALPHA_REF 5
#define EG_DSA__SPI_FOG_CNTL 6
#define EG_DSA__DB_DEPTH_CONTROL 7
#define EG_DSA__DB_SHADER_CONTROL 8
#define EG_DSA__DB_RENDER_CONTROL 9
#define EG_DSA__DB_COUNT_CONTROL 10
#define EG_DSA__DB_RENDER_OVERRIDE 11
#define EG_DSA__DB_RENDER_OVERRIDE2 12
#define EG_DSA__DB_SRESULTS_COMPARE_STATE0 13
#define EG_DSA__DB_SRESULTS_COMPARE_STATE1 14
#define EG_DSA__DB_PRELOAD_CONTROL 15
#define EG_DSA__DB_ALPHA_TO_MASK 16
#define EG_DSA_SIZE 17
#define EG_DSA_PM4 128
/* EG_VS_SHADER */
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_0 0
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_1 1
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_2 2
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_3 3
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_4 4
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_5 5
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_6 6
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_7 7
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_8 8
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_9 9
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_10 10
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_11 11
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_12 12
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_13 13
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_14 14
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_15 15
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_16 16
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_17 17
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_18 18
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_19 19
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_20 20
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_21 21
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_22 22
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_23 23
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_24 24
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_25 25
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_26 26
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_27 27
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_28 28
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_29 29
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_30 30
#define EG_VS_SHADER__SQ_VTX_SEMANTIC_31 31
#define EG_VS_SHADER__SPI_VS_OUT_ID_0 32
#define EG_VS_SHADER__SPI_VS_OUT_ID_1 33
#define EG_VS_SHADER__SPI_VS_OUT_ID_2 34
#define EG_VS_SHADER__SPI_VS_OUT_ID_3 35
#define EG_VS_SHADER__SPI_VS_OUT_ID_4 36
#define EG_VS_SHADER__SPI_VS_OUT_ID_5 37
#define EG_VS_SHADER__SPI_VS_OUT_ID_6 38
#define EG_VS_SHADER__SPI_VS_OUT_ID_7 39
#define EG_VS_SHADER__SPI_VS_OUT_ID_8 40
#define EG_VS_SHADER__SPI_VS_OUT_ID_9 41
#define EG_VS_SHADER__SPI_VS_OUT_CONFIG 42
#define EG_VS_SHADER__SQ_PGM_START_VS 43
#define EG_VS_SHADER__SQ_PGM_RESOURCES_VS 44
#define EG_VS_SHADER__SQ_PGM_RESOURCES_2_VS 45
#define EG_VS_SHADER__SQ_PGM_START_FS 46
#define EG_VS_SHADER__SQ_PGM_RESOURCES_FS 47
#define EG_VS_SHADER_SIZE 48
#define EG_VS_SHADER_PM4 128
/* EG_PS_SHADER */
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 0
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_1 1
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_2 2
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_3 3
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_4 4
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_5 5
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_6 6
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_7 7
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_8 8
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_9 9
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_10 10
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_11 11
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_12 12
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_13 13
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_14 14
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_15 15
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_16 16
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_17 17
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_18 18
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_19 19
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_20 20
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_21 21
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_22 22
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_23 23
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_24 24
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_25 25
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_26 26
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_27 27
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_28 28
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_29 29
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_30 30
#define EG_PS_SHADER__SPI_PS_INPUT_CNTL_31 31
#define EG_PS_SHADER__SPI_THREAD_GROUPING 32
#define EG_PS_SHADER__SPI_PS_IN_CONTROL_0 33
#define EG_PS_SHADER__SPI_PS_IN_CONTROL_1 34
#define EG_PS_SHADER__SPI_INPUT_Z 35
#define EG_PS_SHADER__SPI_BARYC_CNTL 36
#define EG_PS_SHADER__SPI_PS_IN_CONTROL_2 37
#define EG_PS_SHADER__SPI_COMPUTE_INPUT_CNTL 38
#define EG_PS_SHADER__SQ_PGM_START_PS 39
#define EG_PS_SHADER__SQ_PGM_RESOURCES_PS 40
#define EG_PS_SHADER__SQ_PGM_RESOURCES_2_PS 41
#define EG_PS_SHADER__SQ_PGM_EXPORTS_PS 42
#define EG_PS_SHADER_SIZE 43
#define EG_PS_SHADER_PM4 128
/* EG_UCP */
#define EG_UCP__PA_CL_UCP0_X 0
#define EG_UCP__PA_CL_UCP0_Y 1
#define EG_UCP__PA_CL_UCP0_Z 2
#define EG_UCP__PA_CL_UCP0_W 3
#define EG_UCP__PA_CL_UCP1_X 4
#define EG_UCP__PA_CL_UCP1_Y 5
#define EG_UCP__PA_CL_UCP1_Z 6
#define EG_UCP__PA_CL_UCP1_W 7
#define EG_UCP__PA_CL_UCP2_X 8
#define EG_UCP__PA_CL_UCP2_Y 9
#define EG_UCP__PA_CL_UCP2_Z 10
#define EG_UCP__PA_CL_UCP2_W 11
#define EG_UCP__PA_CL_UCP3_X 12
#define EG_UCP__PA_CL_UCP3_Y 13
#define EG_UCP__PA_CL_UCP3_Z 14
#define EG_UCP__PA_CL_UCP3_W 15
#define EG_UCP__PA_CL_UCP4_X 16
#define EG_UCP__PA_CL_UCP4_Y 17
#define EG_UCP__PA_CL_UCP4_Z 18
#define EG_UCP__PA_CL_UCP4_W 19
#define EG_UCP__PA_CL_UCP5_X 20
#define EG_UCP__PA_CL_UCP5_Y 21
#define EG_UCP__PA_CL_UCP5_Z 22
#define EG_UCP__PA_CL_UCP5_W 23
#define EG_UCP_SIZE 24
#define EG_UCP_PM4 128
/* EG_VS_CBUF */
#define EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0 0
#define EG_VS_CBUF__ALU_CONST_CACHE_VS_0 1
#define EG_VS_CBUF_SIZE 2
#define EG_VS_CBUF_PM4 128
/* EG_PS_CBUF */
#define EG_PS_CBUF__ALU_CONST_BUFFER_SIZE_PS_0 0
#define EG_PS_CBUF__ALU_CONST_CACHE_PS_0 1
#define EG_PS_CBUF_SIZE 2
#define EG_PS_CBUF_PM4 128
/* EG_PS_RESOURCE */
#define EG_PS_RESOURCE__RESOURCE0_WORD0 0
#define EG_PS_RESOURCE__RESOURCE0_WORD1 1
#define EG_PS_RESOURCE__RESOURCE0_WORD2 2
#define EG_PS_RESOURCE__RESOURCE0_WORD3 3
#define EG_PS_RESOURCE__RESOURCE0_WORD4 4
#define EG_PS_RESOURCE__RESOURCE0_WORD5 5
#define EG_PS_RESOURCE__RESOURCE0_WORD6 6
#define EG_PS_RESOURCE__RESOURCE0_WORD7 7
#define EG_PS_RESOURCE_SIZE 8
#define EG_PS_RESOURCE_PM4 128
/* EG_VS_RESOURCE */
#define EG_VS_RESOURCE__RESOURCE160_WORD0 0
#define EG_VS_RESOURCE__RESOURCE160_WORD1 1
#define EG_VS_RESOURCE__RESOURCE160_WORD2 2
#define EG_VS_RESOURCE__RESOURCE160_WORD3 3
#define EG_VS_RESOURCE__RESOURCE160_WORD4 4
#define EG_VS_RESOURCE__RESOURCE160_WORD5 5
#define EG_VS_RESOURCE__RESOURCE160_WORD6 6
#define EG_VS_RESOURCE__RESOURCE160_WORD7 7
#define EG_VS_RESOURCE_SIZE 8
#define EG_VS_RESOURCE_PM4 128
/* EG_FS_RESOURCE */
#define EG_FS_RESOURCE__RESOURCE320_WORD0 0
#define EG_FS_RESOURCE__RESOURCE320_WORD1 1
#define EG_FS_RESOURCE__RESOURCE320_WORD2 2
#define EG_FS_RESOURCE__RESOURCE320_WORD3 3
#define EG_FS_RESOURCE__RESOURCE320_WORD4 4
#define EG_FS_RESOURCE__RESOURCE320_WORD5 5
#define EG_FS_RESOURCE__RESOURCE320_WORD6 6
#define EG_FS_RESOURCE__RESOURCE320_WORD7 7
#define EG_FS_RESOURCE_SIZE 8
#define EG_FS_RESOURCE_PM4 128
/* EG_GS_RESOURCE */
#define EG_GS_RESOURCE__RESOURCE336_WORD0 0
#define EG_GS_RESOURCE__RESOURCE336_WORD1 1
#define EG_GS_RESOURCE__RESOURCE336_WORD2 2
#define EG_GS_RESOURCE__RESOURCE336_WORD3 3
#define EG_GS_RESOURCE__RESOURCE336_WORD4 4
#define EG_GS_RESOURCE__RESOURCE336_WORD5 5
#define EG_GS_RESOURCE__RESOURCE336_WORD6 6
#define EG_GS_RESOURCE__RESOURCE336_WORD7 7
#define EG_GS_RESOURCE_SIZE 8
#define EG_GS_RESOURCE_PM4 128
/* EG_PS_SAMPLER */
#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0 0
#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0 1
#define EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0 2
#define EG_PS_SAMPLER_SIZE 3
#define EG_PS_SAMPLER_PM4 128
/* EG_VS_SAMPLER */
#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18 0
#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18 1
#define EG_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18 2
#define EG_VS_SAMPLER_SIZE 3
#define EG_VS_SAMPLER_PM4 128
/* EG_GS_SAMPLER */
#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36 0
#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36 1
#define EG_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36 2
#define EG_GS_SAMPLER_SIZE 3
#define EG_GS_SAMPLER_PM4 128
/* EG_PS_SAMPLER_BORDER */
#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_INDEX 0
#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED 1
#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN 2
#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE 3
#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA 4
#define EG_PS_SAMPLER_BORDER_SIZE 5
#define EG_PS_SAMPLER_BORDER_PM4 128
/* EG_VS_SAMPLER_BORDER */
#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_INDEX 0
#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED 1
#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN 2
#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE 3
#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA 4
#define EG_VS_SAMPLER_BORDER_SIZE 5
#define EG_VS_SAMPLER_BORDER_PM4 128
/* EG_GS_SAMPLER_BORDER */
#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_INDEX 0
#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED 1
#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN 2
#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE 3
#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA 4
#define EG_GS_SAMPLER_BORDER_SIZE 5
#define EG_GS_SAMPLER_BORDER_PM4 128
/* EG_CB */
#define EG_CB__CB_COLOR0_BASE 0
#define EG_CB__CB_COLOR0_PITCH 1
#define EG_CB__CB_COLOR0_SLICE 2
#define EG_CB__CB_COLOR0_VIEW 3
#define EG_CB__CB_COLOR0_INFO 4
#define EG_CB__CB_COLOR0_ATTRIB 5
#define EG_CB__CB_COLOR0_DIM 6
#define EG_CB_SIZE 7
#define EG_CB_PM4 128
/* EG_DB */
#define EG_DB__DB_HTILE_DATA_BASE 0
#define EG_DB__DB_Z_INFO 1
#define EG_DB__DB_STENCIL_INFO 2
#define EG_DB__DB_DEPTH_SIZE 3
#define EG_DB__DB_DEPTH_SLICE 4
#define EG_DB__DB_DEPTH_VIEW 5
#define EG_DB__DB_HTILE_SURFACE 6
#define EG_DB__DB_Z_READ_BASE 7
#define EG_DB__DB_STENCIL_READ_BASE 8
#define EG_DB__DB_Z_WRITE_BASE 9
#define EG_DB__DB_STENCIL_WRITE_BASE 10
#define EG_DB_SIZE 11
#define EG_DB_PM4 128
/* EG_VGT */
#define EG_VGT__VGT_PRIMITIVE_TYPE 0
#define EG_VGT__VGT_MAX_VTX_INDX 1
#define EG_VGT__VGT_MIN_VTX_INDX 2
#define EG_VGT__VGT_INDX_OFFSET 3
#define EG_VGT__VGT_DMA_INDEX_TYPE 4
#define EG_VGT__VGT_PRIMITIVEID_EN 5
#define EG_VGT__VGT_DMA_NUM_INSTANCES 6
#define EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN 7
#define EG_VGT__VGT_INSTANCE_STEP_RATE_0 8
#define EG_VGT__VGT_INSTANCE_STEP_RATE_1 9
#define EG_VGT_SIZE 10
#define EG_VGT_PM4 128
/* EG_DRAW */
#define EG_DRAW__VGT_NUM_INDICES 0
#define EG_DRAW__VGT_DMA_BASE_HI 1
#define EG_DRAW__VGT_DMA_BASE 2
#define EG_DRAW__VGT_DRAW_INITIATOR 3
#define EG_DRAW_SIZE 4
#define EG_DRAW_PM4 128
/* EG_VGT_EVENT */
#define EG_VGT_EVENT__VGT_EVENT_INITIATOR 0
#define EG_VGT_EVENT_SIZE 1
#define EG_VGT_EVENT_PM4 128
/* EG_CB_FLUSH */
#define EG_CB_FLUSH_SIZE 0
#define EG_CB_FLUSH_PM4 128
/* EG_DB_FLUSH */
#define EG_DB_FLUSH_SIZE 0
#define EG_DB_FLUSH_PM4 128
|