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authorHugues Hiegel <root@paranoid>2015-03-11 16:55:04 +0100
committerHugues Hiegel <root@paranoid>2015-03-11 16:55:04 +0100
commit99f904adcc37d93c90defcd8ce898598e25be212 (patch)
tree60a6c7b7b9cf012d6c0e8dcf5c7f4fe0a5b6fc49 /codemirror_ui/lib/CodeMirror-2.3/mode/verilog
parentb2034fdfec040a67988e543a911208ef2491ce7a (diff)
Lot of pluginsHEADmaster
Diffstat (limited to 'codemirror_ui/lib/CodeMirror-2.3/mode/verilog')
-rw-r--r--codemirror_ui/lib/CodeMirror-2.3/mode/verilog/index.html210
-rw-r--r--codemirror_ui/lib/CodeMirror-2.3/mode/verilog/verilog.js194
2 files changed, 404 insertions, 0 deletions
diff --git a/codemirror_ui/lib/CodeMirror-2.3/mode/verilog/index.html b/codemirror_ui/lib/CodeMirror-2.3/mode/verilog/index.html
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+<!doctype html>
+<html>
+ <head>
+ <title>CodeMirror: Verilog mode</title>
+ <link rel="stylesheet" href="../../lib/codemirror.css">
+ <script src="../../lib/codemirror.js"></script>
+ <script src="verilog.js"></script>
+ <link rel="stylesheet" href="../../doc/docs.css">
+ <style>.CodeMirror {border: 2px inset #dee;}</style>
+ </head>
+ <body>
+ <h1>CodeMirror: Verilog mode</h1>
+
+<form><textarea id="code" name="code">
+/* Verilog demo code */
+
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// wb_master_model.v ////
+//// ////
+//// This file is part of the SPI IP core project ////
+//// http://www.opencores.org/projects/spi/ ////
+//// ////
+//// Author(s): ////
+//// - Simon Srot (simons@opencores.org) ////
+//// ////
+//// Based on: ////
+//// - i2c/bench/verilog/wb_master_model.v ////
+//// Copyright (C) 2001 Richard Herveille ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+ parameter dwidth = 32;
+ parameter awidth = 32;
+
+ input clk, rst;
+ output [awidth -1:0] adr;
+ input [dwidth -1:0] din;
+ output [dwidth -1:0] dout;
+ output cyc, stb;
+ output we;
+ output [dwidth/8 -1:0] sel;
+ input ack, err, rty;
+
+ // Internal signals
+ reg [awidth -1:0] adr;
+ reg [dwidth -1:0] dout;
+ reg cyc, stb;
+ reg we;
+ reg [dwidth/8 -1:0] sel;
+
+ reg [dwidth -1:0] q;
+
+ // Memory Logic
+ initial
+ begin
+ adr = {awidth{1'bx}};
+ dout = {dwidth{1'bx}};
+ cyc = 1'b0;
+ stb = 1'bx;
+ we = 1'hx;
+ sel = {dwidth/8{1'bx}};
+ #1;
+ end
+
+ // Wishbone write cycle
+ task wb_write;
+ input delay;
+ integer delay;
+
+ input [awidth -1:0] a;
+ input [dwidth -1:0] d;
+
+ begin
+
+ // wait initial delay
+ repeat(delay) @(posedge clk);
+
+ // assert wishbone signal
+ #1;
+ adr = a;
+ dout = d;
+ cyc = 1'b1;
+ stb = 1'b1;
+ we = 1'b1;
+ sel = {dwidth/8{1'b1}};
+ @(posedge clk);
+
+ // wait for acknowledge from slave
+ while(~ack) @(posedge clk);
+
+ // negate wishbone signals
+ #1;
+ cyc = 1'b0;
+ stb = 1'bx;
+ adr = {awidth{1'bx}};
+ dout = {dwidth{1'bx}};
+ we = 1'hx;
+ sel = {dwidth/8{1'bx}};
+
+ end
+ endtask
+
+ // Wishbone read cycle
+ task wb_read;
+ input delay;
+ integer delay;
+
+ input [awidth -1:0] a;
+ output [dwidth -1:0] d;
+
+ begin
+
+ // wait initial delay
+ repeat(delay) @(posedge clk);
+
+ // assert wishbone signals
+ #1;
+ adr = a;
+ dout = {dwidth{1'bx}};
+ cyc = 1'b1;
+ stb = 1'b1;
+ we = 1'b0;
+ sel = {dwidth/8{1'b1}};
+ @(posedge clk);
+
+ // wait for acknowledge from slave
+ while(~ack) @(posedge clk);
+
+ // negate wishbone signals
+ #1;
+ cyc = 1'b0;
+ stb = 1'bx;
+ adr = {awidth{1'bx}};
+ dout = {dwidth{1'bx}};
+ we = 1'hx;
+ sel = {dwidth/8{1'bx}};
+ d = din;
+
+ end
+ endtask
+
+ // Wishbone compare cycle (read data from location and compare with expected data)
+ task wb_cmp;
+ input delay;
+ integer delay;
+
+ input [awidth -1:0] a;
+ input [dwidth -1:0] d_exp;
+
+ begin
+ wb_read (delay, a, q);
+
+ if (d_exp !== q) begin
+ $display("\n--- ERROR: At address 0x%0x, got 0x%0x, expected 0x%0x at time %t", a, q, d_exp, $time);
+ $stop;
+ end
+ end
+ endtask
+
+endmodule
+</textarea></form>
+
+ <script>
+ var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
+ lineNumbers: true,
+ matchBrackets: true,
+ mode: "text/x-verilog"
+ });
+ </script>
+
+ <p>Simple mode that tries to handle Verilog-like languages as well as it
+ can. Takes one configuration parameters: <code>keywords</code>, an
+ object whose property names are the keywords in the language.</p>
+
+ <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
+ </body>
+</html>
diff --git a/codemirror_ui/lib/CodeMirror-2.3/mode/verilog/verilog.js b/codemirror_ui/lib/CodeMirror-2.3/mode/verilog/verilog.js
new file mode 100644
index 0000000..736d16a
--- /dev/null
+++ b/codemirror_ui/lib/CodeMirror-2.3/mode/verilog/verilog.js
@@ -0,0 +1,194 @@
+CodeMirror.defineMode("verilog", function(config, parserConfig) {
+ var indentUnit = config.indentUnit,
+ keywords = parserConfig.keywords || {},
+ blockKeywords = parserConfig.blockKeywords || {},
+ atoms = parserConfig.atoms || {},
+ hooks = parserConfig.hooks || {},
+ multiLineStrings = parserConfig.multiLineStrings;
+ var isOperatorChar = /[&|~><!\)\(*#%@+\/=?\:;}{,\.\^\-\[\]]/;
+
+ var curPunc;
+
+ function tokenBase(stream, state) {
+ var ch = stream.next();
+ if (hooks[ch]) {
+ var result = hooks[ch](stream, state);
+ if (result !== false) return result;
+ }
+ if (ch == '"') {
+ state.tokenize = tokenString(ch);
+ return state.tokenize(stream, state);
+ }
+ if (/[\[\]{}\(\),;\:\.]/.test(ch)) {
+ curPunc = ch;
+ return null
+ }
+ if (/[\d']/.test(ch)) {
+ stream.eatWhile(/[\w\.']/);
+ return "number";
+ }
+ if (ch == "/") {
+ if (stream.eat("*")) {
+ state.tokenize = tokenComment;
+ return tokenComment(stream, state);
+ }
+ if (stream.eat("/")) {
+ stream.skipToEnd();
+ return "comment";
+ }
+ }
+ if (isOperatorChar.test(ch)) {
+ stream.eatWhile(isOperatorChar);
+ return "operator";
+ }
+ stream.eatWhile(/[\w\$_]/);
+ var cur = stream.current();
+ if (keywords.propertyIsEnumerable(cur)) {
+ if (blockKeywords.propertyIsEnumerable(cur)) curPunc = "newstatement";
+ return "keyword";
+ }
+ if (atoms.propertyIsEnumerable(cur)) return "atom";
+ return "word";
+ }
+
+ function tokenString(quote) {
+ return function(stream, state) {
+ var escaped = false, next, end = false;
+ while ((next = stream.next()) != null) {
+ if (next == quote && !escaped) {end = true; break;}
+ escaped = !escaped && next == "\\";
+ }
+ if (end || !(escaped || multiLineStrings))
+ state.tokenize = tokenBase;
+ return "string";
+ };
+ }
+
+ function tokenComment(stream, state) {
+ var maybeEnd = false, ch;
+ while (ch = stream.next()) {
+ if (ch == "/" && maybeEnd) {
+ state.tokenize = tokenBase;
+ break;
+ }
+ maybeEnd = (ch == "*");
+ }
+ return "comment";
+ }
+
+ function Context(indented, column, type, align, prev) {
+ this.indented = indented;
+ this.column = column;
+ this.type = type;
+ this.align = align;
+ this.prev = prev;
+ }
+ function pushContext(state, col, type) {
+ return state.context = new Context(state.indented, col, type, null, state.context);
+ }
+ function popContext(state) {
+ var t = state.context.type;
+ if (t == ")" || t == "]" || t == "}")
+ state.indented = state.context.indented;
+ return state.context = state.context.prev;
+ }
+
+ // Interface
+
+ return {
+ startState: function(basecolumn) {
+ return {
+ tokenize: null,
+ context: new Context((basecolumn || 0) - indentUnit, 0, "top", false),
+ indented: 0,
+ startOfLine: true
+ };
+ },
+
+ token: function(stream, state) {
+ var ctx = state.context;
+ if (stream.sol()) {
+ if (ctx.align == null) ctx.align = false;
+ state.indented = stream.indentation();
+ state.startOfLine = true;
+ }
+ if (stream.eatSpace()) return null;
+ curPunc = null;
+ var style = (state.tokenize || tokenBase)(stream, state);
+ if (style == "comment" || style == "meta") return style;
+ if (ctx.align == null) ctx.align = true;
+
+ if ((curPunc == ";" || curPunc == ":") && ctx.type == "statement") popContext(state);
+ else if (curPunc == "{") pushContext(state, stream.column(), "}");
+ else if (curPunc == "[") pushContext(state, stream.column(), "]");
+ else if (curPunc == "(") pushContext(state, stream.column(), ")");
+ else if (curPunc == "}") {
+ while (ctx.type == "statement") ctx = popContext(state);
+ if (ctx.type == "}") ctx = popContext(state);
+ while (ctx.type == "statement") ctx = popContext(state);
+ }
+ else if (curPunc == ctx.type) popContext(state);
+ else if (ctx.type == "}" || ctx.type == "top" || (ctx.type == "statement" && curPunc == "newstatement"))
+ pushContext(state, stream.column(), "statement");
+ state.startOfLine = false;
+ return style;
+ },
+
+ indent: function(state, textAfter) {
+ if (state.tokenize != tokenBase && state.tokenize != null) return 0;
+ var firstChar = textAfter && textAfter.charAt(0), ctx = state.context, closing = firstChar == ctx.type;
+ if (ctx.type == "statement") return ctx.indented + (firstChar == "{" ? 0 : indentUnit);
+ else if (ctx.align) return ctx.column + (closing ? 0 : 1);
+ else return ctx.indented + (closing ? 0 : indentUnit);
+ },
+
+ electricChars: "{}"
+ };
+});
+
+(function() {
+ function words(str) {
+ var obj = {}, words = str.split(" ");
+ for (var i = 0; i < words.length; ++i) obj[words[i]] = true;
+ return obj;
+ }
+
+ var verilogKeywords = "always and assign automatic begin buf bufif0 bufif1 case casex casez cell cmos config " +
+ "deassign default defparam design disable edge else end endcase endconfig endfunction endgenerate endmodule " +
+ "endprimitive endspecify endtable endtask event for force forever fork function generate genvar highz0 " +
+ "highz1 if ifnone incdir include initial inout input instance integer join large liblist library localparam " +
+ "macromodule medium module nand negedge nmos nor noshowcancelled not notif0 notif1 or output parameter pmos " +
+ "posedge primitive pull0 pull1 pulldown pullup pulsestyle_onevent pulsestyle_ondetect rcmos real realtime " +
+ "reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared showcancelled signed small specify specparam " +
+ "strong0 strong1 supply0 supply1 table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg " +
+ "unsigned use vectored wait wand weak0 weak1 while wire wor xnor xor";
+
+ var verilogBlockKeywords = "begin bufif0 bufif1 case casex casez config else end endcase endconfig endfunction " +
+ "endgenerate endmodule endprimitive endspecify endtable endtask for forever function generate if ifnone " +
+ "macromodule module primitive repeat specify table task while";
+
+ function metaHook(stream, state) {
+ stream.eatWhile(/[\w\$_]/);
+ return "meta";
+ }
+
+ // C#-style strings where "" escapes a quote.
+ function tokenAtString(stream, state) {
+ var next;
+ while ((next = stream.next()) != null) {
+ if (next == '"' && !stream.eat('"')) {
+ state.tokenize = null;
+ break;
+ }
+ }
+ return "string";
+ }
+
+ CodeMirror.defineMIME("text/x-verilog", {
+ name: "verilog",
+ keywords: words(verilogKeywords),
+ blockKeywords: words(verilogBlockKeywords),
+ atoms: words("null"),
+ hooks: {"`": metaHook, "$": metaHook}
+ });
+}());
generated by cgit v1.2.3 (git 2.51.0) at 2025-11-04 15:34:52 +0000