Merge remote branch 'origin/master' into lp-setup-llvm

Conflicts:
	src/gallium/drivers/llvmpipe/lp_setup_coef.c
	src/gallium/drivers/llvmpipe/lp_setup_coef.h
	src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
	src/gallium/drivers/llvmpipe/lp_setup_point.c
	src/gallium/drivers/llvmpipe/lp_setup_tri.c
	src/gallium/drivers/llvmpipe/lp_state_derived.c
	src/gallium/drivers/llvmpipe/lp_state_fs.h

37 files changed, 5903 insertions, 7719 deletions

diff --git a/src/gallium/drivers/r600/Makefile b/src/gallium/drivers/r600/Makefile
index 3cdb963f97..ede0bb2ec4 100644
--- a/src/gallium/drivers/r600/Makefile
+++ b/src/gallium/drivers/r600/Makefile
@@ -7,22 +7,18 @@ LIBRARY_INCLUDES = \
 	$(shell pkg-config libdrm --cflags-only-I)
 
 C_SOURCES = \
-	r600_buffer.c \
-	r600_state2.c \
-	r600_context.c \
-	r600_shader.c \
-	r600_draw.c \
+	r600_asm.c \
 	r600_blit.c \
+	r600_buffer.c \
 	r600_helper.c \
+	r600_pipe.c \
 	r600_query.c \
 	r600_resource.c \
-	r600_screen.c \
+	r600_shader.c \
 	r600_state.c \
 	r600_texture.c \
-	r600_asm.c \
 	r700_asm.c \
-	r600_hw_states.c \
-	eg_asm.c \
-	eg_hw_states.c
+	evergreen_state.c \
+	eg_asm.c
 
 include ../../Makefile.template
diff --git a/src/gallium/drivers/r600/SConscript b/src/gallium/drivers/r600/SConscript
index 99c8644e02..bf0ad8571b 100644
--- a/src/gallium/drivers/r600/SConscript
+++ b/src/gallium/drivers/r600/SConscript
@@ -16,19 +16,19 @@ env.Append(CPPPATH = [
 r600 = env.ConvenienceLibrary(
     target = 'r600',
     source = [
+        'r600_asm.c',
         'r600_buffer.c',
-        'r600_context.c',
-        'r600_draw.c',
         'r600_blit.c',
         'r600_helper.c',
+        'r600_pipe.c',
         'r600_query.c',
         'r600_resource.c',
-        'r600_screen.c',
+        'r600_shader.c',
         'r600_state.c',
         'r600_texture.c',
-        'r600_shader.c',
-        'r600_asm.c',
         'r700_asm.c',
+        'evergreen_state.c',
+        'eg_asm.c',
     ])
 
 Export('r600')
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index 769f550874..52b7189e9e 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -20,14 +20,13 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_asm.h"
-#include "r600_context.h"
+#include <stdio.h>
+#include <errno.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
+#include "r600_asm.h"
 #include "eg_sq.h"
 #include "r600_opcodes.h"
-#include <stdio.h>
-#include <errno.h>
 
 int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 {
@@ -73,8 +72,8 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
 		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
 					S_SQ_CF_WORD1_BARRIER(1) |
-			                S_SQ_CF_WORD1_COND(cf->cond) |
-			                S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
+					S_SQ_CF_WORD1_COND(cf->cond) |
+					S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
 
 		break;
 	default:
diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
deleted file mode 100644
index d6f417e1e3..0000000000
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ /dev/null
@@ -1,1215 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *           2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Dave Airlie
- */
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include <util/u_blitter.h>
-#include "util/u_pack_color.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "eg_state_inlines.h"
-#include "evergreend.h"
-
-#include "eg_states_inc.h"
-
-static void eg_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	int i;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
-	rstate->states[EG_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
-	rstate->states[EG_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
-	rstate->states[EG_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
-	rstate->states[EG_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
-	rstate->states[EG_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
-	rstate->states[EG_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
-
-	for (i = 0; i < 8; i++) {
-		unsigned eqRGB = state->rt[i].rgb_func;
-		unsigned srcRGB = state->rt[i].rgb_src_factor;
-		unsigned dstRGB = state->rt[i].rgb_dst_factor;
-		
-		unsigned eqA = state->rt[i].alpha_func;
-		unsigned srcA = state->rt[i].alpha_src_factor;
-		unsigned dstA = state->rt[i].alpha_dst_factor;
-		uint32_t bc = 0;
-
-		if (!state->rt[i].blend_enable)
-			continue;
-
-		bc |= S_028780_BLEND_CONTROL_ENABLE(1);
-
-		bc |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
-		bc |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
-		bc |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
-
-		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
-			bc |= S_028780_SEPARATE_ALPHA_BLEND(1);
-			bc |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
-			bc |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
-			bc |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
-		}
-
-		rstate->states[EG_BLEND__CB_BLEND0_CONTROL + i] = bc;
-	}
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_ucp(struct r600_context *rctx, struct radeon_state *rstate,
-	    const struct pipe_clip_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
-
-	for (int i = 0; i < state->nr; i++) {
-		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
-		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
-		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
-		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
-	}
-	radeon_state_pm4(rstate);
-}
-
-static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_framebuffer_state *state, int cb)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	rstate->nbo = 1;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_028C70_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-
-	color_info = S_028C70_FORMAT(format) |
-		S_028C70_COMP_SWAP(swap) |
-		S_028C70_BLEND_CLAMP(1) |
-		S_028C70_SOURCE_FORMAT(1) |
-		S_028C70_NUMBER_TYPE(ntype);
-
-	rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
-	rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
-	rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
-	rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_db(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_framebuffer_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	if (state->zsbuf == NULL)
-		return;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[EG_DB__DB_HTILE_DATA_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[EG_DB__DB_Z_READ_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[EG_DB__DB_Z_WRITE_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[EG_DB__DB_STENCIL_READ_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[EG_DB__DB_STENCIL_WRITE_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format);
-	rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
-	radeon_state_pm4(rstate);
-}
-
-static void eg_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
-	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-	const struct pipe_clip_state *clip = NULL;
-	struct r600_screen *rscreen = rctx->screen;
-	float offset_units = 0, offset_scale = 0;
-	char depth = 0;
-	unsigned offset_db_fmt_cntl = 0;
-	unsigned tmp;
-	unsigned prov_vtx = 1;
-
-	if (rctx->clip)
-		clip = &rctx->clip->state.clip;
-	if (fb->zsbuf) {
-		offset_units = state->offset_units;
-		offset_scale = state->offset_scale * 12.0f;
-		switch (fb->zsbuf->texture->format) {
-		case PIPE_FORMAT_Z24X8_UNORM:
-		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-			depth = -24;
-			offset_units *= 2.0f;
-			break;
-		case PIPE_FORMAT_Z32_FLOAT:
-			depth = -23;
-			offset_units *= 1.0f;
-			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
-			break;
-		case PIPE_FORMAT_Z16_UNORM:
-			depth = -16;
-			offset_units *= 4.0f;
-			break;
-		default:
-			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return;
-		}
-	}
-	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
-
-	if (state->flatshade_first)
-		prov_vtx = 0;
-
-	rctx->flat_shade = state->flatshade;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
-	rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000000;
-	if (rctx->flat_shade)
-		rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |= S_0286D4_FLAT_SHADE_ENA(1);
-	if (state->sprite_coord_enable) {
-		rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
-				S_0286D4_PNT_SPRITE_ENA(1) |
-				S_0286D4_PNT_SPRITE_OVRD_X(2) |
-				S_0286D4_PNT_SPRITE_OVRD_Y(3) |
-				S_0286D4_PNT_SPRITE_OVRD_Z(0) |
-				S_0286D4_PNT_SPRITE_OVRD_W(1);
-		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
-			rstate->states[EG_RASTERIZER__SPI_INTERP_CONTROL_0] |=
-					S_0286D4_PNT_SPRITE_TOP_1(1);
-		}
-	}
-	rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
-	if (clip) {
-		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
-		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
-		rstate->states[EG_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
-	}
-	rstate->states[EG_RASTERIZER__PA_SU_SC_MODE_CNTL] =
-		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
-		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
-		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-		S_028814_FACE(!state->front_ccw) |
-		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
-	rstate->states[EG_RASTERIZER__PA_CL_VS_OUT_CNTL] =
-			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
-			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
-	rstate->states[EG_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
-	/* point size 12.4 fixed point */
-	tmp = (unsigned)(state->point_size * 8.0);
-	rstate->states[EG_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
-	rstate->states[EG_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
-	rstate->states[EG_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
-	rstate->states[EG_RASTERIZER__PA_SU_VTX_CNTL] = 0x00000005;
-
-	rstate->states[EG_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
-	rstate->states[EG_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
-	rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
-	rstate->states[EG_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
-	rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
-	rstate->states[EG_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
-	rstate->states[EG_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	radeon_state_pm4(rstate);
-}
-
-static void eg_scissor(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
-	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-	struct r600_screen *rscreen = rctx->screen;
-	unsigned minx, maxx, miny, maxy;
-	u32 tl, br;
-
-	if (state == NULL) {
-		minx = 0;
-		miny = 0;
-		maxx = fb->cbufs[0]->width;
-		maxy = fb->cbufs[0]->height;
-	} else {
-		minx = state->minx;
-		miny = state->miny;
-		maxx = state->maxx;
-		maxy = state->maxy;
-	}
-	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny);
-	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	/* screen scissor has no WINDOW OFFSET */
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl | S_028204_WINDOW_OFFSET_DISABLE(1);
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl | S_028240_WINDOW_OFFSET_DISABLE(1);
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	radeon_state_pm4(rstate);
-}
-
-static void eg_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
-	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
-	rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	radeon_state_pm4(rstate);
-}
-
-static void eg_dsa(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
-	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
-	struct r600_screen *rscreen = rctx->screen;
-	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
-	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
-	struct r600_shader *rshader;
-	struct r600_query *rquery = NULL;
-	boolean query_running;
-	int i;
-
-	if (rctx->ps_shader == NULL) {
-		return;
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
-
-	db_shader_control = 0;
-	db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
-	db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
-
-	rshader = &rctx->ps_shader->shader;
-	if (rshader->uses_kill)
-		db_shader_control |= S_02880C_KILL_ENABLE(1);
-	for (i = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-			db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
-	}
-	stencil_ref_mask = 0;
-	stencil_ref_mask_bf = 0;
-	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
-		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
-		S_028800_ZFUNC(state->depth.func);
-	/* set stencil enable */
-
-	if (state->stencil[0].enabled) {
-		db_depth_control |= S_028800_STENCIL_ENABLE(1);
-		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
-		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
-		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
-		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-
-		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
-			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
-		stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
-		if (state->stencil[1].enabled) {
-			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
-			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
-			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
-			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
-			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
-			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
-				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
-			stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
-		}
-	}
-
-	alpha_test_control = 0;
-	alpha_ref = 0;
-	if (state->alpha.enabled) {
-		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
-		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
-		alpha_ref = fui(state->alpha.ref_value);
-	}
-
-	db_render_control = 0;
-///	db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
-///		S_028D0C_DEPTH_COMPRESS_DISABLE(1);
-	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
-
-	query_running = false;
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			query_running = true;
-		}
-	}
-
-	if (query_running) {
-		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
-		db_render_control |= S_028D0C_PERFECT_ZPASS_COUNTS(1);
-	}
-
-	rstate->states[EG_DSA__DB_STENCIL_CLEAR] = 0x00000000;
-	rstate->states[EG_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[EG_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
-	rstate->states[EG_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
-	rstate->states[EG_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
-	rstate->states[EG_DSA__SX_ALPHA_REF] = alpha_ref;
-	//	rstate->states[EG_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
-	//	rstate->states[EG_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
-	rstate->states[EG_DSA__SPI_FOG_CNTL] = 0x00000000;
-	rstate->states[EG_DSA__DB_DEPTH_CONTROL] = db_depth_control;
-	rstate->states[EG_DSA__DB_SHADER_CONTROL] = db_shader_control;
-	rstate->states[EG_DSA__DB_RENDER_CONTROL] = db_render_control;
-	rstate->states[EG_DSA__DB_RENDER_OVERRIDE] = db_render_override;
-	  
-	rstate->states[EG_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
-	rstate->states[EG_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
-	rstate->states[EG_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	radeon_state_pm4(rstate);
-}
-
-
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
-{
-	return value * (1 << frac_bits);
-}
-
-static void eg_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
-				const struct pipe_sampler_state *state, unsigned id)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	union util_color uc;
-
-	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
-	if (uc.ui) {
-		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
-		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
-		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
-		rstate->states[EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
-	}
-	radeon_state_pm4(rstate);
-}
-
-static void eg_sampler(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_state *state, unsigned id)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	union util_color uc;
-
-	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
-	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
-			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
-			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
-			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
-			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
-			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
-			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
-	                S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
-	                S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
-	/* FIXME LOD it depends on texture base level ... */
-	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
-			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
-		S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6));
-
-	rstate->states[EG_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = 
-		S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
-S_03C008_TYPE(1);
-	radeon_state_pm4(rstate);
-
-}
-
-
-static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
-			const struct pipe_sampler_view *view, unsigned id)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	const struct util_format_description *desc;
-	struct r600_resource_texture *tmp;
-	struct r600_resource *rbuffer;
-	unsigned format;
-	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
-	unsigned char swizzle[4];
-	int r;
-
-	rstate->cpm4 = 0;
-	swizzle[0] = view->swizzle_r;
-	swizzle[1] = view->swizzle_g;
-	swizzle[2] = view->swizzle_b;
-	swizzle[3] = view->swizzle_a;
-	format = r600_translate_texformat(view->texture->format,
-					  swizzle,
-					  &word4, &yuv_format);
-	if (format == ~0) {
-		return;
-	}
-	desc = util_format_description(view->texture->format);
-	if (desc == NULL) {
-		R600_ERR("unknow format %d\n", view->texture->format);
-		return;
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
-	tmp = (struct r600_resource_texture*)view->texture;
-	rbuffer = &tmp->resource;
-	if (tmp->depth) {
-		r = r600_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
-	}
-	rstate->nbo = 2;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
-
-	pitch = (tmp->pitch[0] / tmp->bpt);
-	pitch = (pitch + 0x7) & ~0x7;
-
-	/* FIXME properly handle first level != 0 */
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
-			S_030000_DIM(r600_tex_dim(view->texture->target)) |
-			S_030000_PITCH((pitch / 8) - 1) |
-			S_030000_TEX_WIDTH(view->texture->width0 - 1);
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD1] =
-		S_030004_TEX_HEIGHT(view->texture->height0 - 1) |
-		S_030004_TEX_DEPTH(view->texture->depth0 - 1);
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD4] =
-		        word4 | 
-			S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
-			S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
-			S_030010_REQUEST_SIZE(1) |
-			S_030010_BASE_LEVEL(view->first_level);
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD5] =
-			S_030014_LAST_LEVEL(view->last_level) |
-			S_030014_BASE_ARRAY(0) |
-			S_030014_LAST_ARRAY(0);
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0;
-	rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD7] =
-			S_03001C_DATA_FORMAT(format) |
-			S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE);
-	radeon_state_pm4(rstate);
-}
-
-static void eg_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
-	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	uint32_t color_control, target_mask, shader_mask;
-	int i;
-
-	target_mask = 0;
-	shader_mask = 0;
-	color_control = S_028808_MODE(1);
-
-	for (i = 0; i < nr_cbufs; i++) {
-		shader_mask |= 0xf << (i * 4);
-	}
-
-	if (pbs->logicop_enable) {
-		color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
-	} else {
-		color_control |= (0xcc << 16);
-	}
-
-	if (pbs->independent_blend_enable) {
-		for (i = 0; i < nr_cbufs; i++) {
-			target_mask |= (pbs->rt[i].colormask << (4 * i));
-		}
-	} else {
-		for (i = 0; i < nr_cbufs; i++) {
-			target_mask |= (pbs->rt[0].colormask << (4 * i));
-		}
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
-	rstate->states[EG_CB_CNTL__CB_SHADER_MASK] = shader_mask;
-	rstate->states[EG_CB_CNTL__CB_TARGET_MASK] = target_mask;
-	rstate->states[EG_CB_CNTL__CB_COLOR_CONTROL] = color_control;
-	rstate->states[EG_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
-	rstate->states[EG_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
-	rstate->states[EG_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rstate);
-}
-
-
-static void eg_init_config(struct r600_context *rctx)
-{
-	int ps_prio;
-	int vs_prio;
-	int gs_prio;
-	int es_prio;
-	int hs_prio, cs_prio, ls_prio;
-	int num_ps_gprs;
-	int num_vs_gprs;
-	int num_gs_gprs;
-	int num_es_gprs;
-	int num_hs_gprs;
-	int num_ls_gprs;
-	int num_temp_gprs;
-	int num_ps_threads;
-	int num_vs_threads;
-	int num_gs_threads;
-	int num_es_threads;
-	int num_hs_threads;
-	int num_ls_threads;
-	int num_ps_stack_entries;
-	int num_vs_stack_entries;
-	int num_gs_stack_entries;
-	int num_es_stack_entries;
-	int num_hs_stack_entries;
-	int num_ls_stack_entries;
-	enum radeon_family family;
-
-	family = radeon_get_family(rctx->rw);
-	ps_prio = 0;
-	vs_prio = 1;
-	gs_prio = 2;
-	es_prio = 3;
-	hs_prio = 0;
-	ls_prio = 0;
-	cs_prio = 0;
-
-	switch (family) {
-	case CHIP_CEDAR:
-	default:
-		num_ps_gprs = 93;
-		num_vs_gprs = 46;
-		num_temp_gprs = 4;
-		num_gs_gprs = 31;
-		num_es_gprs = 31;
-		num_hs_gprs = 23;
-		num_ls_gprs = 23;
-		num_ps_threads = 96;
-		num_vs_threads = 16;
-		num_gs_threads = 16;
-		num_es_threads = 16;
-		num_hs_threads = 16;
-		num_ls_threads = 16;
-		num_ps_stack_entries = 42;
-		num_vs_stack_entries = 42;
-		num_gs_stack_entries = 42;
-		num_es_stack_entries = 42;
-		num_hs_stack_entries = 42;
-		num_ls_stack_entries = 42;
-		break;
-	case CHIP_REDWOOD:
-		num_ps_gprs = 93;
-		num_vs_gprs = 46;
-		num_temp_gprs = 4;
-		num_gs_gprs = 31;
-		num_es_gprs = 31;
-		num_hs_gprs = 23;
-		num_ls_gprs = 23;
-		num_ps_threads = 128;
-		num_vs_threads = 20;
-		num_gs_threads = 20;
-		num_es_threads = 20;
-		num_hs_threads = 20;
-		num_ls_threads = 20;
-		num_ps_stack_entries = 42;
-		num_vs_stack_entries = 42;
-		num_gs_stack_entries = 42;
-		num_es_stack_entries = 42;
-		num_hs_stack_entries = 42;
-		num_ls_stack_entries = 42;
-		break;
-	case CHIP_JUNIPER:
-		num_ps_gprs = 93;
-		num_vs_gprs = 46;
-		num_temp_gprs = 4;
-		num_gs_gprs = 31;
-		num_es_gprs = 31;
-		num_hs_gprs = 23;
-		num_ls_gprs = 23;
-		num_ps_threads = 128;
-		num_vs_threads = 20;
-		num_gs_threads = 20;
-		num_es_threads = 20;
-		num_hs_threads = 20;
-		num_ls_threads = 20;
-		num_ps_stack_entries = 85;
-		num_vs_stack_entries = 85;
-		num_gs_stack_entries = 85;
-		num_es_stack_entries = 85;
-		num_hs_stack_entries = 85;
-		num_ls_stack_entries = 85;
-		break;
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-		num_ps_gprs = 93;
-		num_vs_gprs = 46;
-		num_temp_gprs = 4;
-		num_gs_gprs = 31;
-		num_es_gprs = 31;
-		num_hs_gprs = 23;
-		num_ls_gprs = 23;
-		num_ps_threads = 128;
-		num_vs_threads = 20;
-		num_gs_threads = 20;
-		num_es_threads = 20;
-		num_hs_threads = 20;
-		num_ls_threads = 20;
-		num_ps_stack_entries = 85;
-		num_vs_stack_entries = 85;
-		num_gs_stack_entries = 85;
-		num_es_stack_entries = 85;
-		num_hs_stack_entries = 85;
-		num_ls_stack_entries = 85;
-		break;
-	}
-
-	radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
-
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] = 0x00000000;
-	switch (family) {
-	case CHIP_CEDAR:
-		break;
-	default:
-		rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
-		break;
-	}
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_EXPORT_SRC_C(1);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_CS_PRIO(cs_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_LS_PRIO(ls_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_HS_PRIO(hs_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->config.states[EG_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
-
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
-
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_ES_GPRS(num_es_gprs);
-
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] = 0;
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
-	rctx->config.states[EG_CONFIG__SQ_GPR_RESOURCE_MGMT_3] |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
-
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_PS_THREADS(num_ps_threads);
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_VS_THREADS(num_vs_threads);
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_GS_THREADS(num_gs_threads);
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_1] |= S_008C18_NUM_ES_THREADS(num_es_threads);
-
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
-	rctx->config.states[EG_CONFIG__SQ_THREAD_RESOURCE_MGMT_2] |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
-
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
-
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
-
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] = 0;
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
-	rctx->config.states[EG_CONFIG__SQ_STACK_RESOURCE_MGMT_3] |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
-
-	rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SPI_CONFIG_CNTL_1] = S_00913C_VTX_DONE_DELAY(4);
-
-	rctx->config.states[EG_CONFIG__SX_MISC] = 0x00000000;
-
-	rctx->config.states[EG_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
-	rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_0] = 0x0;
-	rctx->config.states[EG_CONFIG__PA_SC_MODE_CNTL_1] = 0x0;
-
-	rctx->config.states[EG_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-
-	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_1] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_2] = 0x00000000;
-	rctx->config.states[EG_CONFIG__SQ_GS_VERT_ITEMSIZE_3] = 0x00000000;
-
-	rctx->config.states[EG_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_STRMOUT_CONFIG] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_STRMOUT_BUFFER_CONFIG] = 0x00000000;
-	rctx->config.states[EG_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config.states[EG_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-//	rctx->config.states[EG_CONFIG__VGT_CACHE_INVALIDATION] = 0x2;
-//	rctx->config.states[EG_CONFIG__VGT_GS_VERTEX_REUSE] = 0x16;
-	rctx->config.states[EG_CONFIG__PA_CL_ENHANCE] = (3 << 1) | 1;
-	
-	radeon_state_pm4(&rctx->config);
-}
-
-static int eg_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
-			    uint32_t stride, uint32_t format)
-{
-	struct radeon_state *vs_resource = &rctx->vs_resource[id];
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
-
-	radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
-	vs_resource->nbo = 1;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD2] = S_030008_STRIDE(stride) |
-		S_030008_DATA_FORMAT(format);
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD3] = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
-		S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
-		S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
-		S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
-	  
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD6] = 0x00000000;
-	vs_resource->states[EG_PS_RESOURCE__RESOURCE0_WORD7] = 0xC0000000;
-	vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(vs_resource);
-}
-
-static int eg_draw_vgt_init(struct r600_draw *draw,
-			    int vgt_draw_initiator)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
-	radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
-	draw->draw.states[EG_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw.states[EG_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
-	draw->draw.states[EG_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
-	if (rbuffer) {
-		radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
-		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.nbo = 1;
-	}
-	return radeon_state_pm4(&draw->draw);
-}
-
-static int eg_draw_vgt_prim(struct r600_draw *draw,
-			    uint32_t prim, uint32_t vgt_dma_index_type)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
-	draw->vgt.states[EG_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt.states[EG_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
-	draw->vgt.states[EG_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
-	draw->vgt.states[EG_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt.states[EG_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt.states[EG_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt.states[EG_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt.states[EG_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt.states[EG_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	return radeon_state_pm4(&draw->vgt);
-}
-
-
-static int eg_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
-			  struct radeon_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	const struct pipe_rasterizer_state *rasterizer;
-	struct r600_shader *rshader = &rpshader->shader;
-	unsigned i, tmp, exports_ps, num_cout;
-	boolean have_pos = FALSE;
-
-	rasterizer = &rctx->rasterizer->state.rasterizer;
-
-	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	for (i = 0; i < rshader->ninput; i++) {
-		tmp = S_028644_SEMANTIC(i);
-		tmp |= S_028644_SEL_CENTROID(1);
-		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
-			have_pos = TRUE;
-		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
-			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
-		}
-		if (rasterizer->sprite_coord_enable & (1 << i)) {
-			tmp |= S_028644_PT_SPRITE_TEX(1);
-		}
-		state->states[EG_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
-	}
-
-	exports_ps = 0;
-	num_cout = 0;
-	for (i = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-			exports_ps |= 1;
-		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
-			exports_ps |= (1 << (num_cout+1));
-			num_cout++;
-		}
-	}
-	if (!exports_ps) {
-		/* always at least export 1 component per pixel */
-		exports_ps = 2;
-	}
-	state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
-							S_0286CC_PERSP_GRADIENT_ENA(1);
-	if (have_pos) {
-		state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1);
-		state->states[EG_PS_SHADER__SPI_INPUT_Z] |= 1;
-	}
-	state->states[EG_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
-	state->states[EG_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028844_NUM_GPRS(rshader->bc.ngpr) | S_028844_PRIME_CACHE_ON_DRAW(1) |
-		S_028844_STACK_SIZE(rshader->bc.nstack);
-	state->states[EG_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
-	state->states[EG_PS_SHADER__SPI_BARYC_CNTL] = S_0286E0_PERSP_CENTROID_ENA(1) |
-	  S_0286E0_LINEAR_CENTROID_ENA(1); 
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
-	state->nbo = 1;
-	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(state);
-}
-
-static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
-			  struct radeon_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;	
-	struct r600_shader *rshader = &rpshader->shader;
-	unsigned i, tmp;
-
-	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	for (i = 0; i < 10; i++) {
-		state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
-	}
-	/* so far never got proper semantic id from tgsi */
-	for (i = 0; i < 32; i++) {
-		tmp = i << ((i & 3) * 8);
-		state->states[EG_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
-	}
-	state->states[EG_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
-	state->states[EG_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028860_NUM_GPRS(rshader->bc.ngpr) |
-		S_028860_STACK_SIZE(rshader->bc.nstack);
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
-	state->nbo = 2;
-	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(state);
-}
-
-static void eg_texture_state_scissor(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->scissor[level];
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-	rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct radeon_state *rstate;
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype, attrib;
-	const struct util_format_description *desc;
-
-	rstate = &rtexture->cb[cb][level];
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
-	rbuffer = &rtexture->resource;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	ntype = 0;
-	attrib = 0;
-	desc = util_format_description(rbuffer->base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_028C70_NUMBER_SRGB;
-	format = r600_translate_colorformat(rtexture->resource.base.b.format);
-	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 1;
-		color_info = 0;
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 1;
-		color_info = S_028C70_SOURCE_FORMAT(1);
-	}
-	color_info |= S_028C70_FORMAT(format) |
-		S_028C70_COMP_SWAP(swap) |
-		S_028C70_BLEND_CLAMP(1) |
-		S_028C70_NUMBER_TYPE(ntype);
-	rstate->states[EG_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
-	rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
-	rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->db[level];
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	rbuffer = &rtexture->resource;
-	rtexture->tilled = 1;
-	rtexture->array_mode = 2;
-	rtexture->tile_type = 1;
-	rtexture->depth = 1;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	format = r600_translate_dbformat(rbuffer->base.b.format);
-	rstate->states[EG_DB__DB_Z_READ_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_DB__DB_Z_WRITE_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtexture->array_mode) | S_028040_FORMAT(format);
-	rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 1;
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->viewport[level];
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
-	rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
-	radeon_state_pm4(rstate);
-}
-
-struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
-	.blend = eg_blend,
-	.ucp = eg_ucp,
-	.cb = eg_cb,
-	.db = eg_db,
-	.rasterizer = eg_rasterizer,
-	.scissor = eg_scissor,
-	.viewport = eg_viewport,
-	.dsa = eg_dsa,
-	.sampler_border = eg_sampler_border,
-	.sampler = eg_sampler,
-	.resource = eg_resource,
-	.cb_cntl = eg_cb_cntl,
-	.vs_resource = eg_vs_resource,
-	.vgt_init = eg_draw_vgt_init,
-	.vgt_prim = eg_draw_vgt_prim,
-	.vs_shader = eg_vs_shader,
-	.ps_shader = eg_ps_shader,
-	.init_config = eg_init_config,
-	.texture_state_viewport = eg_texture_state_viewport,
-	.texture_state_db = eg_texture_state_db,
-	.texture_state_cb = eg_texture_state_cb,
-	.texture_state_scissor = eg_texture_state_scissor,
-};
-
-void eg_set_constant_buffer(struct pipe_context *ctx,
-			    uint shader, uint index,
-			    struct pipe_resource *buffer)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, type, shader_class, size;
-	struct radeon_state *rstate, *rstates;
-	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
-
-	type = R600_STATE_CBUF;
-
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		shader_class = R600_SHADER_VS;
-		rstates = rctx->vs_constant;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		shader_class = R600_SHADER_PS;
-		rstates = rctx->ps_constant;
-		break;
-	default:
-		R600_ERR("unsupported %d\n", shader);
-		return;
-	}
-
-	rstate = &rstates[0];
-
-#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
-	nconstant = buffer->width0 / 16;
-	size = ALIGN_DIVUP(nconstant, 16);
-
-	radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
-	rstate->states[EG_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
-	rstate->states[EG_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	if (radeon_state_pm4(rstate))
-		return;
-	radeon_draw_bind(&rctx->draw, rstate);
-}
diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h
index 4e3514638b..be81c28b43 100644
--- a/src/gallium/drivers/r600/eg_state_inlines.h
+++ b/src/gallium/drivers/r600/eg_state_inlines.h
@@ -25,6 +25,7 @@
 
 #include "util/u_format.h"
 #include "evergreend.h"
+#include "r600_formats.h"
 
 static INLINE uint32_t r600_translate_blend_function(int blend_func)
 {
@@ -123,6 +124,21 @@ static INLINE uint32_t r600_translate_stencil_op(int s_op)
 	return 0;
 }
 
+static INLINE uint32_t r600_translate_fill(uint32_t func)
+{
+	switch(func) {
+	case PIPE_POLYGON_MODE_FILL:
+		return 2;
+	case PIPE_POLYGON_MODE_LINE:
+		return 1;
+	case PIPE_POLYGON_MODE_POINT:
+		return 0;
+	default:
+		assert(0);
+		return 0;
+	}
+}
+
 /* translates straight */
 static INLINE uint32_t r600_translate_ds_func(int func)
 {
@@ -136,17 +152,17 @@ static inline unsigned r600_tex_wrap(unsigned wrap)
 	case PIPE_TEX_WRAP_REPEAT:
 		return V_03C000_SQ_TEX_WRAP;
 	case PIPE_TEX_WRAP_CLAMP:
-		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
-	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 		return V_03C000_SQ_TEX_CLAMP_BORDER;
 	case PIPE_TEX_WRAP_MIRROR_REPEAT:
 		return V_03C000_SQ_TEX_MIRROR;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 	}
@@ -261,6 +277,14 @@ static inline uint32_t r600_translate_dbformat(enum pipe_format format)
 	}
 }
 
+static inline uint32_t r600_translate_stencilformat(enum pipe_format format)
+{
+	if (format == PIPE_FORMAT_Z24_UNORM_S8_USCALED)
+		return 1;
+	else
+		return 0;
+}
+
 static inline uint32_t r600_translate_colorswap(enum pipe_format format)
 {
 	switch (format) {
@@ -283,6 +307,15 @@ static inline uint32_t r600_translate_colorswap(enum pipe_format format)
 	case PIPE_FORMAT_B4G4R4A4_UNORM:
 	case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_028C70_SWAP_STD;
 		/* 32-bit buffers. */
 
 	case PIPE_FORMAT_A8B8G8R8_SRGB:
@@ -310,12 +343,19 @@ static inline uint32_t r600_translate_colorswap(enum pipe_format format)
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 		return V_028C70_SWAP_STD;
 
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_028C70_SWAP_STD;
+
 	case PIPE_FORMAT_R10G10B10A2_UNORM:
 	case PIPE_FORMAT_R10G10B10X2_SNORM:
 	case PIPE_FORMAT_B10G10R10A2_UNORM:
 	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 		return V_028C70_SWAP_STD_REV;
 
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_028C70_SWAP_STD;
+
 		/* 64-bit buffers. */
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
 	case PIPE_FORMAT_R16G16B16A16_SNORM:
@@ -357,6 +397,15 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return V_028C70_COLOR_4_4_4_4;
 
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028C70_COLOR_16;
+
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_028C70_COLOR_8_8;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_028C70_COLOR_16;
+
 		/* 32-bit buffers. */
 	case PIPE_FORMAT_A8B8G8R8_SRGB:
 	case PIPE_FORMAT_A8B8G8R8_UNORM:
@@ -383,18 +432,37 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 		return V_028C70_COLOR_8_24;
 
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_028C70_COLOR_24_8;
+
 	case PIPE_FORMAT_R32_FLOAT:
 		return V_028C70_COLOR_32_FLOAT;
 
+	case PIPE_FORMAT_R16G16_FLOAT:
+		return V_028C70_COLOR_16_16_FLOAT;
+
+	case PIPE_FORMAT_R16G16_SSCALED:
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_028C70_COLOR_16_16;
+
 		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16A16_SSCALED:
+	case PIPE_FORMAT_R16G16B16_SSCALED:
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
 	case PIPE_FORMAT_R16G16B16A16_SNORM:
 		return V_028C70_COLOR_16_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_FLOAT:
 	case PIPE_FORMAT_R16G16B16A16_FLOAT:
 		return V_028C70_COLOR_16_16_16_16_FLOAT;
+
 	case PIPE_FORMAT_R32G32_FLOAT:
 		return V_028C70_COLOR_32_32_FLOAT;
 
+	case PIPE_FORMAT_R32G32_SSCALED:
+		return V_028C70_COLOR_32_32;
+
 		/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32_FLOAT:
 	  	return V_028C70_COLOR_32_32_32_FLOAT;
@@ -431,4 +499,173 @@ static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
 	return r600_translate_colorformat(format) != ~0;
 }
 
+static INLINE uint32_t r600_translate_vertex_data_type(enum pipe_format format)
+{
+	uint32_t result = 0;
+	const struct util_format_description *desc;
+	unsigned i;
+
+	desc = util_format_description(format);
+	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
+		goto out_unknown;
+	}
+
+	/* Find the first non-VOID channel. */
+	for (i = 0; i < 4; i++) {
+		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+			break;
+		}
+	}
+
+	switch (desc->channel[i].type) {
+		/* Half-floats, floats, doubles */
+	case UTIL_FORMAT_TYPE_FLOAT:
+		switch (desc->channel[i].size) {
+		case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_16_FLOAT;
+				break;
+			case 2:
+				result = FMT_16_16_FLOAT;
+				break;
+			case 3:
+				result = FMT_16_16_16_FLOAT;
+				break;
+			case 4:
+				result = FMT_16_16_16_16_FLOAT;
+				break;
+			}
+			break;
+		case 32:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_32_FLOAT;
+				break;
+			case 2:
+				result = FMT_32_32_FLOAT;
+				break;
+			case 3:
+				result = FMT_32_32_32_FLOAT;
+				break;
+			case 4:
+				result = FMT_32_32_32_32_FLOAT;
+				break;
+			}
+			break;
+		default:
+			goto out_unknown;
+		}
+		break;
+	/* Unsigned ints */
+	case UTIL_FORMAT_TYPE_UNSIGNED:
+	/* Signed ints */
+	case UTIL_FORMAT_TYPE_SIGNED:
+		switch (desc->channel[i].size) {
+		case 8:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_8;
+				break;
+			case 2:
+				result = FMT_8_8;
+				break;
+			case 3:
+//				result = V_038008_FMT_8_8_8; /* fails piglit draw-vertices test */
+//				break;
+			case 4:
+				result = FMT_8_8_8_8;
+				break;
+			}
+			break;
+		case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_16;
+				break;
+			case 2:
+				result = FMT_16_16;
+				break;
+			case 3:
+//				result = V_038008_FMT_16_16_16; /* fails piglit draw-vertices test */
+//				break;
+			case 4:
+				result = FMT_16_16_16_16;
+				break;
+			}
+			break;
+		case 32:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_32;
+				break;
+			case 2:
+				result = FMT_32_32;
+				break;
+			case 3:
+				result = FMT_32_32_32;
+				break;
+			case 4:
+				result = FMT_32_32_32_32;
+				break;
+			}
+			break;
+		default:
+			goto out_unknown;
+		}
+		break;
+	default:
+		goto out_unknown;
+	}
+
+	result = S_030008_DATA_FORMAT(result);
+
+	if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+		result |= S_030008_FORMAT_COMP_ALL(1);
+	}
+	if (desc->channel[i].normalized) {
+		result |= S_030008_NUM_FORMAT_ALL(0);
+	} else {
+		result |= S_030008_NUM_FORMAT_ALL(2);
+	}
+	return result;
+out_unknown:
+	R600_ERR("unsupported vertex format %s\n", util_format_name(format));
+	return ~0;
+}
+
+static INLINE uint32_t r600_translate_vertex_data_swizzle(enum pipe_format format)
+{
+	const struct util_format_description *desc = util_format_description(format);
+	unsigned i;
+	uint32_t word3;
+
+	assert(format);
+
+	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
+		fprintf(stderr, "r600: Bad format %s in %s:%d\n",
+				util_format_short_name(format), __FUNCTION__, __LINE__);
+		return 0;
+	}
+
+	word3 = 0;
+	for (i = 0; i < desc->nr_channels; i++) {
+		switch (i) {
+		case 0:
+			word3 |= S_03000C_DST_SEL_X(desc->swizzle[0]);
+			break;
+		case 1:
+			word3 |= S_03000C_DST_SEL_Y(desc->swizzle[1]);
+			break;
+		case 2:
+			word3 |= S_03000C_DST_SEL_Z(desc->swizzle[2]);
+			break;
+		case 3:
+			word3 |= S_03000C_DST_SEL_W(desc->swizzle[3]);
+			break;
+		}
+	}
+	return word3;
+}
+
 #endif
diff --git a/src/gallium/drivers/r600/eg_states_inc.h b/src/gallium/drivers/r600/eg_states_inc.h
index 462f31cc79..1379c11291 100644
--- a/src/gallium/drivers/r600/eg_states_inc.h
+++ b/src/gallium/drivers/r600/eg_states_inc.h
@@ -150,13 +150,14 @@
 #define EG_DSA__DB_DEPTH_CONTROL		7
 #define EG_DSA__DB_SHADER_CONTROL		8
 #define EG_DSA__DB_RENDER_CONTROL		9
-#define EG_DSA__DB_RENDER_OVERRIDE		10
-#define EG_DSA__DB_RENDER_OVERRIDE2		11
-#define EG_DSA__DB_SRESULTS_COMPARE_STATE0		12
-#define EG_DSA__DB_SRESULTS_COMPARE_STATE1		13
-#define EG_DSA__DB_PRELOAD_CONTROL		14
-#define EG_DSA__DB_ALPHA_TO_MASK		15
-#define EG_DSA_SIZE		16
+#define EG_DSA__DB_COUNT_CONTROL		10
+#define EG_DSA__DB_RENDER_OVERRIDE		11
+#define EG_DSA__DB_RENDER_OVERRIDE2		12
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE0		13
+#define EG_DSA__DB_SRESULTS_COMPARE_STATE1		14
+#define EG_DSA__DB_PRELOAD_CONTROL		15
+#define EG_DSA__DB_ALPHA_TO_MASK		16
+#define EG_DSA_SIZE		17
 #define EG_DSA_PM4 128		
 
 /* EG_VS_SHADER */
@@ -368,27 +369,30 @@
 #define EG_GS_SAMPLER_PM4 128		
 
 /* EG_PS_SAMPLER_BORDER */
-#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED		0
-#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN		1
-#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE		2
-#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA		3
-#define EG_PS_SAMPLER_BORDER_SIZE		4
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_INDEX		0
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED		1
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN		2
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE		3
+#define EG_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA		4
+#define EG_PS_SAMPLER_BORDER_SIZE		5
 #define EG_PS_SAMPLER_BORDER_PM4 128		
 
 /* EG_VS_SAMPLER_BORDER */
-#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED		0
-#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN		1
-#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE		2
-#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA		3
-#define EG_VS_SAMPLER_BORDER_SIZE		4
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_INDEX		0
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED		1
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN		2
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE		3
+#define EG_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA		4
+#define EG_VS_SAMPLER_BORDER_SIZE		5
 #define EG_VS_SAMPLER_BORDER_PM4 128		
 
 /* EG_GS_SAMPLER_BORDER */
-#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED		0
-#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN		1
-#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE		2
-#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA		3
-#define EG_GS_SAMPLER_BORDER_SIZE		4
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_INDEX		0
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED		1
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN		2
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE		3
+#define EG_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA		4
+#define EG_GS_SAMPLER_BORDER_SIZE		5
 #define EG_GS_SAMPLER_BORDER_PM4 128		
 
 /* EG_CB */
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
new file mode 100644
index 0000000000..935496c04a
--- /dev/null
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -0,0 +1,1743 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/* TODO:
+ *	- fix mask for depth control & cull for query
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <util/u_framebuffer.h>
+#include <pipebuffer/pb_buffer.h>
+#include "r600.h"
+#include "evergreend.h"
+#include "r600_resource.h"
+#include "r600_shader.h"
+#include "r600_pipe.h"
+#include "eg_state_inlines.h"
+
+static void evergreen_set_blend_color(struct pipe_context *ctx,
+					const struct pipe_blend_color *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rstate->id = R600_PIPE_STATE_BLEND_COLOR;
+	r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
+	rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *evergreen_create_blend_state(struct pipe_context *ctx,
+					const struct pipe_blend_state *state)
+{
+	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
+	struct r600_pipe_state *rstate;
+	u32 color_control, target_mask;
+	/* FIXME there is more then 8 framebuffer */
+	unsigned blend_cntl[8];
+
+	if (blend == NULL) {
+		return NULL;
+	}
+	rstate = &blend->rstate;
+
+	rstate->id = R600_PIPE_STATE_BLEND;
+
+	target_mask = 0;
+	color_control = S_028808_MODE(1);
+	if (state->logicop_enable) {
+		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
+	} else {
+		color_control |= (0xcc << 16);
+	}
+	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+	if (state->independent_blend_enable) {
+		for (int i = 0; i < 8; i++) {
+			target_mask |= (state->rt[i].colormask << (4 * i));
+		}
+	} else {
+		for (int i = 0; i < 8; i++) {
+			target_mask |= (state->rt[0].colormask << (4 * i));
+		}
+	}
+	blend->cb_target_mask = target_mask;
+	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
+				color_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
+
+	for (int i = 0; i < 8; i++) {
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+
+		blend_cntl[i] = 0;
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
+		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
+			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+		}
+	}
+	for (int i = 0; i < 8; i++) {
+		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL);
+	}
+
+	return rstate;
+}
+
+static void evergreen_bind_blend_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
+	struct r600_pipe_state *rstate;
+
+	if (state == NULL)
+		return;
+	rstate = &blend->rstate;
+	rctx->states[rstate->id] = rstate;
+	rctx->cb_target_mask = blend->cb_target_mask;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void *evergreen_create_dsa_state(struct pipe_context *ctx,
+				   const struct pipe_depth_stencil_alpha_state *state)
+{
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
+
+	if (rstate == NULL) {
+		return NULL;
+	}
+
+	rstate->id = R600_PIPE_STATE_DSA;
+	/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
+	/* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
+	 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
+	 * be set if shader use texkill instruction
+	 */
+	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+
+	/* stencil */
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+		}
+	}
+
+	/* alpha */
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+		alpha_ref = fui(state->alpha.ref_value);
+	}
+
+	/* misc */
+	db_render_control = 0;
+	db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
+		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
+		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
+	/* TODO db_render_override depends on query */
+	r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028430_DB_STENCILREFMASK, stencil_ref_mask,
+				0xFFFFFFFF & C_028430_STENCILREF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
+				0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
+	r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
+
+	return rstate;
+}
+
+static void *evergreen_create_rs_state(struct pipe_context *ctx,
+					const struct pipe_rasterizer_state *state)
+{
+	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
+	struct r600_pipe_state *rstate;
+	unsigned tmp;
+	unsigned prov_vtx = 1, polygon_dual_mode;
+	unsigned clip_rule;
+
+	if (rs == NULL) {
+		return NULL;
+	}
+
+	rstate = &rs->rstate;
+	rs->flatshade = state->flatshade;
+	rs->sprite_coord_enable = state->sprite_coord_enable;
+
+	clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
+
+	/* offset */
+	rs->offset_units = state->offset_units;
+	rs->offset_scale = state->offset_scale * 12.0f;
+
+	rstate->id = R600_PIPE_STATE_RASTERIZER;
+	if (state->flatshade_first)
+		prov_vtx = 0;
+	tmp = 0x00000001;
+	if (state->sprite_coord_enable) {
+		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+			S_0286D4_PNT_SPRITE_OVRD_X(2) |
+			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+			S_0286D4_PNT_SPRITE_OVRD_W(1);
+		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
+		}
+	}
+	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
+
+	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
+				state->fill_back != PIPE_POLYGON_MODE_FILL);
+	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
+		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+		S_028814_FACE(!state->front_ccw) |
+		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
+		S_028814_POLY_MODE(polygon_dual_mode) |
+		S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
+		S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
+			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	/* point size 12.4 fixed point */
+	tmp = (unsigned)(state->point_size * 8.0);
+	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 0x00000005, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
+	return rstate;
+}
+
+static void evergreen_bind_rs_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	if (state == NULL)
+		return;
+
+	rctx->flatshade = rs->flatshade;
+	rctx->sprite_coord_enable = rs->sprite_coord_enable;
+	rctx->rasterizer = rs;
+
+	rctx->states[rs->rstate.id] = &rs->rstate;
+	r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
+}
+
+static void evergreen_delete_rs_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+
+	if (rctx->rasterizer == rs) {
+		rctx->rasterizer = NULL;
+	}
+	if (rctx->states[rs->rstate.id] == &rs->rstate) {
+		rctx->states[rs->rstate.id] = NULL;
+	}
+	free(rs);
+}
+
+static void *evergreen_create_sampler_state(struct pipe_context *ctx,
+					const struct pipe_sampler_state *state)
+{
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	union util_color uc;
+
+	if (rstate == NULL) {
+		return NULL;
+	}
+
+	rstate->id = R600_PIPE_STATE_SAMPLER;
+	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+	r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
+	/* FIXME LOD it depends on texture base level ... */
+	r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
+				S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)) |
+				S_03C008_TYPE(1),
+				0xFFFFFFFF, NULL);
+
+	if (uc.ui) {
+		r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
+	}
+	return rstate;
+}
+
+static void *evergreen_create_vertex_elements(struct pipe_context *ctx,
+				unsigned count,
+				const struct pipe_vertex_element *elements)
+{
+	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+	assert(count < 32);
+	v->count = count;
+	v->refcount = 1;
+	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+	return v;
+}
+
+static void evergreen_sampler_view_destroy(struct pipe_context *ctx,
+				      struct pipe_sampler_view *state)
+{
+	struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
+
+	pipe_resource_reference(&state->texture, NULL);
+	FREE(resource);
+}
+
+static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
+							struct pipe_resource *texture,
+							const struct pipe_sampler_view *state)
+{
+	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
+	struct r600_pipe_state *rstate;
+	const struct util_format_description *desc;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
+	unsigned format;
+	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+	unsigned char swizzle[4];
+	struct r600_bo *bo[2];
+
+	if (resource == NULL)
+		return NULL;
+	rstate = &resource->state;
+
+	/* initialize base object */
+	resource->base = *state;
+	resource->base.texture = NULL;
+	pipe_reference(NULL, &texture->reference);
+	resource->base.texture = texture;
+	resource->base.reference.count = 1;
+	resource->base.context = ctx;
+
+	swizzle[0] = state->swizzle_r;
+	swizzle[1] = state->swizzle_g;
+	swizzle[2] = state->swizzle_b;
+	swizzle[3] = state->swizzle_a;
+	format = r600_translate_texformat(state->format,
+					  swizzle,
+					  &word4, &yuv_format);
+	if (format == ~0) {
+		format = 0;
+	}
+	desc = util_format_description(state->format);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", state->format);
+	}
+	tmp = (struct r600_resource_texture*)texture;
+	rbuffer = &tmp->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	/* FIXME depth texture decompression */
+	if (tmp->depth) {
+		r600_texture_depth_flush(ctx, texture);
+		tmp = (struct r600_resource_texture*)texture;
+		rbuffer = &tmp->flushed_depth_texture->resource;
+		bo[0] = rbuffer->bo;
+		bo[1] = rbuffer->bo;
+	}
+	pitch = align(tmp->pitch_in_pixels[0], 8);
+
+	/* FIXME properly handle first level != 0 */
+	r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0,
+				S_030000_DIM(r600_tex_dim(texture->target)) |
+				S_030000_PITCH((pitch / 8) - 1) |
+				S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
+				S_030004_TEX_HEIGHT(texture->height0 - 1) |
+				S_030004_TEX_DEPTH(texture->depth0 - 1),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
+				(tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
+				(tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
+	r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
+				word4 | S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_NORM) |
+				S_030010_SRF_MODE_ALL(V_030010_SFR_MODE_NO_ZERO) |
+				S_030010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
+				S_030014_LAST_LEVEL(state->last_level) |
+				S_030014_BASE_ARRAY(0) |
+				S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
+	r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
+				S_03001C_DATA_FORMAT(format) |
+				S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+
+	return &resource->base;
+}
+
+static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
+
+	for (int i = 0; i < count; i++) {
+		if (resource[i]) {
+			evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
+		}
+	}
+}
+
+static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
+
+	rctx->ps_samplers.views = resource;
+	rctx->ps_samplers.n_views = count;
+
+	for (int i = 0; i < count; i++) {
+		if (resource[i]) {
+			evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
+		}
+	}
+}
+
+static void evergreen_bind_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+	if (state == NULL)
+		return;
+	rctx->states[rstate->id] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+	rctx->ps_samplers.samplers = states;
+	rctx->ps_samplers.n_samplers = count;
+
+	for (int i = 0; i < count; i++) {
+		evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
+	}
+}
+
+static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
+
+	for (int i = 0; i < count; i++) {
+		evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
+	}
+}
+
+static void evergreen_delete_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
+
+	if (rctx->states[rstate->id] == rstate) {
+		rctx->states[rstate->id] = NULL;
+	}
+	for (int i = 0; i < rstate->nregs; i++) {
+		r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+	}
+	free(rstate);
+}
+
+static void evergreen_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	if (v == NULL)
+		return;
+	if (--v->refcount)
+		return;
+	free(v);
+}
+
+static void evergreen_set_clip_state(struct pipe_context *ctx,
+				const struct pipe_clip_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rctx->clip = *state;
+	rstate->id = R600_PIPE_STATE_CLIP;
+	for (int i = 0; i < state->nr; i++) {
+		r600_pipe_state_add_reg(rstate,
+					R_0285BC_PA_CL_UCP0_X + i * 4,
+					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_0285C0_PA_CL_UCP0_Y + i * 4,
+					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_0285C4_PA_CL_UCP0_Z + i * 4,
+					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_0285C8_PA_CL_UCP0_W + i * 4,
+					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
+	}
+	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
+			S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
+			S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
+			S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_CLIP]);
+	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	evergreen_delete_vertex_element(ctx, rctx->vertex_elements);
+	rctx->vertex_elements = v;
+	if (v) {
+		v->refcount++;
+//		rctx->vs_rebuild = TRUE;
+	}
+}
+
+static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
+					 const struct pipe_poly_stipple *state)
+{
+}
+
+static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void evergreen_set_scissor_state(struct pipe_context *ctx,
+					const struct pipe_scissor_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tl, br;
+
+	if (rstate == NULL)
+		return;
+
+	rstate->id = R600_PIPE_STATE_SCISSOR;
+	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
+	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	r600_pipe_state_add_reg(rstate,
+				R_028210_PA_SC_CLIPRECT_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028214_PA_SC_CLIPRECT_0_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028218_PA_SC_CLIPRECT_1_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_02821C_PA_SC_CLIPRECT_1_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028220_PA_SC_CLIPRECT_2_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028224_PA_SC_CLIPRECT_2_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028228_PA_SC_CLIPRECT_3_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_02822C_PA_SC_CLIPRECT_3_BR, br,
+				0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
+	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_stencil_ref(struct pipe_context *ctx,
+				const struct pipe_stencil_ref *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tmp;
+
+	if (rstate == NULL)
+		return;
+
+	rctx->stencil_ref = *state;
+	rstate->id = R600_PIPE_STATE_STENCIL_REF;
+	tmp = S_028430_STENCILREF(state->ref_value[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_028430_DB_STENCILREFMASK, tmp,
+				~C_028430_STENCILREF, NULL);
+	tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
+	r600_pipe_state_add_reg(rstate,
+				R_028434_DB_STENCILREFMASK_BF, tmp,
+				~C_028434_STENCILREF_BF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+	rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_viewport_state(struct pipe_context *ctx,
+					const struct pipe_viewport_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+
+	if (rstate == NULL)
+		return;
+
+	rctx->viewport = *state;
+	rstate->id = R600_PIPE_STATE_VIEWPORT;
+	r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
+	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state, int cb)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+	struct r600_bo *bo[3];
+
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	bo[2] = rbuffer->bo;
+
+	pitch = rtex->pitch_in_pixels[level] / 8 - 1;
+	slice = rtex->pitch_in_pixels[level] * state->cbufs[cb]->height / 64 - 1;
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_028C70_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+	color_info = S_028C70_FORMAT(format) |
+		S_028C70_COMP_SWAP(swap) |
+		S_028C70_BLEND_CLAMP(1) |
+		S_028C70_NUMBER_TYPE(ntype);
+	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 
+		color_info |= S_028C70_SOURCE_FORMAT(1);
+
+	/* FIXME handle enabling of CB beyond BASE8 which has different offset */
+	r600_pipe_state_add_reg(rstate,
+				R_028C60_CB_COLOR0_BASE + cb * 0x3C,
+				(state->cbufs[cb]->offset +  r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_028C78_CB_COLOR0_DIM + cb * 0x3C,
+				0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028C70_CB_COLOR0_INFO + cb * 0x3C,
+				color_info, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
+				S_028C64_PITCH_TILE_MAX(pitch),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
+				S_028C68_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
+				S_028C74_NON_DISP_TILING_ORDER(1),
+				0xFFFFFFFF, bo[0]);
+}
+
+static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level;
+	unsigned pitch, slice, format, stencil_format;
+
+	if (state->zsbuf == NULL)
+		return;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tiled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	level = state->zsbuf->level;
+	pitch = rtex->pitch_in_pixels[level] / 8 - 1;
+	slice = rtex->pitch_in_pixels[level] * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+	stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format);
+
+	r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
+				(state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+	r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
+				(state->zsbuf->offset  + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+
+	if (stencil_format) {
+		uint32_t stencil_offset;
+
+		stencil_offset = ((state->zsbuf->height * rtex->pitch_in_bytes[level]) + 255) & ~255;
+		r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE,
+					(state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+		r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE,
+					(state->zsbuf->offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+	}
+
+	r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO,
+				S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo);
+
+	r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO,
+				S_028040_ARRAY_MODE(rtex->array_mode) | S_028040_FORMAT(format),
+				0xFFFFFFFF, rbuffer->bo);
+	r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
+				S_028058_PITCH_TILE_MAX(pitch),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
+				S_02805C_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+}
+
+static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
+					const struct pipe_framebuffer_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 shader_mask, tl, br, target_mask;
+
+	if (rstate == NULL)
+		return;
+
+	/* unreference old buffer and reference new one */
+	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
+
+	util_copy_framebuffer_state(&rctx->framebuffer, state);
+
+	rctx->pframebuffer = &rctx->framebuffer;
+
+	/* build states */
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		evergreen_cb(rctx, rstate, state, i);
+	}
+	if (state->zsbuf) {
+		evergreen_db(rctx, rstate, state);
+	}
+
+	target_mask = 0x00000000;
+	target_mask = 0xFFFFFFFF;
+	shader_mask = 0;
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		target_mask ^= 0xf << (i * 4);
+		shader_mask |= 0xf << (i * 4);
+	}
+	tl = S_028240_TL_X(0) | S_028240_TL_Y(0);
+	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
+
+	r600_pipe_state_add_reg(rstate,
+				R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
+				0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
+				0x00000000, target_mask, NULL);
+	r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
+				shader_mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+				0x00000000, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
+	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void evergreen_set_index_buffer(struct pipe_context *ctx,
+				  const struct pipe_index_buffer *ib)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	if (ib) {
+		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+	} else {
+		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+	}
+
+	/* TODO make this more like a state */
+}
+
+static void evergreen_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+					const struct pipe_vertex_buffer *buffers)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	for (int i = 0; i < rctx->nvertex_buffer; i++) {
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	}
+	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+	for (int i = 0; i < count; i++) {
+		rctx->vertex_buffer[i].buffer = NULL;
+		if (r600_buffer_is_user_buffer(buffers[i].buffer))
+			rctx->any_user_vbs = TRUE;
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	}
+	rctx->nvertex_buffer = count;
+}
+
+static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+					struct pipe_resource *buffer)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		rctx->vs_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028980_ALU_CONST_CACHE_VS_0,
+					(r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		rctx->ps_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028940_ALU_CONST_CACHE_PS_0,
+					(r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
+		break;
+	default:
+		R600_ERR("unsupported %d\n", shader);
+		return;
+	}
+}
+
+static void *evergreen_create_shader_state(struct pipe_context *ctx,
+					const struct pipe_shader_state *state)
+{
+	struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
+	int r;
+
+	r =  r600_pipe_shader_create(ctx, shader, state->tokens);
+	if (r) {
+		return NULL;
+	}
+	return shader;
+}
+
+static void evergreen_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->ps_shader = (struct r600_pipe_shader *)state;
+}
+
+static void evergreen_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->vs_shader = (struct r600_pipe_shader *)state;
+}
+
+static void evergreen_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->ps_shader == shader) {
+		rctx->ps_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+static void evergreen_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->vs_shader == shader) {
+		rctx->vs_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+void evergreen_init_state_functions(struct r600_pipe_context *rctx)
+{
+	rctx->context.create_blend_state = evergreen_create_blend_state;
+	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
+	rctx->context.create_fs_state = evergreen_create_shader_state;
+	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
+	rctx->context.create_sampler_state = evergreen_create_sampler_state;
+	rctx->context.create_sampler_view = evergreen_create_sampler_view;
+	rctx->context.create_vertex_elements_state = evergreen_create_vertex_elements;
+	rctx->context.create_vs_state = evergreen_create_shader_state;
+	rctx->context.bind_blend_state = evergreen_bind_blend_state;
+	rctx->context.bind_depth_stencil_alpha_state = evergreen_bind_state;
+	rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler;
+	rctx->context.bind_fs_state = evergreen_bind_ps_shader;
+	rctx->context.bind_rasterizer_state = evergreen_bind_rs_state;
+	rctx->context.bind_vertex_elements_state = evergreen_bind_vertex_elements;
+	rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler;
+	rctx->context.bind_vs_state = evergreen_bind_vs_shader;
+	rctx->context.delete_blend_state = evergreen_delete_state;
+	rctx->context.delete_depth_stencil_alpha_state = evergreen_delete_state;
+	rctx->context.delete_fs_state = evergreen_delete_ps_shader;
+	rctx->context.delete_rasterizer_state = evergreen_delete_rs_state;
+	rctx->context.delete_sampler_state = evergreen_delete_state;
+	rctx->context.delete_vertex_elements_state = evergreen_delete_vertex_element;
+	rctx->context.delete_vs_state = evergreen_delete_vs_shader;
+	rctx->context.set_blend_color = evergreen_set_blend_color;
+	rctx->context.set_clip_state = evergreen_set_clip_state;
+	rctx->context.set_constant_buffer = evergreen_set_constant_buffer;
+	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view;
+	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
+	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
+	rctx->context.set_sample_mask = evergreen_set_sample_mask;
+	rctx->context.set_scissor_state = evergreen_set_scissor_state;
+	rctx->context.set_stencil_ref = evergreen_set_stencil_ref;
+	rctx->context.set_vertex_buffers = evergreen_set_vertex_buffers;
+	rctx->context.set_index_buffer = evergreen_set_index_buffer;
+	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view;
+	rctx->context.set_viewport_state = evergreen_set_viewport_state;
+	rctx->context.sampler_view_destroy = evergreen_sampler_view_destroy;
+}
+
+void evergreen_init_config(struct r600_pipe_context *rctx)
+{
+	struct r600_pipe_state *rstate = &rctx->config;
+	int ps_prio;
+	int vs_prio;
+	int gs_prio;
+	int es_prio;
+	int hs_prio, cs_prio, ls_prio;
+	int num_ps_gprs;
+	int num_vs_gprs;
+	int num_gs_gprs;
+	int num_es_gprs;
+	int num_hs_gprs;
+	int num_ls_gprs;
+	int num_temp_gprs;
+	int num_ps_threads;
+	int num_vs_threads;
+	int num_gs_threads;
+	int num_es_threads;
+	int num_hs_threads;
+	int num_ls_threads;
+	int num_ps_stack_entries;
+	int num_vs_stack_entries;
+	int num_gs_stack_entries;
+	int num_es_stack_entries;
+	int num_hs_stack_entries;
+	int num_ls_stack_entries;
+	enum radeon_family family;
+	unsigned tmp;
+
+	family = r600_get_family(rctx->radeon);
+	ps_prio = 0;
+	vs_prio = 1;
+	gs_prio = 2;
+	es_prio = 3;
+	hs_prio = 0;
+	ls_prio = 0;
+	cs_prio = 0;
+
+	switch (family) {
+	case CHIP_CEDAR:
+	default:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 96;
+		num_vs_threads = 16;
+		num_gs_threads = 16;
+		num_es_threads = 16;
+		num_hs_threads = 16;
+		num_ls_threads = 16;
+		num_ps_stack_entries = 42;
+		num_vs_stack_entries = 42;
+		num_gs_stack_entries = 42;
+		num_es_stack_entries = 42;
+		num_hs_stack_entries = 42;
+		num_ls_stack_entries = 42;
+		break;
+	case CHIP_REDWOOD:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 42;
+		num_vs_stack_entries = 42;
+		num_gs_stack_entries = 42;
+		num_es_stack_entries = 42;
+		num_hs_stack_entries = 42;
+		num_ls_stack_entries = 42;
+		break;
+	case CHIP_JUNIPER:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 85;
+		num_vs_stack_entries = 85;
+		num_gs_stack_entries = 85;
+		num_es_stack_entries = 85;
+		num_hs_stack_entries = 85;
+		num_ls_stack_entries = 85;
+		break;
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		num_ps_gprs = 93;
+		num_vs_gprs = 46;
+		num_temp_gprs = 4;
+		num_gs_gprs = 31;
+		num_es_gprs = 31;
+		num_hs_gprs = 23;
+		num_ls_gprs = 23;
+		num_ps_threads = 128;
+		num_vs_threads = 20;
+		num_gs_threads = 20;
+		num_es_threads = 20;
+		num_hs_threads = 20;
+		num_ls_threads = 20;
+		num_ps_stack_entries = 85;
+		num_vs_stack_entries = 85;
+		num_gs_stack_entries = 85;
+		num_es_stack_entries = 85;
+		num_hs_stack_entries = 85;
+		num_ls_stack_entries = 85;
+		break;
+	}
+
+	tmp = 0x00000000;
+	switch (family) {
+	case CHIP_CEDAR:
+		break;
+	default:
+		tmp |= S_008C00_VC_ENABLE(1);
+		break;
+	}
+	tmp |= S_008C00_EXPORT_SRC_C(1);
+	tmp |= S_008C00_CS_PRIO(cs_prio);
+	tmp |= S_008C00_LS_PRIO(ls_prio);
+	tmp |= S_008C00_HS_PRIO(hs_prio);
+	tmp |= S_008C00_PS_PRIO(ps_prio);
+	tmp |= S_008C00_VS_PRIO(vs_prio);
+	tmp |= S_008C00_GS_PRIO(gs_prio);
+	tmp |= S_008C00_ES_PRIO(es_prio);
+	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
+	r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs);
+	tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs);
+	r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads);
+	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
+	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
+	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
+	r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads);
+	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
+	r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	tmp = 0;
+	tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
+	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
+	r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
+
+//	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL);
+
+//	r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL);
+
+r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
+			0x0, 0xFFFFFFFF, NULL);
+
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate;
+	struct r600_resource *rbuffer;
+	unsigned i, j, offset, prim;
+	u32 vgt_dma_index_type, vgt_draw_initiator, mask;
+	struct pipe_vertex_buffer *vertex_buffer;
+	struct r600_draw rdraw;
+	struct r600_pipe_state vgt;
+	struct r600_drawl draw;
+
+	if (rctx->any_user_vbs) {
+		r600_upload_user_buffers(rctx);
+		rctx->any_user_vbs = FALSE;
+	}
+
+	memset(&draw, 0, sizeof(struct r600_drawl));
+	draw.ctx = ctx;
+	draw.mode = info->mode;
+	draw.start = info->start;
+	draw.count = info->count;
+	if (info->indexed && rctx->index_buffer.buffer) {
+		draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
+		draw.min_index = info->min_index;
+		draw.max_index = info->max_index;
+		draw.index_bias = info->index_bias;
+
+		r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
+					    &rctx->index_buffer.index_size,
+					    &draw.start,
+					    info->count);
+
+		draw.index_size = rctx->index_buffer.index_size;
+		pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
+		draw.index_buffer_offset = draw.start * draw.index_size;
+		draw.start = 0;
+		r600_upload_index_buffer(rctx, &draw);
+	} else {
+		draw.index_size = 0;
+		draw.index_buffer = NULL;
+		draw.min_index = info->min_index;
+		draw.max_index = info->max_index;
+		draw.index_bias = info->start;
+	}
+
+	switch (draw.index_size) {
+	case 2:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 0;
+		break;
+	case 4:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 1;
+		break;
+	case 0:
+		vgt_draw_initiator = 2;
+		vgt_dma_index_type = 0;
+		break;
+	default:
+		R600_ERR("unsupported index size %d\n", draw.index_size);
+		return;
+	}
+	if (r600_conv_pipe_prim(draw.mode, &prim))
+		return;
+
+	/* rebuild vertex shader if input format changed */
+	if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
+		return;
+	if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
+		return;
+
+	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+		uint32_t word3, word2;
+		uint32_t format;
+		rstate = &rctx->vs_resource[i];
+
+		rstate->id = R600_PIPE_STATE_RESOURCE;
+		rstate->nregs = 0;
+
+		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
+		vertex_buffer = &rctx->vertex_buffer[j];
+		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+		offset = rctx->vertex_elements->elements[i].src_offset +
+			vertex_buffer->buffer_offset +
+			r600_bo_offset(rbuffer->bo);
+
+		format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
+
+		word2 = format | S_030008_STRIDE(vertex_buffer->stride);
+
+		word3 = r600_translate_vertex_data_swizzle(rctx->vertex_elements->elements[i].src_format);
+
+		r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
+		r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, word3, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC0000000, 0xFFFFFFFF, NULL);
+		evergreen_vs_resource_set(&rctx->ctx, rstate, i);
+	}
+
+	mask = 0;
+	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+		mask |= (0xF << (i * 4));
+	}
+
+	vgt.id = R600_PIPE_STATE_VGT;
+	vgt.nregs = 0;
+	r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw.index_bias, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw.max_index, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw.min_index, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
+
+	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
+		float offset_units = rctx->rasterizer->offset_units;
+		unsigned offset_db_fmt_cntl = 0, depth;
+
+		switch (rctx->framebuffer.zsbuf->texture->format) {
+		case PIPE_FORMAT_Z24X8_UNORM:
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			depth = -24;
+			offset_units *= 2.0f;
+			break;
+		case PIPE_FORMAT_Z32_FLOAT:
+			depth = -23;
+			offset_units *= 1.0f;
+			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			depth = -16;
+			offset_units *= 4.0f;
+			break;
+		default:
+			return;
+		}
+		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+		r600_pipe_state_add_reg(&vgt,
+				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
+				fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
+				fui(offset_units), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
+				fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
+				fui(offset_units), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+				offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+	}
+	r600_context_pipe_state_set(&rctx->ctx, &vgt);
+
+	rdraw.vgt_num_indices = draw.count;
+	rdraw.vgt_num_instances = 1;
+	rdraw.vgt_index_type = vgt_dma_index_type;
+	rdraw.vgt_draw_initiator = vgt_draw_initiator;
+	rdraw.indices = NULL;
+	if (draw.index_buffer) {
+		rbuffer = (struct r600_resource*)draw.index_buffer;
+		rdraw.indices = rbuffer->bo;
+		rdraw.indices_bo_offset = draw.index_buffer_offset;
+	}
+	evergreen_context_draw(&rctx->ctx, &rdraw);
+
+	pipe_resource_reference(&draw.index_buffer, NULL);
+}
+
+void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
+	int pos_index = -1, face_index = -1;
+	int ninterp = 0;
+	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
+	unsigned spi_baryc_cntl;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	for (i = 0; i < rshader->ninput; i++) {
+		tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
+		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
+		   POSITION goes via GPRs from the SC so isn't counted */
+		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+			pos_index = i;
+		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
+			face_index = i;
+		else {
+			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR ||
+			    rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
+				ninterp++;
+			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
+				have_linear = TRUE;
+			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
+				have_perspective = TRUE;
+			if (rshader->input[i].centroid)
+				have_centroid = TRUE;
+		}
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
+		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+			rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
+			tmp |= S_028644_PT_SPRITE_TEX(1);
+		}
+		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+	}
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			r600_pipe_state_add_reg(rstate,
+						R_02880C_DB_SHADER_CONTROL,
+						S_02880C_Z_EXPORT_ENABLE(1),
+						S_02880C_Z_EXPORT_ENABLE(1), NULL);
+		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
+			r600_pipe_state_add_reg(rstate,
+						R_02880C_DB_SHADER_CONTROL,
+						S_02880C_STENCIL_EXPORT_ENABLE(1),
+						S_02880C_STENCIL_EXPORT_ENABLE(1), NULL);
+	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
+		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			num_cout++;
+		}
+	}
+	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
+	if (!exports_ps) {
+		/* always at least export 1 component per pixel */
+		exports_ps = 2;
+	}
+
+	if (ninterp == 0) {
+		ninterp = 1;
+		have_perspective = TRUE;
+	}
+
+	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
+		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
+		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
+	spi_input_z = 0;
+	if (pos_index != -1) {
+		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
+			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
+			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
+		spi_input_z |= 1;
+	}
+
+	spi_ps_in_control_1 = 0;
+	if (face_index != -1) {
+		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
+			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
+	}
+
+	spi_baryc_cntl = 0;
+	if (have_perspective)
+		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
+				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
+	if (have_linear)
+		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
+			          S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
+				
+	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
+				spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
+				spi_ps_in_control_1, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
+				0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_0286E0_SPI_BARYC_CNTL,
+				spi_baryc_cntl,
+				0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate,
+				R_028840_SQ_PGM_START_PS,
+				(r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate,
+				R_028844_SQ_PGM_RESOURCES_PS,
+				S_028844_NUM_GPRS(rshader->bc.ngpr) |
+				S_028844_PRIME_CACHE_ON_DRAW(1) |
+				S_028844_STACK_SIZE(rshader->bc.nstack),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028848_SQ_PGM_RESOURCES_2_PS,
+				0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_02884C_SQ_PGM_EXPORTS_PS,
+				exports_ps, 0xFFFFFFFF, NULL);
+
+	if (rshader->uses_kill) {
+		/* only set some bits here, the other bits are set in the dsa state */
+		r600_pipe_state_add_reg(rstate,
+					R_02880C_DB_SHADER_CONTROL,
+					S_02880C_KILL_ENABLE(1),
+					S_02880C_KILL_ENABLE(1), NULL);
+	}
+
+	r600_pipe_state_add_reg(rstate,
+				R_03A200_SQ_LOOP_CONST_0, 0x01000FFF,
+				0xFFFFFFFF, NULL);
+}
+
+void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned spi_vs_out_id[10];
+	unsigned i, tmp;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	/* so far never got proper semantic id from tgsi */
+	for (i = 0; i < 10; i++) {
+		spi_vs_out_id[i] = 0;
+	}
+	for (i = 0; i < 32; i++) {
+		tmp = i << ((i & 3) * 8);
+		spi_vs_out_id[i / 4] |= tmp;
+	}
+	for (i = 0; i < 10; i++) {
+		r600_pipe_state_add_reg(rstate,
+					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
+					spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+	}
+
+	r600_pipe_state_add_reg(rstate,
+			R_0286C4_SPI_VS_OUT_CONFIG,
+			S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_028860_SQ_PGM_RESOURCES_VS,
+			S_028860_NUM_GPRS(rshader->bc.ngpr) |
+			S_028860_STACK_SIZE(rshader->bc.nstack),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028864_SQ_PGM_RESOURCES_2_VS,
+				0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_0288A8_SQ_PGM_RESOURCES_FS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_02885C_SQ_PGM_START_VS,
+			(r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate,
+			R_0288A4_SQ_PGM_START_FS,
+			(r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo);
+
+	r600_pipe_state_add_reg(rstate,
+				R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
+				0xFFFFFFFF, NULL);
+}
+
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_pipe_state *rstate;
+
+	memset(&dsa, 0, sizeof(dsa));
+
+	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	r600_pipe_state_add_reg(rstate,
+				R_02880C_DB_SHADER_CONTROL,
+				0x0,
+				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028000_DB_RENDER_CONTROL,
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1),
+				S_028000_DEPTH_COPY_ENABLE(1) |
+				S_028000_STENCIL_COPY_ENABLE(1) |
+				S_028000_COPY_CENTROID(1), NULL);
+	return rstate;
+}
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 77cd8f1588..8e96f9355e 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -26,6 +26,26 @@
 #ifndef EVERGREEND_H
 #define EVERGREEND_H
 
+/* evergreen values */
+#define EVERGREEN_CONFIG_REG_OFFSET                 0X00008000
+#define EVERGREEN_CONFIG_REG_END                    0X0000AC00
+#define EVERGREEN_CONTEXT_REG_OFFSET                0X00028000
+#define EVERGREEN_CONTEXT_REG_END                   0X00029000
+#define EVERGREEN_RESOURCE_OFFSET                   0x00030000
+#define EVERGREEN_RESOURCE_END                      0x00034000
+#define EVERGREEN_LOOP_CONST_OFFSET                 0x0003A200
+#define EVERGREEN_LOOP_CONST_END                    0x0003A26C
+#define EVERGREEN_BOOL_CONST_OFFSET                 0x0003A500
+#define EVERGREEN_BOOL_CONST_END                    0x0003A506
+#define EVERGREEN_SAMPLER_OFFSET                    0X0003C000
+#define EVERGREEN_SAMPLER_END                       0X0003CFF0
+
+#define EVERGREEN_CTL_CONST_OFFSET                  0x0003CFF0
+#define EVERGREEN_CTL_CONST_END                     0x0003E200
+
+#define EVENT_TYPE_ZPASS_DONE                  0x15
+#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
+
 #define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
 
 #define PKT3_NOP                               0x10
@@ -309,7 +329,7 @@
 #define   S_028C74_NON_DISP_TILING_ORDER(x)            (((x) & 0x1) << 4)
 #define   G_028C74_NON_DISP_TILING_ORDER(x)            (((x) >> 4) & 0x1)
 #define   C_028C74_NON_DISP_TILING_ORDER               0xFFFFFFEF
- 
+
 #define R_028C78_CB_COLOR0_DIM                         0x028C78
 #define   S_028C78_WIDTH_MAX(x)                        (((x) & 0xFFFF) << 0)
 #define   G_028C78_WIDTH_MAX(x)                        (((x) >> 0) & 0xFFFF)
@@ -662,60 +682,13 @@
 #define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
 #define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
 #define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
-#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
-#define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
-#define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
-#define   S_028D0C_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
-#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
-#define   V_028D10_FORCE_OFF                         0
-#define   V_028D10_FORCE_ENABLE                      1
-#define   V_028D10_FORCE_DISABLE                     2
-#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
-#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
-#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
-#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
-#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
-#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
-#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
-#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
-#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
-#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
-#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
-#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
-#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
-#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
-#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
-#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
-#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
-#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
-#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
-#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
-#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
-#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
-#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
-#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
-#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
-#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
-#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
-#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
-#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
-#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
-#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
-#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
-#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
-#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
-#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
-#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
-#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
-#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
-#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
-#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
-#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
-#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
 #define R_02880C_DB_SHADER_CONTROL                    0x02880C
 #define   S_02880C_Z_EXPORT_ENABLE(x)                  (((x) & 0x1) << 0)
 #define   G_02880C_Z_EXPORT_ENABLE(x)                  (((x) >> 0) & 0x1)
 #define   C_02880C_Z_EXPORT_ENABLE                     0xFFFFFFFE
+#define   S_02880C_STENCIL_EXPORT_ENABLE(x)            (((x) & 0x1) << 1)
+#define   G_02880C_STENCIL_EXPORT_ENABLE(x)            (((x) >> 1) & 0x1)
+#define   C_02880C_STENCIL_EXPORT_ENABLE               0xFFFFFFFD
 #define   S_02880C_Z_ORDER(x)                          (((x) & 0x3) << 4)
 #define   G_02880C_Z_ORDER(x)                          (((x) >> 4) & 0x3)
 #define   C_02880C_Z_ORDER                             0xFFFFFCFF
@@ -729,29 +702,6 @@
 #define   S_02880C_DUAL_EXPORT_ENABLE(x)               (((x) & 0x1) << 9)
 #define   G_02880C_DUAL_EXPORT_ENABLE(x)               (((x) >> 9) & 0x1)
 #define   C_02880C_DUAL_EXPORT_ENABLE                  0xFFFFFDFF
-#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
-#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
-#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
-#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
-#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
-#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
-#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
-#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
-#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E00_SCALE                               0x00000000
-#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
-#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E04_OFFSET                              0x00000000
-#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
-#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E08_SCALE                               0x00000000
-#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
-#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
-#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
-#define   C_028E0C_OFFSET                              0x00000000
 #define R_028A00_PA_SU_POINT_SIZE                    0x028A00
 #define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
 #define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
@@ -1037,9 +987,6 @@
 #define   S_030010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
 #define   G_030010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
 #define   C_030010_ENDIAN_SWAP                         0xFFFFCFFF
-#define   S_030010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
-#define   G_030010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
-#define   C_030010_REQUEST_SIZE                        0xFFFF3FFF
 #define   S_030010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
 #define   G_030010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
 #define   C_030010_DST_SEL_X                           0xFFF8FFFF
@@ -1103,43 +1050,12 @@
 #define   S_030008_DATA_FORMAT(x)                      (((x) & 0x3F) << 20)
 #define   G_030008_DATA_FORMAT(x)                      (((x) >> 20) & 0x3F)
 #define   C_030008_DATA_FORMAT                         0xFC0FFFFF
-#define     V_030008_COLOR_INVALID                     0x00000000
-#define     V_030008_COLOR_8                           0x00000001
-#define     V_030008_COLOR_4_4                         0x00000002
-#define     V_030008_COLOR_3_3_2                       0x00000003
-#define     V_030008_COLOR_16                          0x00000005
-#define     V_030008_COLOR_16_FLOAT                    0x00000006
-#define     V_030008_COLOR_8_8                         0x00000007
-#define     V_030008_COLOR_5_6_5                       0x00000008
-#define     V_030008_COLOR_6_5_5                       0x00000009
-#define     V_030008_COLOR_1_5_5_5                     0x0000000A
-#define     V_030008_COLOR_4_4_4_4                     0x0000000B
-#define     V_030008_COLOR_5_5_5_1                     0x0000000C
-#define     V_030008_COLOR_32                          0x0000000D
-#define     V_030008_COLOR_32_FLOAT                    0x0000000E
-#define     V_030008_COLOR_16_16                       0x0000000F
-#define     V_030008_COLOR_16_16_FLOAT                 0x00000010
-#define     V_030008_COLOR_8_24                        0x00000011
-#define     V_030008_COLOR_8_24_FLOAT                  0x00000012
-#define     V_030008_COLOR_24_8                        0x00000013
-#define     V_030008_COLOR_24_8_FLOAT                  0x00000014
-#define     V_030008_COLOR_10_11_11                    0x00000015
-#define     V_030008_COLOR_10_11_11_FLOAT              0x00000016
-#define     V_030008_COLOR_11_11_10                    0x00000017
-#define     V_030008_COLOR_11_11_10_FLOAT              0x00000018
-#define     V_030008_COLOR_2_10_10_10                  0x00000019
-#define     V_030008_COLOR_8_8_8_8                     0x0000001A
-#define     V_030008_COLOR_10_10_10_2                  0x0000001B
-#define     V_030008_COLOR_X24_8_32_FLOAT              0x0000001C
-#define     V_030008_COLOR_32_32                       0x0000001D
-#define     V_030008_COLOR_32_32_FLOAT                 0x0000001E
-#define     V_030008_COLOR_16_16_16_16                 0x0000001F
-#define     V_030008_COLOR_16_16_16_16_FLOAT           0x00000020
-#define     V_030008_COLOR_32_32_32_32                 0x00000022
-#define     V_030008_COLOR_32_32_32_32_FLOAT           0x00000023
 #define   S_030008_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 26)
 #define   G_030008_NUM_FORMAT_ALL(x)                   (((x) >> 26) & 0x3)
 #define   C_030008_NUM_FORMAT_ALL                      0xF3FFFFFF
+#define     V_030008_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_030008_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_030008_SQ_NUM_FORMAT_SCALED              0x00000002
 #define   S_030008_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 28)
 #define   G_030008_FORMAT_COMP_ALL(x)                  (((x) >> 28) & 0x1)
 #define   C_030008_FORMAT_COMP_ALL                     0xEFFFFFFF
@@ -1166,6 +1082,22 @@
 #define   S_03000C_DST_SEL_W(x)                        (((x) & 0x7) << 12)
 #define   G_03000C_DST_SEL_W(x)                        (((x) >> 12) & 0x7)
 
+#define R_00A400_TD_PS_SAMPLER0_BORDER_INDEX         0x00A400
+#define R_00A404_TD_PS_SAMPLER0_BORDER_RED           0x00A404
+#define R_00A408_TD_PS_SAMPLER0_BORDER_GREEN         0x00A408
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE          0x00A40C
+#define R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA         0x00A410
+#define R_00A414_TD_VS_SAMPLER0_BORDER_INDEX         0x00A414
+#define R_00A418_TD_VS_SAMPLER0_BORDER_RED           0x00A418
+#define R_00A41C_TD_VS_SAMPLER0_BORDER_GREEN         0x00A41C
+#define R_00A420_TD_VS_SAMPLER0_BORDER_BLUE          0x00A420
+#define R_00A424_TD_VS_SAMPLER0_BORDER_ALPHA         0x00A424
+#define R_00A428_TD_GS_SAMPLER0_BORDER_INDEX         0x00A428
+#define R_00A42C_TD_GS_SAMPLER0_BORDER_RED           0x00A42C
+#define R_00A430_TD_GS_SAMPLER0_BORDER_GREEN         0x00A430
+#define R_00A434_TD_GS_SAMPLER0_BORDER_BLUE          0x00A434
+#define R_00A438_TD_GS_SAMPLER0_BORDER_ALPHA         0x00A438
+
 #define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
 #define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
 #define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
@@ -1456,4 +1388,488 @@
 #define SQ_TEX_INST_SAMPLE 0x10
 #define SQ_TEX_INST_SAMPLE_L 0x11
 #define SQ_TEX_INST_SAMPLE_C 0x18
+
+#define R_008A14_PA_CL_ENHANCE                       0x00008A14
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x00008C0C
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x00008D8C
+#define R_028000_DB_RENDER_CONTROL                   0x00028000
+#define   S_028000_DEPTH_CLEAR_ENABLE(x)               (((x) & 0x1) << 0)
+#define   S_028000_STENCIL_CLEAR_ENABLE(x)             (((x) & 0x1) << 1)
+#define   S_028000_DEPTH_COPY_ENABLE(x)                (((x) & 0x1) << 2)
+#define   S_028000_STENCIL_COPY_ENABLE(x)              (((x) & 0x1) << 3)
+#define   S_028000_RESUMMARIZE_ENABLE(x)               (((x) & 0x1) << 4)
+#define   S_028000_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
+#define   S_028000_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028000_COPY_CENTROID(x)                    (((x) & 0x1) << 7)
+#define   S_028000_COPY_SAMPLE(x)                      (((x) & 0x7) << 8)
+#define   S_028000_COLOR_DISABLE(x)                    (((x) & 0x1) << 12)
+#define R_028004_DB_COUNT_CONTROL                    0x00028004
+#define   S_028004_ZPASS_INCREMENT_DISABLE        (((x) & 0x1) << 0)
+#define   S_028004_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 1)
+#define R_028008_DB_DEPTH_VIEW                       0x00028008
+#define R_02800C_DB_RENDER_OVERRIDE                  0x0002800C
+#define   V_02800C_FORCE_OFF                         0
+#define   V_02800C_FORCE_ENABLE                      1
+#define   V_02800C_FORCE_DISABLE                     2
+#define   S_02800C_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_02800C_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_02800C_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_02800C_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_02800C_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_02800C_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_02800C_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_02800C_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_02800C_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_02800C_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_02800C_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_02800C_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_02800C_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_02800C_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_02800C_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_02800C_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_02800C_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_02800C_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_02800C_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_02800C_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_02800C_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_02800C_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_02800C_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_02800C_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_02800C_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_02800C_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_02800C_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_02800C_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_02800C_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_02800C_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_02800C_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_02800C_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_02800C_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_02800C_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_02800C_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_02800C_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_02800C_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_02800C_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_02800C_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_02800C_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_02800C_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_02800C_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028010_DB_RENDER_OVERRIDE2                 0x00028010
+#define R_028014_DB_HTILE_DATA_BASE                  0x00028014
+#define R_028028_DB_STENCIL_CLEAR                    0x00028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x0002802C
+#define R_028048_DB_Z_READ_BASE                      0x00028048
+#define R_02804C_DB_STENCIL_READ_BASE                0x0002804C
+#define R_028050_DB_Z_WRITE_BASE                     0x00028050
+#define R_028054_DB_STENCIL_WRITE_BASE               0x00028054
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x00028200
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x0002820C
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x00028210
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x00028214
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x00028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x0002821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x00028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x00028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x00028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x0002822C
+#define R_028230_PA_SC_EDGERULE                      0x00028230
+#define R_028234_PA_SU_HARDWARE_SCREEN_OFFSET        0x00028234
+#define R_028238_CB_TARGET_MASK                      0x00028238
+#define R_02823C_CB_SHADER_MASK                      0x0002823C
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x00028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x00028254
+#define R_028350_SX_MISC                             0x00028350
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x00028380
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x00028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x00028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x0002838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x00028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x00028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x00028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x0002839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x000283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x000283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x000283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x000283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x000283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x000283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x000283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x000283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x000283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x000283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x000283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x000283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x000283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x000283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x000283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x000283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x000283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x000283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x000283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x000283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x000283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x000283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x000283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x000283FC
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x000282D0
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x000282D4
+#define R_028400_VGT_MAX_VTX_INDX                    0x00028400
+#define R_028404_VGT_MIN_VTX_INDX                    0x00028404
+#define R_028408_VGT_INDX_OFFSET                     0x00028408
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x0002840C
+#define R_028414_CB_BLEND_RED                        0x00028414
+#define R_028418_CB_BLEND_GREEN                      0x00028418
+#define R_02841C_CB_BLEND_BLUE                       0x0002841C
+#define R_028420_CB_BLEND_ALPHA                      0x00028420
+#define R_028438_SX_ALPHA_REF                        0x00028438
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x0002843C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x00028440
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x00028444
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x00028448
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x0002844C
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x00028450
+#define R_0285BC_PA_CL_UCP0_X                        0x000285BC
+#define R_0285C0_PA_CL_UCP0_Y                        0x000285C0
+#define R_0285C4_PA_CL_UCP0_Z                        0x000285C4
+#define R_0285C8_PA_CL_UCP0_W                        0x000285C8
+#define R_0285CC_PA_CL_UCP1_X                        0x000285CC
+#define R_0285D0_PA_CL_UCP1_Y                        0x000285D0
+#define R_0285D4_PA_CL_UCP1_Z                        0x000285D4
+#define R_0285D8_PA_CL_UCP1_W                        0x000285D8
+#define R_0285DC_PA_CL_UCP2_X                        0x000285DC
+#define R_0285E0_PA_CL_UCP2_Y                        0x000285E0
+#define R_0285E4_PA_CL_UCP2_Z                        0x000285E4
+#define R_0285E8_PA_CL_UCP2_W                        0x000285E8
+#define R_0285EC_PA_CL_UCP3_X                        0x000285EC
+#define R_0285F0_PA_CL_UCP3_Y                        0x000285F0
+#define R_0285F4_PA_CL_UCP3_Z                        0x000285F4
+#define R_0285F8_PA_CL_UCP3_W                        0x000285F8
+#define R_0285FC_PA_CL_UCP4_X                        0x000285FC
+#define R_028600_PA_CL_UCP4_Y                        0x00028600
+#define R_028604_PA_CL_UCP4_Z                        0x00028604
+#define R_028608_PA_CL_UCP4_W                        0x00028608
+#define R_02860C_PA_CL_UCP5_X                        0x0002860C
+#define R_028610_PA_CL_UCP5_Y                        0x00028610
+#define R_028614_PA_CL_UCP5_Z                        0x00028614
+#define R_028618_PA_CL_UCP5_W                        0x00028618
+#define R_02861C_SPI_VS_OUT_ID_0                     0x0002861C
+#define R_028620_SPI_VS_OUT_ID_1                     0x00028620
+#define R_028624_SPI_VS_OUT_ID_2                     0x00028624
+#define R_028628_SPI_VS_OUT_ID_3                     0x00028628
+#define R_02862C_SPI_VS_OUT_ID_4                     0x0002862C
+#define R_028630_SPI_VS_OUT_ID_5                     0x00028630
+#define R_028634_SPI_VS_OUT_ID_6                     0x00028634
+#define R_028638_SPI_VS_OUT_ID_7                     0x00028638
+#define R_02863C_SPI_VS_OUT_ID_8                     0x0002863C
+#define R_028640_SPI_VS_OUT_ID_9                     0x00028640
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x00028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x0002864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x00028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x00028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x00028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x0002865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x00028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x00028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x00028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x0002866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x00028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x00028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x00028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x0002867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x00028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x00028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x00028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x0002868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x00028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x00028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x00028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x0002869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x000286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x000286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x000286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x000286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x000286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x000286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x000286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x000286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x000286C0
+#define R_0286C8_SPI_THREAD_GROUPING                 0x000286C8
+#define R_0286D8_SPI_INPUT_Z                         0x000286D8
+#define R_0286DC_SPI_FOG_CNTL                        0x000286DC
+#define R_0286E4_SPI_PS_IN_CONTROL_2                 0x000286E4
+#define R_0286E8_SPI_COMPUTE_INPUT_CNTL              0x000286E8
+#define R_028780_CB_BLEND0_CONTROL                   0x00028780
+#define R_028784_CB_BLEND1_CONTROL                   0x00028784
+#define R_028788_CB_BLEND2_CONTROL                   0x00028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x0002878C
+#define R_028790_CB_BLEND4_CONTROL                   0x00028790
+#define R_028794_CB_BLEND5_CONTROL                   0x00028794
+#define R_028798_CB_BLEND6_CONTROL                   0x00028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x0002879C
+#define R_028818_PA_CL_VTE_CNTL                      0x00028818
+#define R_028820_PA_CL_NANINF_CNTL                   0x00028820
+#define R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1         0x00028838
+#define R_028840_SQ_PGM_START_PS                     0x00028840
+#define R_02884C_SQ_PGM_EXPORTS_PS                   0x0002884C
+#define   S_02884C_EXPORT_COLORS(x)                    (((x) & 0xF) << 1)
+#define   G_02884C_EXPORT_COLORS(x)                    (((x) >> 1) & 0xF)
+#define   C_02884C_EXPORT_COLORS                       0xFFFFFFE1
+#define   S_02884C_EXPORT_Z(x)                         (((x) & 0x1) << 0)
+#define   G_02884C_EXPORT_Z(x)                         (((x) >> 0) & 0x1)
+#define   C_02884C_EXPORT_Z                            0xFFFFFFFE
+#define R_02885C_SQ_PGM_START_VS                     0x0002885C
+#define R_0288A4_SQ_PGM_START_FS                     0x000288A4
+#define R_0288A8_SQ_PGM_RESOURCES_FS                 0x000288A8
+#define R_0288EC_SQ_LDS_ALLOC_PS                     0x000288EC
+#define R_028900_SQ_ESGS_RING_ITEMSIZE               0x00028900
+#define R_028904_SQ_GSVS_RING_ITEMSIZE               0x00028904
+#define R_028908_SQ_ESTMP_RING_ITEMSIZE              0x00028908
+#define R_02890C_SQ_GSTMP_RING_ITEMSIZE              0x0002890C
+#define R_028910_SQ_VSTMP_RING_ITEMSIZE              0x00028910
+#define R_028914_SQ_PSTMP_RING_ITEMSIZE              0x00028914
+#define R_02891C_SQ_GS_VERT_ITEMSIZE                 0x0002891C
+#define R_028920_SQ_GS_VERT_ITEMSIZE_1               0x00028920
+#define R_028924_SQ_GS_VERT_ITEMSIZE_2               0x00028924
+#define R_028928_SQ_GS_VERT_ITEMSIZE_3               0x00028928
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+#define R_028A04_PA_SU_POINT_MINMAX                  0x00028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x00028A08
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x00028A10
+#define R_028A14_VGT_HOS_CNTL                        0x00028A14
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x00028A18
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x00028A1C
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x00028A20
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x00028A24
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x00028A28
+#define R_028A2C_VGT_GROUP_DECR                      0x00028A2C
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x00028A30
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x00028A34
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x00028A38
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x00028A3C
+#define R_028A48_PA_SC_MODE_CNTL_0                   0x00028A48
+#define R_028A4C_PA_SC_MODE_CNTL_1                   0x00028A4C
+#define R_028AB4_VGT_REUSE_OFF                       0x00028AB4
+#define R_028AB8_VGT_VTX_CNT_EN                      0x00028AB8
+#define R_028ABC_DB_HTILE_SURFACE                    0x00028ABC
+#define R_028AC0_DB_SRESULTS_COMPARE_STATE0          0x00028AC0
+#define R_028AC4_DB_SRESULTS_COMPARE_STATE1          0x00028AC4
+#define R_028AC8_DB_PRELOAD_CONTROL                  0x00028AC8
+#define R_028B54_VGT_SHADER_STAGES_EN                0x00028B54
+#define R_028B70_DB_ALPHA_TO_MASK                    0x00028B70
+#define R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x00028B78
+#define   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028B78_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028B7C_PA_SU_POLY_OFFSET_CLAMP             0x00028B7C
+#define R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE       0x00028B80
+#define   S_028B80_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B80_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B80_SCALE                               0x00000000
+#define R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x00028B84
+#define   S_028B84_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B84_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B84_OFFSET                              0x00000000
+#define R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE        0x00028B88
+#define   S_028B88_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B88_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B88_SCALE                               0x00000000
+#define R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x00028B8C
+#define   S_028B8C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028B8C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028B8C_OFFSET                              0x00000000
+#define R_028B94_VGT_STRMOUT_CONFIG                  0x00028B94
+#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG           0x00028B98
+#define R_028C00_PA_SC_LINE_CNTL                     0x00028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x00028C04
+#define R_028C08_PA_SU_VTX_CNTL                      0x00028C08
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x00028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x00028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x00028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x00028C18
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x00028C1C
+#define R_028C3C_PA_SC_AA_MASK                       0x00028C3C
+#define R_028C60_CB_COLOR0_BASE                      0x00028C60
+#define R_028C6C_CB_COLOR0_VIEW                      0x00028C6C
+#define R_028C9C_CB_COLOR1_BASE                      0x00028C9C
+#define R_028CA0_CB_COLOR1_PITCH                     0x00028CA0
+#define R_028CA4_CB_COLOR1_SLICE                     0x00028CA4
+#define R_028CA8_CB_COLOR1_VIEW                      0x00028CA8
+#define R_028CAC_CB_COLOR1_INFO                      0x00028CAC
+#define R_028CB0_CB_COLOR1_ATTRIB                    0x00028CB0
+#define R_028CB4_CB_COLOR1_DIM                       0x00028CB4
+#define R_028CD8_CB_COLOR2_BASE                      0x00028CD8
+#define R_028CDC_CB_COLOR2_PITCH                     0x00028CDC
+#define R_028CE0_CB_COLOR2_SLICE                     0x00028CE0
+#define R_028CE4_CB_COLOR2_VIEW                      0x00028CE4
+#define R_028CE8_CB_COLOR2_INFO                      0x00028CE8
+#define R_028CEC_CB_COLOR2_ATTRIB                    0x00028CEC
+#define R_028CF0_CB_COLOR2_DIM                       0x00028CF0
+#define R_028D14_CB_COLOR3_BASE                      0x00028D14
+#define R_028D18_CB_COLOR3_PITCH                     0x00028D18
+#define R_028D1C_CB_COLOR3_SLICE                     0x00028D1C
+#define R_028D20_CB_COLOR3_VIEW                      0x00028D20
+#define R_028D24_CB_COLOR3_INFO                      0x00028D24
+#define R_028D28_CB_COLOR3_ATTRIB                    0x00028D28
+#define R_028D2C_CB_COLOR3_DIM                       0x00028D2C
+#define R_028D50_CB_COLOR4_BASE                      0x00028D50
+#define R_028D54_CB_COLOR4_PITCH                     0x00028D54
+#define R_028D58_CB_COLOR4_SLICE                     0x00028D58
+#define R_028D5C_CB_COLOR4_VIEW                      0x00028D5C
+#define R_028D60_CB_COLOR4_INFO                      0x00028D60
+#define R_028D64_CB_COLOR4_ATTRIB                    0x00028D64
+#define R_028D68_CB_COLOR4_DIM                       0x00028D68
+#define R_028D8C_CB_COLOR5_BASE                      0x00028D8C
+#define R_028D90_CB_COLOR5_PITCH                     0x00028D90
+#define R_028D94_CB_COLOR5_SLICE                     0x00028D94
+#define R_028D98_CB_COLOR5_VIEW                      0x00028D98
+#define R_028D9C_CB_COLOR5_INFO                      0x00028D9C
+#define R_028DA0_CB_COLOR5_ATTRIB                    0x00028DA0
+#define R_028DA4_CB_COLOR5_DIM                       0x00028DA4
+#define R_028DC8_CB_COLOR6_BASE                      0x00028DC8
+#define R_028DCC_CB_COLOR6_PITCH                     0x00028DCC
+#define R_028DD0_CB_COLOR6_SLICE                     0x00028DD0
+#define R_028DD4_CB_COLOR6_VIEW                      0x00028DD4
+#define R_028DD8_CB_COLOR6_INFO                      0x00028DD8
+#define R_028DDC_CB_COLOR6_ATTRIB                    0x00028DDC
+#define R_028DE0_CB_COLOR6_DIM                       0x00028DE0
+#define R_028E04_CB_COLOR7_BASE                      0x00028E04
+#define R_028E08_CB_COLOR7_PITCH                     0x00028E08
+#define R_028E0C_CB_COLOR7_SLICE                     0x00028E0C
+#define R_028E10_CB_COLOR7_VIEW                      0x00028E10
+#define R_028E14_CB_COLOR7_INFO                      0x00028E14
+#define R_028E18_CB_COLOR7_ATTRIB                    0x00028E18
+#define R_028E1C_CB_COLOR7_DIM                       0x00028E1C
+#define R_028E40_CB_COLOR8_BASE                      0x00028E40
+#define R_028E44_CB_COLOR8_PITCH                     0x00028E44
+#define R_028E48_CB_COLOR8_SLICE                     0x00028E48
+#define R_028E4C_CB_COLOR8_VIEW                      0x00028E4C
+#define R_028E50_CB_COLOR8_INFO                      0x00028E50
+#define R_028E54_CB_COLOR8_ATTRIB                    0x00028E54
+#define R_028E58_CB_COLOR8_DIM                       0x00028E58
+#define R_028E5C_CB_COLOR9_BASE                      0x00028E5C
+#define R_028E60_CB_COLOR9_PITCH                     0x00028E60
+#define R_028E64_CB_COLOR9_SLICE                     0x00028E64
+#define R_028E68_CB_COLOR9_VIEW                      0x00028E68
+#define R_028E6C_CB_COLOR9_INFO                      0x00028E6C
+#define R_028E70_CB_COLOR9_ATTRIB                    0x00028E70
+#define R_028E74_CB_COLOR9_DIM                       0x00028E74
+#define R_028E78_CB_COLOR10_BASE                     0x00028E78
+#define R_028E7C_CB_COLOR10_PITCH                    0x00028E7C
+#define R_028E80_CB_COLOR10_SLICE                    0x00028E80
+#define R_028E84_CB_COLOR10_VIEW                     0x00028E84
+#define R_028E88_CB_COLOR10_INFO                     0x00028E88
+#define R_028E8C_CB_COLOR10_ATTRIB                   0x00028E8C
+#define R_028E90_CB_COLOR10_DIM                      0x00028E90
+#define R_028E94_CB_COLOR11_BASE                     0x00028E94
+#define R_028E98_CB_COLOR11_PITCH                    0x00028E98
+#define R_028E9C_CB_COLOR11_SLICE                    0x00028E9C
+#define R_028EA0_CB_COLOR11_VIEW                     0x00028EA0
+#define R_028EA4_CB_COLOR11_INFO                     0x00028EA4
+#define R_028EA8_CB_COLOR11_ATTRIB                   0x00028EA8
+#define R_028EAC_CB_COLOR11_DIM                      0x00028EAC
+#define R_030000_RESOURCE0_WORD0                     0x00030000
+#define R_030004_RESOURCE0_WORD1                     0x00030004
+#define R_030008_RESOURCE0_WORD2                     0x00030008
+#define R_03000C_RESOURCE0_WORD3                     0x0003000C
+#define R_030010_RESOURCE0_WORD4                     0x00030010
+#define R_030014_RESOURCE0_WORD5                     0x00030014
+#define R_030018_RESOURCE0_WORD6                     0x00030018
+#define R_03001C_RESOURCE0_WORD7                     0x0003001C
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CB8_DEST_BASE_ENA(x)                (((x) & 0x1) << 15)
+#define   G_0085F0_CB8_DEST_BASE_ENA(x)                (((x) >> 15) & 0x1)
+
+#define   S_0085F0_CB9_DEST_BASE_ENA(x)                (((x) & 0x1) << 16)
+#define   G_0085F0_CB9_DEST_BASE_ENA(x)                (((x) >> 16) & 0x1)
+
+#define   S_0085F0_CB10_DEST_BASE_ENA(x)               (((x) & 0x1) << 17)
+#define   G_0085F0_CB10_DEST_BASE_ENA(x)               (((x) >> 17) & 0x1)
+
+#define   S_0085F0_CB11_DEST_BASE_ENA(x)               (((x) & 0x1) << 18)
+#define   G_0085F0_CB11_DEST_BASE_ENA(x)               (((x) >> 18) & 0x1)
+
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+#define R_008970_VGT_NUM_INDICES                     0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                    0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC                  0x03CFF4
+
+#define R_03A200_SQ_LOOP_CONST_0                     0x3A200
 #endif
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index bce2707e77..15ee001106 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -26,8 +26,11 @@
 #ifndef R600_H
 #define R600_H
 
+#include <assert.h>
 #include <stdint.h>
 #include <stdio.h>
+#include <util/u_double_list.h>
+#include <pipe/p_compiler.h>
 
 #define RADEON_CTX_MAX_PM4	(64 * 1024 / 4)
 
@@ -90,63 +93,48 @@ enum radeon_family {
 	CHIP_LAST,
 };
 
-enum radeon_family r600_get_family(struct radeon *rw);
+enum chip_class {
+	R600,
+	R700,
+	EVERGREEN,
+};
 
-/*
- * radeon object functions
- */
-#if 0
-struct radeon_bo {
-	unsigned			refcount;
-	unsigned			handle;
-	unsigned			size;
-	unsigned			alignment;
-	unsigned			map_count;
-	void				*data;
+struct r600_tiling_info {
+	unsigned num_channels;
+	unsigned num_banks;
+	unsigned group_bytes;
 };
-struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
-			unsigned size, unsigned alignment, void *ptr);
-int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
-void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
-struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
-struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
-int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
-#endif
-/* lowlevel WS bo */
-struct radeon_ws_bo;
-struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
+
+enum radeon_family r600_get_family(struct radeon *rw);
+enum chip_class r600_get_family_class(struct radeon *radeon);
+struct r600_tiling_info *r600_get_tiling_info(struct radeon *radeon);
+
+/* r600_bo.c */
+struct r600_bo;
+struct r600_bo *r600_bo(struct radeon *radeon,
 				  unsigned size, unsigned alignment, unsigned usage);
-struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
+struct r600_bo *r600_bo_handle(struct radeon *radeon,
 					 unsigned handle);
-void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
-void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
-void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
-			    struct radeon_ws_bo *src);
-int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *bo);
+void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage, void *ctx);
+void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
+void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
+			    struct r600_bo *src);
+static INLINE unsigned r600_bo_offset(struct r600_bo *bo)
+{
+	return 0;
+}
+
 
 /* R600/R700 STATES */
 #define R600_GROUP_MAX			16
 #define R600_BLOCK_MAX_BO		32
 #define R600_BLOCK_MAX_REG		128
 
-enum r600_group_id {
-	R600_GROUP_CONFIG = 0,
-	R600_GROUP_CONTEXT,
-	R600_GROUP_ALU_CONST,
-	R600_GROUP_RESOURCE,
-	R600_GROUP_SAMPLER,
-	R600_GROUP_CTL_CONST,
-	R600_GROUP_LOOP_CONST,
-	R600_GROUP_BOOL_CONST,
-	R600_NGROUPS
-};
-
 struct r600_pipe_reg {
-	unsigned			group_id;
 	u32				offset;
 	u32				mask;
 	u32				value;
-	struct radeon_ws_bo		*bo;
+	struct r600_bo		*bo;
 };
 
 struct r600_pipe_state {
@@ -156,11 +144,9 @@ struct r600_pipe_state {
 };
 
 static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
-					unsigned group_id, u32 offset,
-					u32 value, u32 mask,
-					struct radeon_ws_bo *bo)
+					u32 offset, u32 value, u32 mask,
+					struct r600_bo *bo)
 {
-	state->regs[state->nregs].group_id = group_id;
 	state->regs[state->nregs].offset = offset;
 	state->regs[state->nregs].value = value;
 	state->regs[state->nregs].mask = mask;
@@ -173,30 +159,35 @@ static inline void r600_pipe_state_add_reg(struct r600_pipe_state *state,
 #define R600_BLOCK_STATUS_DIRTY		(1 << 1)
 
 struct r600_block_reloc {
-	struct radeon_ws_bo	*bo;
-	unsigned		nreloc;
-	unsigned		bo_pm4_index[R600_BLOCK_MAX_BO];
+	struct r600_bo		*bo;
+	unsigned		flush_flags;
+	unsigned		flush_mask;
+	unsigned		bo_pm4_index;
 };
 
-struct r600_group_block {
+struct r600_block {
+	struct list_head	list;
 	unsigned		status;
 	unsigned		start_offset;
 	unsigned		pm4_ndwords;
+	unsigned		pm4_flush_ndwords;
 	unsigned		nbo;
 	unsigned		nreg;
+	u32			*reg;
 	u32			pm4[R600_BLOCK_MAX_REG];
 	unsigned		pm4_bo_index[R600_BLOCK_MAX_REG];
 	struct r600_block_reloc	reloc[R600_BLOCK_MAX_BO];
 };
 
-struct r600_group {
+struct r600_range {
 	unsigned		start_offset;
 	unsigned		end_offset;
-	unsigned		nblocks;
-	struct r600_group_block	*blocks;
-	unsigned		*offset_block_id;
+	struct r600_block	**blocks;
 };
 
+/*
+ * relocation
+ */
 #pragma pack(1)
 struct r600_reloc {
 	uint32_t	handle;
@@ -206,10 +197,38 @@ struct r600_reloc {
 };
 #pragma pack()
 
+/*
+ * query
+ */
+struct r600_query {
+	u64					result;
+	/* The kind of query. Currently only OQ is supported. */
+	unsigned				type;
+	/* How many results have been written, in dwords. It's incremented
+	 * after end_query and flush. */
+	unsigned				num_results;
+	/* if we've flushed the query */
+	unsigned				state;
+	/* The buffer where query results are stored. */
+	struct r600_bo			*buffer;
+	unsigned				buffer_size;
+	/* linked list of queries */
+	struct list_head			list;
+};
+
+#define R600_QUERY_STATE_STARTED	(1 << 0)
+#define R600_QUERY_STATE_ENDED		(1 << 1)
+#define R600_QUERY_STATE_SUSPENDED	(1 << 2)
+
+
 struct r600_context {
 	struct radeon		*radeon;
-	unsigned		ngroups;
-	struct r600_group	groups[R600_GROUP_MAX];
+	unsigned		hash_size;
+	unsigned		hash_shift;
+	struct r600_range	range[256];
+	unsigned		nblocks;
+	struct r600_block	**blocks;
+	struct list_head	dirty;
 	unsigned		pm4_ndwords;
 	unsigned		pm4_cdwords;
 	unsigned		pm4_dirty_cdwords;
@@ -217,8 +236,14 @@ struct r600_context {
 	unsigned		nreloc;
 	unsigned		creloc;
 	struct r600_reloc	*reloc;
-	struct radeon_ws_bo	**bo;
+	struct radeon_bo	**bo;
 	u32			*pm4;
+	struct list_head	query_list;
+	unsigned		num_query_running;
+	unsigned		fence;
+	struct list_head	fenced_bo;
+	unsigned		*cfence;
+	struct r600_bo		*fence_bo;
 };
 
 struct r600_draw {
@@ -227,7 +252,7 @@ struct r600_draw {
 	u32			vgt_index_type;
 	u32			vgt_draw_initiator;
 	u32			indices_bo_offset;
-	struct radeon_ws_bo	*indices;
+	struct r600_bo		*indices;
 };
 
 int r600_context_init(struct r600_context *ctx, struct radeon *radeon);
@@ -241,4 +266,24 @@ void r600_context_flush(struct r600_context *ctx);
 void r600_context_dump_bof(struct r600_context *ctx, const char *file);
 void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
 
+struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
+void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
+boolean r600_context_query_result(struct r600_context *ctx,
+				struct r600_query *query,
+				boolean wait, void *vresult);
+void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
+void r600_query_end(struct r600_context *ctx, struct r600_query *query);
+void r600_context_queries_suspend(struct r600_context *ctx);
+void r600_context_queries_resume(struct r600_context *ctx);
+
+int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
+void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw);
+void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+
+void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid);
+void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id);
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 0d17f75da7..d13da0ef63 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -20,14 +20,13 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_context.h"
+#include <stdio.h>
+#include <errno.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
 #include "r600_sq.h"
 #include "r600_opcodes.h"
 #include "r600_asm.h"
-#include <stdio.h>
-#include <errno.h>
 
 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
 {
@@ -420,7 +419,6 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 	/* cf can contains only alu or only vtx or only tex */
 	if (bc->cf_last == NULL || bc->cf_last->inst != (type << 3) ||
 		bc->force_add_cf) {
-		/* at most 128 slots, one add alu can add 4 slots + 4 constant worst case */
 		r = r600_bc_add_cf(bc);
 		if (r) {
 			free(nalu);
@@ -434,7 +432,9 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 	} else {
 		LIST_ADDTAIL(&nalu->bs_list, &bc->cf_last->curr_bs_head->bs_list);
 	}
-	if (alu->last && (bc->cf_last->ndw >> 1) >= 124) {
+	/* at most 128 slots, one add alu can add 4 slots + 4 constants(2 slots)
+	 * worst case */
+	if (alu->last && (bc->cf_last->ndw >> 1) >= 120) {
 		bc->force_add_cf = 1;
 	}
 	/* number of gpr == the last gpr used in any alu */
@@ -465,8 +465,7 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 	bc->cf_last->ndw += 2;
 	bc->ndw += 2;
 
-	if (bc->use_mem_constant)
-		bc->cf_last->kcache0_mode = 2;
+	bc->cf_last->kcache0_mode = 2;
 
 	/* process cur ALU instructions for bank swizzle */
 	if (alu->last) {
@@ -531,7 +530,8 @@ int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
 	/* cf can contains only alu or only vtx or only tex */
 	if (bc->cf_last == NULL ||
 		(bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX &&
-		 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC)) {
+		 bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC) ||
+	         bc->force_add_cf) {
 		r = r600_bc_add_cf(bc);
 		if (r) {
 			free(nvtx);
@@ -543,6 +543,8 @@ int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
 	/* each fetch use 4 dwords */
 	bc->cf_last->ndw += 4;
 	bc->ndw += 4;
+	if ((bc->ndw / 4) > 7)
+		bc->force_add_cf = 1;
 	return 0;
 }
 
@@ -557,7 +559,8 @@ int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
 
 	/* cf can contains only alu or only vtx or only tex */
 	if (bc->cf_last == NULL ||
-		bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
+		bc->cf_last->inst != V_SQ_CF_WORD1_SQ_CF_INST_TEX ||
+	        bc->force_add_cf) {
 		r = r600_bc_add_cf(bc);
 		if (r) {
 			free(ntex);
@@ -569,6 +572,8 @@ int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
 	/* each texture fetch use 4 dwords */
 	bc->cf_last->ndw += 4;
 	bc->ndw += 4;
+	if ((bc->ndw / 4) > 7)
+		bc->force_add_cf = 1;
 	return 0;
 }
 
@@ -595,7 +600,11 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
 				S_SQ_VTX_WORD1_DST_SEL_Y(vtx->dst_sel_y) |
 				S_SQ_VTX_WORD1_DST_SEL_Z(vtx->dst_sel_z) |
 				S_SQ_VTX_WORD1_DST_SEL_W(vtx->dst_sel_w) |
-				S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) |
+				S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx->use_const_fields) |
+				S_SQ_VTX_WORD1_DATA_FORMAT(vtx->data_format) |
+				S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx->num_format_all) |
+				S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx->format_comp_all) |
+				S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx->srf_mode_all) |
 				S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
 	bc->bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
 	bc->bytecode[id++] = 0;
@@ -696,6 +705,7 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 
 		bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
 					S_SQ_CF_ALU_WORD1_BARRIER(1) |
+					S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == 0 ? cf->r6xx_uses_waterfall : 0) |
 					S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
 		break;
 	case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 62a46cb0e1..bebc7c15b0 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -58,7 +58,7 @@ struct r600_bc_alu {
 	unsigned			bank_swizzle;
 	unsigned			bank_swizzle_force;
 	u32				value[4];
-	int hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
+	int				hw_gpr[NUM_OF_CYCLES][NUM_OF_COMPONENTS];
 };
 
 struct r600_bc_tex {
@@ -101,6 +101,11 @@ struct r600_bc_vtx {
 	unsigned			dst_sel_y;
 	unsigned			dst_sel_z;
 	unsigned			dst_sel_w;
+	unsigned			use_const_fields;
+	unsigned			data_format;
+	unsigned			num_format_all;
+	unsigned			format_comp_all;
+	unsigned			srf_mode_all;
 };
 
 struct r600_bc_output {
@@ -127,6 +132,7 @@ struct r600_bc_cf {
 	unsigned			pop_count;
 	unsigned			cf_addr; /* control flow addr */
 	unsigned			kcache0_mode;
+	unsigned			r6xx_uses_waterfall;
 	struct list_head		alu;
 	struct list_head		tex;
 	struct list_head		vtx;
@@ -159,7 +165,6 @@ struct r600_cf_callstack {
 struct r600_bc {
 	enum radeon_family		family;
 	int				chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
-	unsigned			use_mem_constant; 
 	struct list_head		cf;
 	struct r600_bc_cf		*cf_last;
 	unsigned			ndw;
@@ -175,6 +180,10 @@ struct r600_bc {
 	struct r600_cf_callstack	callstack[SQ_MAX_CALL_DEPTH];
 };
 
+/* eg_asm.c */
+int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
+
+/* r600_asm.c */
 int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu);
 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value);
@@ -185,4 +194,7 @@ int r600_bc_build(struct r600_bc *bc);
 int r600_bc_add_cfinst(struct r600_bc *bc, int inst);
 int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type);
 
+/* r700_asm.c */
+int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id);
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 54fbc50bbc..cae05aab28 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Marek Olšák <maraeo@gmail.com>
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -19,69 +19,118 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Marek Olšák
  */
-#include <errno.h>
-#include <pipe/p_screen.h>
+#include <util/u_surface.h>
 #include <util/u_blitter.h>
-#include <util/u_inlines.h>
-#include <util/u_memory.h>
-#include "util/u_surface.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600d.h"
+#include <util/u_format.h>
+#include "r600_pipe.h"
 
-static void r600_blitter_save_states(struct pipe_context *ctx)
+enum r600_blitter_op /* bitmask */
 {
-	struct r600_context *rctx = r600_context(ctx);
+    R600_CLEAR         = 1,
+    R600_CLEAR_SURFACE = 2,
+    R600_COPY          = 4
+};
+
+static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	r600_context_queries_suspend(&rctx->ctx);
 
-	util_blitter_save_blend(rctx->blitter, rctx->blend);
-	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
-	if (rctx->stencil_ref) {
-		util_blitter_save_stencil_ref(rctx->blitter,
-					&rctx->stencil_ref->state.stencil_ref);
+	util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
+	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
+	if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
+		util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
 	}
-	util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
+	util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
 	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
 	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
 	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
-	if (rctx->viewport) {
-		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
+	if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
+		util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
 	}
-	if (rctx->clip) {
-		util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
+	if (rctx->states[R600_PIPE_STATE_CLIP]) {
+		util_blitter_save_clip(rctx->blitter, &rctx->clip);
 	}
-	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
-					rctx->vertex_buffer);
+	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
 
-	/* remove ptr so they don't get deleted */
-	rctx->blend = NULL;
-	rctx->clip = NULL;
-	rctx->vs_shader = NULL;
-	rctx->ps_shader = NULL;
-	rctx->rasterizer = NULL;
-	rctx->dsa = NULL;
 	rctx->vertex_elements = NULL;
 
-	/* suspend queries */
-	r600_queries_suspend(ctx);
+	if (op & (R600_CLEAR_SURFACE | R600_COPY))
+		util_blitter_save_framebuffer(rctx->blitter, &rctx->framebuffer);
+
+	if (op & R600_COPY) {
+		util_blitter_save_fragment_sampler_states(
+			rctx->blitter, rctx->ps_samplers.n_samplers,
+			(void**)rctx->ps_samplers.samplers);
+
+		util_blitter_save_fragment_sampler_views(
+			rctx->blitter, rctx->ps_samplers.n_views,
+			(struct pipe_sampler_view**)rctx->ps_samplers.views);
+	}
+
+}
+
+static void r600_blitter_end(struct pipe_context *ctx)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	r600_context_queries_resume(&rctx->ctx);
+}
+
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct pipe_framebuffer_state fb = *rctx->pframebuffer;
+	struct pipe_surface *zsurf, *cbsurf;
+	int level = 0;
+	float depth = 1.0f;
+
+	r600_context_queries_suspend(&rctx->ctx);
+	for (int i = 0; i < fb.nr_cbufs; i++) {
+		fb.cbufs[i] = NULL;
+		pipe_surface_reference(&fb.cbufs[i], rctx->pframebuffer->cbufs[i]);
+	}
+	fb.zsbuf = NULL;
+	pipe_surface_reference(&fb.zsbuf, rctx->pframebuffer->zsbuf);
+
+	zsurf = ctx->screen->get_tex_surface(ctx->screen, &texture->resource.base.b, 0, level, 0,
+					     PIPE_BIND_DEPTH_STENCIL);
+
+	cbsurf = ctx->screen->get_tex_surface(ctx->screen,
+			(struct pipe_resource*)texture->flushed_depth_texture,
+			0, level, 0, PIPE_BIND_RENDER_TARGET);
+
+	r600_blitter_begin(ctx, R600_CLEAR);
+	util_blitter_save_framebuffer(rctx->blitter, &fb);
+	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+		depth = 0.0f;
+
+	util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth);
+
+	pipe_surface_reference(&zsurf, NULL);
+	pipe_surface_reference(&cbsurf, NULL);
+	for (int i = 0; i < fb.nr_cbufs; i++) {
+		pipe_surface_reference(&fb.cbufs[i], NULL);
+	}
+	pipe_surface_reference(&fb.zsbuf, NULL);
+	r600_context_queries_resume(&rctx->ctx);
+
+	return 0;
 }
 
 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 			const float *rgba, double depth, unsigned stencil)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
 
-	r600_blitter_save_states(ctx);
+	r600_blitter_begin(ctx, R600_CLEAR);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
 				fb->nr_cbufs, buffers, rgba, depth,
 				stencil);
-	/* resume queries */
-	r600_queries_resume(ctx);
+	r600_blitter_end(ctx);
 }
 
 static void r600_clear_render_target(struct pipe_context *ctx,
@@ -90,16 +139,12 @@ static void r600_clear_render_target(struct pipe_context *ctx,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
+	r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
-	/* resume queries */
-	r600_queries_resume(ctx);
+	r600_blitter_end(ctx);
 }
 
 static void r600_clear_depth_stencil(struct pipe_context *ctx,
@@ -110,19 +155,35 @@ static void r600_clear_depth_stencil(struct pipe_context *ctx,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
+	r600_blitter_begin(ctx, R600_CLEAR_SURFACE);
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
-	/* resume queries */
-	r600_queries_resume(ctx);
+	r600_blitter_end(ctx);
 }
 
 
+
+/* Copy a block of pixels from one surface to another using HW. */
+static void r600_hw_copy_region(struct pipe_context *ctx,
+                                struct pipe_resource *dst,
+                                struct pipe_subresource subdst,
+                                unsigned dstx, unsigned dsty, unsigned dstz,
+                                struct pipe_resource *src,
+                                struct pipe_subresource subsrc,
+                                unsigned srcx, unsigned srcy, unsigned srcz,
+                                unsigned width, unsigned height)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	r600_blitter_begin(ctx, R600_COPY);
+	util_blitter_copy_region(rctx->blitter, dst, subdst, dstx, dsty, dstz,
+				 src, subsrc, srcx, srcy, srcz, width, height,
+				 TRUE);
+	r600_blitter_end(ctx);
+}
+
 static void r600_resource_copy_region(struct pipe_context *ctx,
 				      struct pipe_resource *dst,
 				      struct pipe_subresource subdst,
@@ -132,463 +193,22 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
-				  src, subsrc, srcx, srcy, srcz, width, height);
+	boolean is_depth;
+	/* there is something wrong with depth resource copies at the moment so avoid them for now */
+	is_depth = util_format_get_component_bits(src->format, UTIL_FORMAT_COLORSPACE_ZS, 0) != 0;
+	if (is_depth)
+		util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+					  src, subsrc, srcx, srcy, srcz, width, height);
+	else
+		r600_hw_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+				    src, subsrc, srcx, srcy, srcz, width, height);
+
 }
 
-void r600_init_blit_functions(struct r600_context *rctx)
+void r600_init_blit_functions(struct r600_pipe_context *rctx)
 {
 	rctx->context.clear = r600_clear;
 	rctx->context.clear_render_target = r600_clear_render_target;
 	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
 	rctx->context.resource_copy_region = r600_resource_copy_region;
 }
-
-
-struct r600_blit_states {
-	struct radeon_state	rasterizer;
-	struct radeon_state	dsa;
-	struct radeon_state	blend;
-	struct radeon_state	cb_cntl;
-	struct radeon_state	vgt;
-	struct radeon_state	draw;
-	struct radeon_state	vs_constant0;
-	struct radeon_state	vs_constant1;
-	struct radeon_state	vs_constant2;
-	struct radeon_state	vs_constant3;
-	struct radeon_state	ps_shader;
-	struct radeon_state	vs_shader;
-	struct radeon_state	vs_resource0;
-	struct radeon_state	vs_resource1;
-};
-
-static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
-{
-	struct radeon_state *rstate;
-	struct radeon_ws_bo *bo;
-	void *data;
-	u32 vbo[] = {
-		0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000,
-		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
-		0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000,
-		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
-		0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000,
-		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
-		0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000,
-		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000
-	};
-
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return -ENOMEM;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return -ENOMEM;
-	}
-	memcpy(data, vbo, 128);
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	rstate = &bstates->vs_resource0;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
-	rstate->bo[0] = bo;
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-		return -ENOMEM;
-	}
-
-	rstate = &bstates->vs_resource1;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	struct radeon_ws_bo *bo;
-	void *data;
-	u32 shader_bc_r600[] = {
-		0x00000004, 0x81000400,
-		0x00000008, 0xA01C0000,
-		0xC001A03C, 0x94000688,
-		0xC0024000, 0x94200688,
-		0x7C000000, 0x002D1001,
-		0x00080000, 0x00000000,
-		0x7C000100, 0x002D1002,
-		0x00080000, 0x00000000,
-		0x00000001, 0x00601910,
-		0x00000401, 0x20601910,
-		0x00000801, 0x40601910,
-		0x80000C01, 0x60601910,
-		0x00000002, 0x00801910,
-		0x00000402, 0x20801910,
-		0x00000802, 0x40801910,
-		0x80000C02, 0x60801910
-	};
-	u32 shader_bc_r700[] = {
-		0x00000004, 0x81000400,
-		0x00000008, 0xA01C0000,
-		0xC001A03C, 0x94000688,
-		0xC0024000, 0x94200688,
-		0x7C000000, 0x002D1001,
-		0x00080000, 0x00000000,
-		0x7C000100, 0x002D1002,
-		0x00080000, 0x00000000,
-		0x00000001, 0x00600C90,
-		0x00000401, 0x20600C90,
-		0x00000801, 0x40600C90,
-		0x80000C01, 0x60600C90,
-		0x00000002, 0x00800C90,
-		0x00000402, 0x20800C90,
-		0x00000802, 0x40800C90,
-		0x80000C02, 0x60800C90
-	};
-
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	switch (rscreen->chip_class) {
-	case R600:
-		memcpy(data, shader_bc_r600, 128);
-		break;
-	case R700:
-		memcpy(data, shader_bc_r700, 128);
-		break;
-	default:
-		R600_ERR("unsupported chip family\n");
-		radeon_ws_bo_unmap(rscreen->rw, bo);
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100;
-	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504;
-	rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005;
-
-	rstate->bo[0] = bo;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], bo);
-	rstate->nbo = 2;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	struct radeon_ws_bo *bo;
-	void *data;
-	u32 shader_bc_r600[] = {
-		0x00000002, 0xA00C0000,
-		0xC0008000, 0x94200688,
-		0x00000000, 0x00201910,
-		0x00000400, 0x20201910,
-		0x00000800, 0x40201910,
-		0x80000C00, 0x60201910
-	};
-	u32 shader_bc_r700[] = {
-		0x00000002, 0xA00C0000,
-		0xC0008000, 0x94200688,
-		0x00000000, 0x00200C90,
-		0x00000400, 0x20200C90,
-		0x00000800, 0x40200C90,
-		0x80000C00, 0x60200C90
-	};
-
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	switch (rscreen->chip_class) {
-	case R600:
-		memcpy(data, shader_bc_r600, 48);
-		break;
-	case R700:
-		memcpy(data, shader_bc_r700, 48);
-		break;
-	default:
-		R600_ERR("unsupported chip family\n");
-		radeon_ws_bo_unmap(rscreen->rw, bo);
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00;
-	rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001;
-	rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
-	rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002;
-
-	rstate->bo[0] = bo;
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_vgt(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VGT, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_draw(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DRAW, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
-	rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_vs_constant(struct r600_screen *rscreen, struct radeon_state *rstate,
-					unsigned id, float c0, float c1, float c2, float c3)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_rasterizer(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
-	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
-	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_dsa(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
-	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_blend(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_cb_cntl(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080;
-	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rstate);
-}
-
-static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-
-	r600_blit_state_ps_shader(rscreen, &bstates->ps_shader);
-	r600_blit_state_vs_shader(rscreen, &bstates->vs_shader);
-	r600_blit_state_vgt(rscreen, &bstates->vgt);
-	r600_blit_state_draw(rscreen, &bstates->draw);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant0, 0, 1.0, 0.0, 0.0, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant1, 1, 0.0, 1.0, 0.0, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant2, 2, 0.0, 0.0, -0.00199900055, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant3, 3, 0.0, 0.0, -0.99900049, 1.0);
-	r600_blit_state_rasterizer(rscreen, &bstates->rasterizer);
-	r600_blit_state_dsa(rscreen, &bstates->dsa);
-	r600_blit_state_blend(rscreen, &bstates->blend);
-	r600_blit_state_cb_cntl(rscreen, &bstates->cb_cntl);
-	r600_blit_state_vs_resources(rscreen, bstates);
-	return 0;
-}
-
-static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
-{
-	radeon_state_fini(&bstates->ps_shader);
-	radeon_state_fini(&bstates->vs_shader);
-	radeon_state_fini(&bstates->vs_resource0);
-	radeon_state_fini(&bstates->vs_resource1);
-}
-
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_draw draw;
-	struct r600_blit_states bstates;
-	int r;
-
-	r = r600_texture_scissor(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_cb(ctx, rtexture, 0, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_db(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_viewport(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-
-	r = r600_blit_states_init(ctx, &bstates);
-	if (r) {
-		return r;
-	}
-	bstates.dsa.states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
-	bstates.cb_cntl.states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
-	/* force rebuild */
-	bstates.dsa.cpm4 = bstates.cb_cntl.cpm4 = 0;
-	if (radeon_state_pm4(&bstates.dsa)) {
-		goto out;
-	}
-	if (radeon_state_pm4(&bstates.cb_cntl)) {
-		goto out;
-	}
-
-	r = radeon_draw_init(&draw, rscreen->rw);
-	if (r) {
-		R600_ERR("failed creating draw for uncompressing textures\n");
-		goto out;
-	}
-
-	radeon_draw_bind(&draw, &bstates.vs_shader);
-	radeon_draw_bind(&draw, &bstates.ps_shader);
-	radeon_draw_bind(&draw, &bstates.rasterizer);
-	radeon_draw_bind(&draw, &bstates.dsa);
-	radeon_draw_bind(&draw, &bstates.blend);
-	radeon_draw_bind(&draw, &bstates.cb_cntl);
-	radeon_draw_bind(&draw, &rctx->config);
-	radeon_draw_bind(&draw, &bstates.vgt);
-	radeon_draw_bind(&draw, &bstates.draw);
-	radeon_draw_bind(&draw, &bstates.vs_resource0);
-	radeon_draw_bind(&draw, &bstates.vs_resource1);
-	radeon_draw_bind(&draw, &bstates.vs_constant0);
-	radeon_draw_bind(&draw, &bstates.vs_constant1);
-	radeon_draw_bind(&draw, &bstates.vs_constant2);
-	radeon_draw_bind(&draw, &bstates.vs_constant3);
-	radeon_draw_bind(&draw, &rtexture->viewport[level]);
-	radeon_draw_bind(&draw, &rtexture->scissor[level]);
-	radeon_draw_bind(&draw, &rtexture->cb[0][level]);
-	radeon_draw_bind(&draw, &rtexture->db[level]);
-
-	/* suspend queries */
-	r600_queries_suspend(ctx);
-
-	/* schedule draw*/
-	r = radeon_ctx_set_draw(rctx->ctx, &draw);
-	if (r == -EBUSY) {
-		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, &draw);
-	}
-	if (r) {
-		goto out;
-	}
-
-	/* resume queries */
-	r600_queries_resume(ctx);
-
-out:
-	r600_blit_states_destroy(ctx, &bstates);
-	return r;
-}
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index dc3fc812e1..2bfa4e22fe 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -31,9 +31,10 @@
 #include <util/u_memory.h>
 #include <util/u_upload_mgr.h>
 #include "state_tracker/drm_driver.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
+#include <xf86drm.h>
+#include "radeon_drm.h"
+#include "r600.h"
+#include "r600_pipe.h"
 
 extern struct u_resource_vtbl r600_buffer_vtbl;
 
@@ -42,23 +43,23 @@ u32 r600_domain_from_usage(unsigned usage)
 	u32 domain = RADEON_GEM_DOMAIN_GTT;
 
 	if (usage & PIPE_BIND_RENDER_TARGET) {
-	    domain |= RADEON_GEM_DOMAIN_VRAM;
+		domain |= RADEON_GEM_DOMAIN_VRAM;
 	}
 	if (usage & PIPE_BIND_DEPTH_STENCIL) {
-	    domain |= RADEON_GEM_DOMAIN_VRAM;
+		domain |= RADEON_GEM_DOMAIN_VRAM;
 	}
 	if (usage & PIPE_BIND_SAMPLER_VIEW) {
-	    domain |= RADEON_GEM_DOMAIN_VRAM;
+		domain |= RADEON_GEM_DOMAIN_VRAM;
 	}
 	/* also need BIND_BLIT_SOURCE/DESTINATION ? */
 	if (usage & PIPE_BIND_VERTEX_BUFFER) {
-	    domain |= RADEON_GEM_DOMAIN_GTT;
+		domain |= RADEON_GEM_DOMAIN_GTT;
 	}
 	if (usage & PIPE_BIND_INDEX_BUFFER) {
-	    domain |= RADEON_GEM_DOMAIN_GTT;
+		domain |= RADEON_GEM_DOMAIN_GTT;
 	}
 	if (usage & PIPE_BIND_CONSTANT_BUFFER) {
-	    domain |= RADEON_GEM_DOMAIN_VRAM;
+		domain |= RADEON_GEM_DOMAIN_VRAM;
 	}
 
 	return domain;
@@ -67,9 +68,8 @@ u32 r600_domain_from_usage(unsigned usage)
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 					 const struct pipe_resource *templ)
 {
-	struct r600_screen *rscreen = r600_screen(screen);
 	struct r600_resource_buffer *rbuffer;
-	struct radeon_ws_bo *bo;
+	struct r600_bo *bo;
 	/* XXX We probably want a different alignment for buffers and textures. */
 	unsigned alignment = 4096;
 
@@ -86,7 +86,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 	rbuffer->r.base.vtbl = &r600_buffer_vtbl;
 	rbuffer->r.size = rbuffer->r.base.b.width0;
 	rbuffer->r.domain = r600_domain_from_usage(rbuffer->r.base.b.bind);
-	bo = radeon_ws_bo(rscreen->rw, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
+	bo = r600_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
 	if (bo == NULL) {
 		FREE(rbuffer);
 		return NULL;
@@ -127,10 +127,9 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 				struct pipe_resource *buf)
 {
 	struct r600_resource_buffer *rbuffer = r600_buffer(buf);
-	struct r600_screen *rscreen = r600_screen(screen);
 
 	if (rbuffer->r.bo) {
-		radeon_ws_bo_reference(rscreen->rw, &rbuffer->r.bo, NULL);
+		r600_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
 	}
 	FREE(rbuffer);
 }
@@ -138,9 +137,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				      struct pipe_transfer *transfer)
 {
-	struct r600_context *rctx = r600_context(pipe);
 	struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
-	struct r600_screen *rscreen = r600_screen(pipe->screen);
 	int write = 0;
 	uint8_t *data;
 	int i;
@@ -156,9 +153,9 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				flush = TRUE;
 			
 			if (flush) {
-				radeon_ws_bo_reference(rscreen->rw, &rbuffer->r.bo, NULL);
+				r600_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
 				rbuffer->num_ranges = 0;
-				rbuffer->r.bo = radeon_ws_bo(rscreen->rw, 
+				rbuffer->r.bo = r600_bo((struct radeon*)pipe->winsys,
 							     rbuffer->r.base.b.width0, 0,
 							     rbuffer->r.base.b.bind);
 				break;
@@ -171,7 +168,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 	if (transfer->usage & PIPE_TRANSFER_WRITE) {
 		write = 1;
 	}
-	data = radeon_ws_bo_map(rscreen->rw, rbuffer->r.bo, transfer->usage, rctx);
+	data = r600_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
 	if (!data)
 		return NULL;
 
@@ -182,10 +179,9 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 					struct pipe_transfer *transfer)
 {
 	struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
-	struct r600_screen *rscreen = r600_screen(pipe->screen);
 
 	if (rbuffer->r.bo)
-		radeon_ws_bo_unmap(rscreen->rw, rbuffer->r.bo);
+		r600_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
 }
 
 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
@@ -229,16 +225,16 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 {
 	struct radeon *rw = (struct radeon*)screen->winsys;
 	struct r600_resource *rbuffer;
-	struct radeon_ws_bo *bo = NULL;
+	struct r600_bo *bo = NULL;
 
-	bo = radeon_ws_bo_handle(rw, whandle->handle);
+	bo = r600_bo_handle(rw, whandle->handle);
 	if (bo == NULL) {
 		return NULL;
 	}
 
 	rbuffer = CALLOC_STRUCT(r600_resource);
 	if (rbuffer == NULL) {
-		radeon_ws_bo_reference(rw, &bo, NULL);
+		r600_bo_reference(rw, &bo, NULL);
 		return NULL;
 	}
 
@@ -263,8 +259,7 @@ struct u_resource_vtbl r600_buffer_vtbl =
 	u_default_transfer_inline_write		/* transfer_inline_write */
 };
 
-int r600_upload_index_buffer(struct r600_context *rctx,
-			     struct r600_draw *draw)
+int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw)
 {
 	struct pipe_resource *upload_buffer = NULL;
 	unsigned index_offset = draw->index_buffer_offset;
@@ -281,14 +276,17 @@ int r600_upload_index_buffer(struct r600_context *rctx,
 			goto done;
 		}
 		draw->index_buffer_offset = index_offset;
-		draw->index_buffer = upload_buffer;
+
+		/* Transfer ownership. */
+		pipe_resource_reference(&draw->index_buffer, upload_buffer);
+		pipe_resource_reference(&upload_buffer, NULL);
 	}
 
 done:
 	return ret;
 }
 
-int r600_upload_user_buffers(struct r600_context *rctx)
+int r600_upload_user_buffers(struct r600_pipe_context *rctx)
 {
 	enum pipe_error ret = PIPE_OK;
 	int i, nr;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
deleted file mode 100644
index 776dc24569..0000000000
--- a/src/gallium/drivers/r600/r600_context.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <stdio.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include <util/u_upload_mgr.h>
-#include <util/u_blitter.h>
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-
-static void r600_destroy_context(struct pipe_context *context)
-{
-	struct r600_context *rctx = r600_context(context);
-
-	rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
-	rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
-	rctx->scissor = r600_context_state_decref(rctx->scissor);
-	rctx->clip = r600_context_state_decref(rctx->clip);
-	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
-	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
-	rctx->depth = r600_context_state_decref(rctx->depth);
-	rctx->stencil = r600_context_state_decref(rctx->stencil);
-	rctx->alpha = r600_context_state_decref(rctx->alpha);
-	rctx->dsa = r600_context_state_decref(rctx->dsa);
-	rctx->blend = r600_context_state_decref(rctx->blend);
-	rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
-	rctx->viewport = r600_context_state_decref(rctx->viewport);
-	rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
-
-	free(rctx->ps_constant);
-	free(rctx->vs_constant);
-	free(rctx->vs_resource);
-
-	u_upload_destroy(rctx->upload_vb);
-	u_upload_destroy(rctx->upload_ib);
-
-	radeon_ctx_fini(rctx->ctx);
-	FREE(rctx);
-}
-
-void r600_flush(struct pipe_context *ctx, unsigned flags,
-			struct pipe_fence_handle **fence)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = NULL;
-
-	/* flush upload buffers */
-	u_upload_flush(rctx->upload_vb);
-	u_upload_flush(rctx->upload_ib);
-
-	/* suspend queries */
-	r600_queries_suspend(ctx);
-
-	radeon_ctx_submit(rctx->ctx);
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		rquery->flushed = true;
-	}
-
-	radeon_ctx_clear(rctx->ctx);
-	/* resume queries */
-	r600_queries_resume(ctx);
-}
-
-void r600_flush_ctx(void *data)
-{
-        struct r600_context *rctx = data;
-
-        rctx->context.flush(&rctx->context, 0, NULL);
-}
-
-struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
-{
-	struct r600_context *rctx = CALLOC_STRUCT(r600_context);
-	struct r600_screen* rscreen = r600_screen(screen);
-
-	if (rctx == NULL)
-		return NULL;
-	rctx->context.winsys = rscreen->screen.winsys;
-	rctx->context.screen = screen;
-	rctx->context.priv = priv;
-	rctx->context.destroy = r600_destroy_context;
-	rctx->context.draw_vbo = r600_draw_vbo;
-	rctx->context.flush = r600_flush;
-
-	/* Easy accessing of screen/winsys. */
-	rctx->screen = rscreen;
-	rctx->rw = rscreen->rw;
-
-	if (rscreen->chip_class == EVERGREEN)
-		rctx->vtbl = &eg_hw_state_vtbl;
-	else
-		rctx->vtbl = &r600_hw_state_vtbl;
-
-	r600_init_blit_functions(rctx);
-	r600_init_query_functions(rctx);
-	r600_init_state_functions(rctx);
-	r600_init_context_resource_functions(rctx);
-
-	rctx->blitter = util_blitter_create(&rctx->context);
-	if (rctx->blitter == NULL) {
-		FREE(rctx);
-		return NULL;
-	}
-
-	rctx->vtbl->init_config(rctx);
-
-	rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
-					  PIPE_BIND_INDEX_BUFFER);
-	if (rctx->upload_ib == NULL) {
-		goto out_free;
-	}
-
-	rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
-					  PIPE_BIND_VERTEX_BUFFER);
-	if (rctx->upload_vb == NULL) {
-		goto out_free;
-	}
-
-	rctx->vs_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
-	if (!rctx->vs_constant) {
-		goto out_free;
-	}
-
-	rctx->ps_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
-	if (!rctx->ps_constant) {
-		goto out_free;
-	}
-
-	rctx->vs_resource = (struct radeon_state *)calloc(R600_MAX_RESOURCE, sizeof(struct radeon_state));
-	if (!rctx->vs_resource) {
-		goto out_free;
-	}						   
-
-	rctx->ctx = radeon_ctx_init(rscreen->rw);
-	radeon_draw_init(&rctx->draw, rscreen->rw);
-	return &rctx->context;
- out_free:
-	FREE(rctx);
-	return NULL;
-}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
deleted file mode 100644
index 3107f189c7..0000000000
--- a/src/gallium/drivers/r600/r600_context.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_CONTEXT_H
-#define R600_CONTEXT_H
-
-#include <stdio.h>
-#include <pipe/p_state.h>
-#include <pipe/p_context.h>
-#include <tgsi/tgsi_scan.h>
-#include <tgsi/tgsi_parse.h>
-#include <tgsi/tgsi_util.h>
-#include <util/u_blitter.h>
-#include <util/u_double_list.h>
-#include "radeon.h"
-#include "r600_shader.h"
-
-struct u_upload_mgr;
-
-#define R600_QUERY_STATE_STARTED	(1 << 0)
-#define R600_QUERY_STATE_ENDED		(1 << 1)
-#define R600_QUERY_STATE_SUSPENDED	(1 << 2)
-
-struct r600_query {
-	u64					result;
-	/* The kind of query. Currently only OQ is supported. */
-	unsigned				type;
-	/* How many results have been written, in dwords. It's incremented
-	 * after end_query and flush. */
-	unsigned				num_results;
-	/* if we've flushed the query */
-	boolean					flushed;
-	unsigned				state;
-	/* The buffer where query results are stored. */
-	struct radeon_ws_bo			*buffer;
-	unsigned				buffer_size;
-	/* linked list of queries */
-	struct list_head			list;
-	struct radeon_state			rstate;
-};
-
-/* XXX move this to a more appropriate place */
-union pipe_states {
-	struct pipe_rasterizer_state		rasterizer;
-	struct pipe_poly_stipple		poly_stipple;
-	struct pipe_scissor_state		scissor;
-	struct pipe_clip_state			clip;
-	struct pipe_shader_state		shader;
-	struct pipe_depth_state			depth;
-	struct pipe_stencil_state		stencil;
-	struct pipe_alpha_state			alpha;
-	struct pipe_depth_stencil_alpha_state	dsa;
-	struct pipe_blend_state			blend;
-	struct pipe_blend_color			blend_color;
-	struct pipe_stencil_ref			stencil_ref;
-	struct pipe_framebuffer_state		framebuffer;
-	struct pipe_sampler_state		sampler;
-	struct pipe_sampler_view		sampler_view;
-	struct pipe_viewport_state		viewport;
-};
-
-enum pipe_state_type {
-	pipe_rasterizer_type = 1,
-	pipe_poly_stipple_type,
-	pipe_scissor_type,
-	pipe_clip_type,
-	pipe_shader_type,
-	pipe_depth_type,
-	pipe_stencil_type,
-	pipe_alpha_type,
-	pipe_dsa_type,
-	pipe_blend_type,
-	pipe_stencil_ref_type,
-	pipe_framebuffer_type,
-	pipe_sampler_type,
-	pipe_sampler_view_type,
-	pipe_viewport_type,
-	pipe_type_count
-};
-
-#define R600_MAX_RSTATE		16
-
-struct r600_context_state {
-	union pipe_states		state;
-	unsigned			refcount;
-	unsigned			type;
-	struct radeon_state		rstate[R600_MAX_RSTATE];
-	struct r600_shader		shader;
-	struct radeon_ws_bo		*bo;
-	unsigned			nrstate;
-};
-
-struct r600_vertex_element
-{
-	unsigned			refcount;
-	unsigned			count;
-	struct pipe_vertex_element	elements[32];
-};
-
-struct r600_draw {
-	struct pipe_context	*ctx;
-	struct radeon_state	draw;
-	struct radeon_state	vgt;
-	unsigned		mode;
-	unsigned		start;
-	unsigned		count;
-	unsigned		index_size;
-	struct pipe_resource	*index_buffer;
-	unsigned		index_buffer_offset;
-	unsigned		min_index, max_index;
-};
-
-struct r600_context_hw_states {
-	struct radeon_state	rasterizer;
-	struct radeon_state	scissor;
-	struct radeon_state	dsa;
-	struct radeon_state	cb_cntl;
-
-	struct radeon_state	db_flush;
-	struct radeon_state	cb_flush;
-};
-
-#define R600_MAX_CONSTANT 256 /* magic */
-#define R600_MAX_RESOURCE 160 /* magic */
-
-struct r600_shader_sampler_states {
-	unsigned			nsampler;
-	unsigned			nview;
-	unsigned			nborder;
-	struct radeon_state		*sampler[PIPE_MAX_ATTRIBS];
-	struct radeon_state		*view[PIPE_MAX_ATTRIBS];
-	struct radeon_state		*border[PIPE_MAX_ATTRIBS];
-};
-
-struct r600_context;
-struct r600_screen;
-struct r600_resource;
-struct r600_resource_texture;
-
-struct r600_context_hw_state_vtbl {
-	void (*blend)(struct r600_context *rctx,
-		      struct radeon_state *rstate,
-		      const struct pipe_blend_state *state);
-	void (*ucp)(struct r600_context *rctx, struct radeon_state *rstate,
-		    const struct pipe_clip_state *state);
-	void (*cb)(struct r600_context *rctx, struct radeon_state *rstate,
-		   const struct pipe_framebuffer_state *state, int cb);
-	void (*db)(struct r600_context *rctx, struct radeon_state *rstate,
-		   const struct pipe_framebuffer_state *state);
-	void (*rasterizer)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*scissor)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*viewport)(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
-	void (*dsa)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*sampler_border)(struct r600_context *rctx, struct radeon_state *rstate,
-			       const struct pipe_sampler_state *state, unsigned id);
-	void (*sampler)(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_state *state, unsigned id);
-	void (*resource)(struct pipe_context *ctx, struct radeon_state *rstate,
-			 const struct pipe_sampler_view *view, unsigned id);
-	void (*cb_cntl)(struct r600_context *rctx, struct radeon_state *rstate);
-	int (*vs_resource)(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
-			   uint32_t stride, uint32_t format);
-	int (*vgt_init)(struct r600_draw *draw,
-			int vgt_draw_initiator);
-	int (*vgt_prim)(struct r600_draw *draw,
-			uint32_t prim, uint32_t vgt_dma_index_type);
-
-	int (*ps_shader)(struct r600_context *rctx, struct r600_context_state *rshader,
-			 struct radeon_state *state);
-	int (*vs_shader)(struct r600_context *rctx, struct r600_context_state *rpshader,
-			 struct radeon_state *state);
-	void (*init_config)(struct r600_context *rctx);
-
-
-	void (*texture_state_viewport)(struct r600_screen *rscreen,
-				       struct r600_resource_texture *rtexture,
-				       unsigned level);
-	void (*texture_state_cb)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned cb,
-				 unsigned level);
-	void (*texture_state_db)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned level);
-	void (*texture_state_scissor)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned level);
-};
-extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
-extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;
-
-struct r600_context {
-	struct pipe_context		context;
-	struct r600_screen		*screen;
-	struct radeon			*rw;
-	struct radeon_ctx		*ctx;
-	struct blitter_context		*blitter;
-	struct radeon_draw		draw;
-	struct r600_context_hw_state_vtbl *vtbl;
-	struct radeon_state		config;
-	boolean use_mem_constant;
-	/* FIXME get rid of those vs_resource,vs/ps_constant */
-	struct radeon_state		*vs_resource;
-	unsigned			vs_nresource;
-	struct radeon_state		*vs_constant;
-	struct radeon_state		*ps_constant;
-	/* hw states */
-	struct r600_context_hw_states	hw_states;
-	/* pipe states */
-	unsigned			flat_shade;
-
-	unsigned			nvertex_buffer;
-	struct r600_context_state	*rasterizer;
-	struct r600_context_state	*poly_stipple;
-	struct r600_context_state	*scissor;
-	struct r600_context_state	*clip;
-	struct r600_context_state	*ps_shader;
-	struct r600_context_state	*vs_shader;
-	struct r600_context_state	*depth;
-	struct r600_context_state	*stencil;
-	struct r600_context_state	*alpha;
-	struct r600_context_state	*dsa;
-	struct r600_context_state	*blend;
-	struct r600_context_state	*stencil_ref;
-	struct r600_context_state	*viewport;
-	struct r600_context_state	*framebuffer;
-	struct r600_shader_sampler_states vs_sampler;
-	struct r600_shader_sampler_states ps_sampler;
-	/* can add gs later */
-	struct r600_vertex_element	*vertex_elements;
-	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
-	struct pipe_index_buffer	index_buffer;
-	struct pipe_blend_color		blend_color;
-	struct list_head		query_list;
-
-	/* upload managers */
-	struct u_upload_mgr *upload_vb;
-	struct u_upload_mgr *upload_ib;
-	bool any_user_vbs;
-
-};
-
-/* Convenience cast wrapper. */
-static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
-{
-    return (struct r600_context*)pipe;
-}
-
-static INLINE struct r600_query* r600_query(struct pipe_query* q)
-{
-    return (struct r600_query*)q;
-}
-
-struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
-struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
-void r600_flush(struct pipe_context *ctx, unsigned flags,
-			struct pipe_fence_handle **fence);
-
-int r600_context_hw_states(struct pipe_context *ctx);
-
-void r600_draw_vbo(struct pipe_context *ctx,
-                   const struct pipe_draw_info *info);
-
-void r600_init_blit_functions(struct r600_context *rctx);
-void r600_init_state_functions(struct r600_context *rctx);
-void r600_init_query_functions(struct r600_context* rctx);
-struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv);
-
-extern int r600_pipe_shader_create(struct pipe_context *ctx,
-			struct r600_context_state *rstate,
-			const struct tgsi_token *tokens);
-extern int r600_pipe_shader_update(struct pipe_context *ctx,
-				struct r600_context_state *rstate);
-
-#define R600_ERR(fmt, args...) \
-	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
-
-uint32_t r600_translate_texformat(enum pipe_format format,
-				  const unsigned char *swizzle_view, 
-				  uint32_t *word4_p, uint32_t *yuv_format_p);
-
-/* query */
-extern void r600_queries_resume(struct pipe_context *ctx);
-extern void r600_queries_suspend(struct pipe_context *ctx);
-
-int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
-
-void r600_set_constant_buffer_file(struct pipe_context *ctx,
-				   uint shader, uint index,
-				   struct pipe_resource *buffer);
-void r600_set_constant_buffer_mem(struct pipe_context *ctx,
-				  uint shader, uint index,
-				  struct pipe_resource *buffer);
-void eg_set_constant_buffer(struct pipe_context *ctx,
-			    uint shader, uint index,
-			    struct pipe_resource *buffer);
-
-int r600_upload_index_buffer(struct r600_context *rctx,
-                             struct r600_draw *draw);
-int r600_upload_user_buffers(struct r600_context *rctx);
-
-#endif
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
deleted file mode 100644
index 5480ca002d..0000000000
--- a/src/gallium/drivers/r600/r600_draw.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <stdio.h>
-#include <errno.h>
-#include <pipe/p_screen.h>
-#include <util/u_format.h>
-#include <util/u_math.h>
-#include <util/u_inlines.h>
-#include <util/u_memory.h>
-#include "radeon.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "r600_state_inlines.h"
-
-static int r600_draw_common(struct r600_draw *draw)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	/* FIXME vs_resource */
-	struct radeon_state *vs_resource;
-	struct r600_resource *rbuffer;
-	unsigned i, j, offset, format, prim;
-	u32 vgt_dma_index_type, vgt_draw_initiator;
-	struct pipe_vertex_buffer *vertex_buffer;
-	int r;
-
-	r = r600_context_hw_states(draw->ctx);
-	if (r)
-		return r;
-	switch (draw->index_size) {
-	case 2:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_DMA);
-		vgt_dma_index_type = 0;
-		break;
-	case 4:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_DMA);
-		vgt_dma_index_type = 1;
-		break;
-	case 0:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_AUTO_INDEX);
-		vgt_dma_index_type = 0;
-		break;
-	default:
-		fprintf(stderr, "%s %d unsupported index size %d\n", __func__, __LINE__, draw->index_size);
-		return -EINVAL;
-	}
-	r = r600_conv_pipe_prim(draw->mode, &prim);
-	if (r)
-		return r;
-
-	/* rebuild vertex shader if input format changed */
-	r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
-	if (r)
-		return r;
-	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
-	if (r)
-		return r;
-	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate[0]);
-	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate[0]);
-
-	for (i = 0 ; i < rctx->vs_nresource; i++) {
-		radeon_state_fini(&rctx->vs_resource[i]);
-	}
-	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
-		vs_resource = &rctx->vs_resource[i];
-		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		vertex_buffer = &rctx->vertex_buffer[j];
-		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
-		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
-		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		
-		rctx->vtbl->vs_resource(rctx, i, rbuffer, offset, vertex_buffer->stride, format);
-		radeon_draw_bind(&rctx->draw, vs_resource);
-	}
-	rctx->vs_nresource = rctx->vertex_elements->count;
-	/* FIXME start need to change winsys */
-	rctx->vtbl->vgt_init(draw, vgt_draw_initiator);
-	radeon_draw_bind(&rctx->draw, &draw->draw);
-
-	rctx->vtbl->vgt_prim(draw, prim, vgt_dma_index_type);
-	radeon_draw_bind(&rctx->draw, &draw->vgt);
-
-	r = radeon_ctx_set_draw(rctx->ctx, &rctx->draw);
-	if (r == -EBUSY) {
-		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, &rctx->draw);
-	}
-
-	radeon_state_fini(&draw->draw);
-
-	return r;
-}
-
-void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_draw draw;
-	int r;
-
-	assert(info->index_bias == 0);
-
-	memset(&draw, 0, sizeof(draw));
-
-	if (rctx->any_user_vbs) {
-		r600_upload_user_buffers(rctx);
-		rctx->any_user_vbs = false;
-	}
-
-	draw.ctx = ctx;
-	draw.mode = info->mode;
-	draw.start = info->start;
-	draw.count = info->count;
-	if (info->indexed && rctx->index_buffer.buffer) {
-		draw.min_index = info->min_index;
-		draw.max_index = info->max_index;
-		draw.index_size = rctx->index_buffer.index_size;
-		draw.index_buffer = rctx->index_buffer.buffer;
-		draw.index_buffer_offset = rctx->index_buffer.offset;
-
-		assert(rctx->index_buffer.offset %
-				rctx->index_buffer.index_size == 0);
-		r600_upload_index_buffer(rctx, &draw);
-	}
-	else {
-		draw.index_size = 0;
-		draw.index_buffer = NULL;
-		draw.min_index = 0;
-		draw.max_index = 0xffffff;
-		draw.index_buffer_offset = 0;
-	}
-	r = r600_draw_common(&draw);
-	if (r)
-	  fprintf(stderr,"draw common failed %d\n", r);
-}
diff --git a/src/gallium/drivers/r600/r600_formats.h b/src/gallium/drivers/r600/r600_formats.h
new file mode 100644
index 0000000000..0c91a21238
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_formats.h
@@ -0,0 +1,56 @@
+#ifndef R600_FORMATS_H
+#define R600_FORMATS_H
+
+/* list of formats from R700 ISA document - apply across GPUs in different registers */
+#define     FMT_INVALID                     0x00000000
+#define     FMT_8                           0x00000001
+#define     FMT_4_4                         0x00000002
+#define     FMT_3_3_2                       0x00000003
+#define     FMT_16                          0x00000005
+#define     FMT_16_FLOAT                    0x00000006
+#define     FMT_8_8                         0x00000007
+#define     FMT_5_6_5                       0x00000008
+#define     FMT_6_5_5                       0x00000009
+#define     FMT_1_5_5_5                     0x0000000A
+#define     FMT_4_4_4_4                     0x0000000B
+#define     FMT_5_5_5_1                     0x0000000C
+#define     FMT_32                          0x0000000D
+#define     FMT_32_FLOAT                    0x0000000E
+#define     FMT_16_16                       0x0000000F
+#define     FMT_16_16_FLOAT                 0x00000010
+#define     FMT_8_24                        0x00000011
+#define     FMT_8_24_FLOAT                  0x00000012
+#define     FMT_24_8                        0x00000013
+#define     FMT_24_8_FLOAT                  0x00000014
+#define     FMT_10_11_11                    0x00000015
+#define     FMT_10_11_11_FLOAT              0x00000016
+#define     FMT_11_11_10                    0x00000017
+#define     FMT_11_11_10_FLOAT              0x00000018
+#define     FMT_2_10_10_10                  0x00000019
+#define     FMT_8_8_8_8                     0x0000001A
+#define     FMT_10_10_10_2                  0x0000001B
+#define     FMT_X24_8_32_FLOAT              0x0000001C
+#define     FMT_32_32                       0x0000001D
+#define     FMT_32_32_FLOAT                 0x0000001E
+#define     FMT_16_16_16_16                 0x0000001F
+#define     FMT_16_16_16_16_FLOAT           0x00000020
+#define     FMT_32_32_32_32                 0x00000022
+#define     FMT_32_32_32_32_FLOAT           0x00000023
+#define     FMT_1                           0x00000025
+#define     FMT_GB_GR                       0x00000027
+#define     FMT_BG_RG                       0x00000028
+#define     FMT_32_AS_8                     0x00000029
+#define     FMT_32_AS_8_8                   0x0000002a
+#define     FMT_5_9_9_9_SHAREDEXP           0x0000002b
+#define     FMT_8_8_8                       0x0000002c
+#define     FMT_16_16_16                    0x0000002d
+#define     FMT_16_16_16_FLOAT              0x0000002e
+#define     FMT_32_32_32                    0x0000002f
+#define     FMT_32_32_32_FLOAT              0x00000030
+#define     FMT_BC1                         0x00000031
+#define     FMT_BC2                         0x00000032
+#define     FMT_BC3                         0x00000033
+#define     FMT_BC4                         0x00000034
+#define     FMT_BC5                         0x00000035
+
+#endif
diff --git a/src/gallium/drivers/r600/r600_helper.c b/src/gallium/drivers/r600/r600_helper.c
index 5e0e0aab57..7e13109306 100644
--- a/src/gallium/drivers/r600/r600_helper.c
+++ b/src/gallium/drivers/r600/r600_helper.c
@@ -26,8 +26,7 @@
 #include <stdio.h>
 #include <errno.h>
 #include <util/u_inlines.h>
-#include "r600_screen.h"
-#include "r600_context.h"
+#include "r600_pipe.h"
 #include "r600d.h"
 
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
deleted file mode 100644
index bca78ee8de..0000000000
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ /dev/null
@@ -1,1287 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *           2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Dave Airlie
- */
-
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include <util/u_blitter.h>
-#include "util/u_pack_color.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "r600_state_inlines.h"
-#include "r600d.h"
-
-static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	int i;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
-	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
-	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
-	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
-	rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
-	rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND4_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND5_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
-
-	for (i = 0; i < 8; i++) {
-		unsigned eqRGB = state->rt[i].rgb_func;
-		unsigned srcRGB = state->rt[i].rgb_src_factor;
-		unsigned dstRGB = state->rt[i].rgb_dst_factor;
-		
-		unsigned eqA = state->rt[i].alpha_func;
-		unsigned srcA = state->rt[i].alpha_src_factor;
-		unsigned dstA = state->rt[i].alpha_dst_factor;
-		uint32_t bc = 0;
-
-		if (!state->rt[i].blend_enable)
-			continue;
-
-		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
-		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
-		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
-
-		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
-			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
-			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
-			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
-			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
-		}
-
-		rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
-		if (i == 0)
-			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
-	}
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_clip_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
-
-	for (int i = 0; i < state->nr; i++) {
-		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
-		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
-		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
-		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
-	}
-	radeon_state_pm4(rstate);
-}
-
-static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_framebuffer_state *state, int cb)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 1;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
-	     const struct pipe_framebuffer_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	if (state->zsbuf == NULL)
-		return;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	radeon_state_pm4(rstate);
-}
-
-static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
-	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-	const struct pipe_clip_state *clip = NULL;
-	struct r600_screen *rscreen = rctx->screen;
-	float offset_units = 0, offset_scale = 0;
-	char depth = 0;
-	unsigned offset_db_fmt_cntl = 0;
-	unsigned tmp;
-	unsigned prov_vtx = 1;
-
-	if (rctx->clip)
-		clip = &rctx->clip->state.clip;
-	if (fb->zsbuf) {
-		offset_units = state->offset_units;
-		offset_scale = state->offset_scale * 12.0f;
-		switch (fb->zsbuf->texture->format) {
-		case PIPE_FORMAT_Z24X8_UNORM:
-		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-			depth = -24;
-			offset_units *= 2.0f;
-			break;
-		case PIPE_FORMAT_Z32_FLOAT:
-			depth = -23;
-			offset_units *= 1.0f;
-			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
-			break;
-		case PIPE_FORMAT_Z16_UNORM:
-			depth = -16;
-			offset_units *= 4.0f;
-			break;
-		default:
-			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return;
-		}
-	}
-	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
-
-	if (state->flatshade_first)
-		prov_vtx = 0;
-
-	rctx->flat_shade = state->flatshade;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
-	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
-	if (state->sprite_coord_enable) {
-		rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
-				S_0286D4_PNT_SPRITE_ENA(1) |
-				S_0286D4_PNT_SPRITE_OVRD_X(2) |
-				S_0286D4_PNT_SPRITE_OVRD_Y(3) |
-				S_0286D4_PNT_SPRITE_OVRD_Z(0) |
-				S_0286D4_PNT_SPRITE_OVRD_W(1);
-		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
-			rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
-					S_0286D4_PNT_SPRITE_TOP_1(1);
-		}
-	}
-	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
-	if (clip) {
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
-	}
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
-		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
-		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
-		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-		S_028814_FACE(!state->front_ccw) |
-		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
-	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
-			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
-			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
-	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
-	/* point size 12.4 fixed point */
-	tmp = (unsigned)(state->point_size * 8.0);
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
-	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
-	rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	radeon_state_pm4(rstate);
-}
-
-static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
-	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-	struct r600_screen *rscreen = rctx->screen;
-	enum radeon_family family;
-	unsigned minx, maxx, miny, maxy;
-	u32 tl, br;
-
-	family = radeon_get_family(rctx->rw);
-
-	if (state == NULL) {
-		minx = 0;
-		miny = 0;
-		maxx = fb->cbufs[0]->width;
-		maxy = fb->cbufs[0]->height;
-	} else {
-		minx = state->minx;
-		miny = state->miny;
-		maxx = state->maxx;
-		maxy = state->maxy;
-	}
-	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
-	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
-
-	if (family >= CHIP_RV770)
-		rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
-	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
-	struct r600_screen *rscreen = rctx->screen;
-	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
-	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
-	struct r600_shader *rshader;
-	struct r600_query *rquery = NULL;
-	boolean query_running;
-	int i;
-
-	if (rctx->ps_shader == NULL) {
-		return;
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
-
-	db_shader_control = 0;
-	db_shader_control |= S_02880C_DUAL_EXPORT_ENABLE(1);
-	db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
-
-	rshader = &rctx->ps_shader->shader;
-	if (rshader->uses_kill)
-		db_shader_control |= S_02880C_KILL_ENABLE(1);
-	for (i = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-			db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
-	}
-	stencil_ref_mask = 0;
-	stencil_ref_mask_bf = 0;
-	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
-		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
-		S_028800_ZFUNC(state->depth.func);
-	/* set stencil enable */
-
-	if (state->stencil[0].enabled) {
-		db_depth_control |= S_028800_STENCIL_ENABLE(1);
-		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
-		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
-		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
-		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-
-		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
-			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
-		stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
-		if (state->stencil[1].enabled) {
-			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
-			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
-			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
-			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
-			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
-			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
-				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
-			stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
-		}
-	}
-
-	alpha_test_control = 0;
-	alpha_ref = 0;
-	if (state->alpha.enabled) {
-		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
-		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
-		alpha_ref = fui(state->alpha.ref_value);
-	}
-
-	db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
-		S_028D0C_DEPTH_COMPRESS_DISABLE(1);
-	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
-
-	query_running = false;
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			query_running = true;
-		}
-	}
-
-	if (query_running) {
-		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
-		if (rscreen->chip_class == R700)
-			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
-	}
-
-	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
-	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
-	rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
-	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
-	rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
-	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
-	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
-	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
-	rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
-	rstate->states[R600_DSA__DB_RENDER_CONTROL] = db_render_control;
-	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
-	  
-	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
-	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
-	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	radeon_state_pm4(rstate);
-}
-
-
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
-{
-	return value * (1 << frac_bits);
-}
-
-static void r600_sampler_border(struct r600_context *rctx, struct radeon_state *rstate,
-				const struct pipe_sampler_state *state, unsigned id)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	union util_color uc;
-
-	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER_BORDER, id, R600_SHADER_PS);
-	if (uc.ui) {
-		rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED] = fui(state->border_color[0]);
-		rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN] = fui(state->border_color[1]);
-		rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE] = fui(state->border_color[2]);
-		rstate->states[R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA] = fui(state->border_color[3]);
-	}
-	radeon_state_pm4(rstate);
-}
-
-static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_state *state, unsigned id)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	union util_color uc;
-
-	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
-	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
-			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
-			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
-			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
-			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
-			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
-			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
-	                S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
-	                S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
-	/* FIXME LOD it depends on texture base level ... */
-	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
-			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
-			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
-			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
-	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	radeon_state_pm4(rstate);
-
-}
-
-
-static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
-			const struct pipe_sampler_view *view, unsigned id)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	const struct util_format_description *desc;
-	struct r600_resource_texture *tmp;
-	struct r600_resource *rbuffer;
-	unsigned format;
-	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
-	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
-	int r;
-
-	rstate->cpm4 = 0;
-	swizzle[0] = view->swizzle_r;
-	swizzle[1] = view->swizzle_g;
-	swizzle[2] = view->swizzle_b;
-	swizzle[3] = view->swizzle_a;
-	format = r600_translate_texformat(view->texture->format,
-					  swizzle,
-					  &word4, &yuv_format);
-	if (format == ~0) {
-		return;
-	}
-	desc = util_format_description(view->texture->format);
-	if (desc == NULL) {
-		R600_ERR("unknow format %d\n", view->texture->format);
-		return;
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
-	tmp = (struct r600_resource_texture*)view->texture;
-	rbuffer = &tmp->resource;
-	if (tmp->depth) {
-		r = r600_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
-	}
-	rstate->nbo = 2;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
-
-	pitch = (tmp->pitch[0] / tmp->bpt);
-	pitch = (pitch + 0x7) & ~0x7;
-
-	/* FIXME properly handle first level != 0 */
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
-			S_038000_DIM(r600_tex_dim(view->texture->target)) |
-			S_038000_TILE_MODE(array_mode) |
-			S_038000_TILE_TYPE(tile_type) |
-			S_038000_PITCH((pitch / 8) - 1) |
-			S_038000_TEX_WIDTH(view->texture->width0 - 1);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
-			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
-			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
-			S_038004_DATA_FORMAT(format);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
-		        word4 | 
-			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
-			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
-			S_038010_REQUEST_SIZE(1) |
-			S_038010_BASE_LEVEL(view->first_level);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
-			S_038014_LAST_LEVEL(view->last_level) |
-			S_038014_BASE_ARRAY(0) |
-			S_038014_LAST_ARRAY(0);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
-			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	radeon_state_pm4(rstate);
-}
-
-static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
-	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	uint32_t color_control, target_mask, shader_mask;
-	int i;
-
-	target_mask = 0;
-	shader_mask = 0;
-	color_control = S_028808_PER_MRT_BLEND(1);
-
-	for (i = 0; i < nr_cbufs; i++) {
-		shader_mask |= 0xf << (i * 4);
-	}
-
-	if (pbs->logicop_enable) {
-		color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
-	} else {
-		color_control |= (0xcc << 16);
-	}
-
-	if (pbs->independent_blend_enable) {
-		for (i = 0; i < nr_cbufs; i++) {
-			if (pbs->rt[i].blend_enable) {
-				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
-			}
-			target_mask |= (pbs->rt[i].colormask << (4 * i));
-		}
-	} else {
-		for (i = 0; i < nr_cbufs; i++) {
-			if (pbs->rt[0].blend_enable) {
-				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
-			}
-			target_mask |= (pbs->rt[0].colormask << (4 * i));
-		}
-	}
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
-	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
-	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
-	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_init_config(struct r600_context *rctx)
-{
-	int ps_prio;
-	int vs_prio;
-	int gs_prio;
-	int es_prio;
-	int num_ps_gprs;
-	int num_vs_gprs;
-	int num_gs_gprs;
-	int num_es_gprs;
-	int num_temp_gprs;
-	int num_ps_threads;
-	int num_vs_threads;
-	int num_gs_threads;
-	int num_es_threads;
-	int num_ps_stack_entries;
-	int num_vs_stack_entries;
-	int num_gs_stack_entries;
-	int num_es_stack_entries;
-	enum radeon_family family;
-
-	family = radeon_get_family(rctx->rw);
-	ps_prio = 0;
-	vs_prio = 1;
-	gs_prio = 2;
-	es_prio = 3;
-	switch (family) {
-	case CHIP_R600:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV630:
-	case CHIP_RV635:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 144;
-		num_vs_threads = 40;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV610:
-	case CHIP_RV620:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	default:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV670:
-		num_ps_gprs = 144;
-		num_vs_gprs = 40;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV770:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 188;
-		num_vs_threads = 60;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 256;
-		num_vs_stack_entries = 256;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV730:
-	case CHIP_RV740:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 188;
-		num_vs_threads = 60;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV710:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 144;
-		num_vs_threads = 48;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	}
-	radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
-
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
-	switch (family) {
-	case CHIP_RV610:
-	case CHIP_RV620:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	case CHIP_RV710:
-		break;
-	default:
-		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
-		break;
-	}
-
-	if (!rctx->screen->use_mem_constant)
-		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
-
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
-
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
-
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
-
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
-
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
-
-	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
-
-	if (family >= CHIP_RV770) {
-		rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-		rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-		rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-		rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-		rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
-		rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	} else {
-		rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
-		rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
-		rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
-		rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
-		rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-		rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
-	}
-	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(&rctx->config);
-}
-
-static int r600_vs_resource(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
-			    uint32_t stride, uint32_t format)
-{
-	struct radeon_state *vs_resource = &rctx->vs_resource[id];
-	struct r600_screen *rscreen = rctx->screen;
-
-	radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_VS);
-	radeon_ws_bo_reference(rscreen->rw, &vs_resource->bo[0], rbuffer->bo);
-	vs_resource->nbo = 1;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->size - offset - 1;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(stride) |
-		S_038008_DATA_FORMAT(format);
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-	vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
-	vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(vs_resource);
-}
-
-static int r600_draw_vgt_init(struct r600_draw *draw,
-			      int vgt_draw_initiator)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource *rbuffer = (struct r600_resource *)draw->index_buffer;
-	radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
-	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
-	draw->draw.states[R600_DRAW__VGT_DMA_BASE] = draw->index_buffer_offset;
-	if (rbuffer) {
-		radeon_ws_bo_reference(rscreen->rw, &draw->draw.bo[0], rbuffer->bo);
-		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.nbo = 1;
-	}
-	return radeon_state_pm4(&draw->draw);
-}
-
-static int r600_draw_vgt_prim(struct r600_draw *draw,
-			      uint32_t prim, uint32_t vgt_dma_index_type)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	struct r600_screen *rscreen = rctx->screen;
-	radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = draw->max_index;
-	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = draw->min_index;
-	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	return radeon_state_pm4(&draw->vgt);
-}
-
-static int r600_ps_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
-			  struct radeon_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	const struct pipe_rasterizer_state *rasterizer;
-	struct r600_shader *rshader = &rpshader->shader;
-	unsigned i, tmp, exports_ps, num_cout;
-	boolean have_pos = FALSE;
-
-	rasterizer = &rctx->rasterizer->state.rasterizer;
-
-	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	for (i = 0; i < rshader->ninput; i++) {
-		tmp = S_028644_SEMANTIC(i);
-		tmp |= S_028644_SEL_CENTROID(1);
-		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
-			have_pos = TRUE;
-		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
-			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
-		}
-		if (rasterizer->sprite_coord_enable & (1 << i)) {
-			tmp |= S_028644_PT_SPRITE_TEX(1);
-		}
-		state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
-	}
-
-	exports_ps = 0;
-	num_cout = 0;
-	for (i = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-			exports_ps |= 1;
-		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
-			exports_ps |= (1 << (num_cout+1));
-			num_cout++;
-		}
-	}
-	if (!exports_ps) {
-		/* always at least export 1 component per pixel */
-		exports_ps = 2;
-	}
-	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
-							S_0286CC_PERSP_GRADIENT_ENA(1);
-	if (have_pos) {
-		state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1) |
-		                                                       S_0286CC_BARYC_SAMPLE_CNTL(1);
-		state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1;
-	}
-	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
-	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
-		S_028868_STACK_SIZE(rshader->bc.nstack);
-	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
-	state->nbo = 1;
-	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(state);
-}
-
-static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *rpshader,
-			  struct radeon_state *state)
-{
-	struct r600_screen *rscreen = rctx->screen;	
-	struct r600_shader *rshader = &rpshader->shader;
-	unsigned i, tmp;
-
-	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	for (i = 0; i < 10; i++) {
-		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
-	}
-	/* so far never got proper semantic id from tgsi */
-	for (i = 0; i < 32; i++) {
-		tmp = i << ((i & 3) * 8);
-		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
-	}
-	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
-	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
-		S_028868_STACK_SIZE(rshader->bc.nstack);
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[0], rpshader->bo);
-	radeon_ws_bo_reference(rscreen->rw, &state->bo[1], rpshader->bo);
-	state->nbo = 2;
-	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	return radeon_state_pm4(state);
-}
-
-static void r600_texture_state_scissor(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->scissor[level];
-	enum radeon_family family;
-
-	family = radeon_get_family(rscreen->rw);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-
-	if (family >= CHIP_RV770)
-		rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct radeon_state *rstate;
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	rstate = &rtexture->cb[cb][level];
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
-	rbuffer = &rtexture->resource;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	ntype = 0;
-	desc = util_format_description(rbuffer->base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-	format = r600_translate_colorformat(rtexture->resource.base.b.format);
-	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
-		color_info = 0;
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
-		color_info = S_0280A0_SOURCE_FORMAT(1);
-	}
-	color_info |= S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->db[level];
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	rbuffer = &rtexture->resource;
-	rtexture->tilled = 1;
-	rtexture->array_mode = 2;
-	rtexture->tile_type = 1;
-	rtexture->depth = 1;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	format = r600_translate_dbformat(rbuffer->base.b.format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 1;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->viewport[level];
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
-	radeon_state_pm4(rstate);
-}
-
-struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
-	.blend = r600_blend,
-	.ucp = r600_ucp,
-	.cb = r600_cb,
-	.db = r600_db,
-	.rasterizer = r600_rasterizer,
-	.scissor = r600_scissor,
-	.viewport = r600_viewport,
-	.dsa = r600_dsa,
-	.sampler_border = r600_sampler_border,
-	.sampler = r600_sampler,
-	.resource = r600_resource,
-	.cb_cntl = r600_cb_cntl,
-	.vs_resource = r600_vs_resource,
-	.vgt_init = r600_draw_vgt_init,
-	.vgt_prim = r600_draw_vgt_prim,
-	.vs_shader = r600_vs_shader,
-	.ps_shader = r600_ps_shader,
-	.init_config = r600_init_config,
-	.texture_state_viewport = r600_texture_state_viewport,
-	.texture_state_db = r600_texture_state_db,
-	.texture_state_cb = r600_texture_state_cb,
-	.texture_state_scissor = r600_texture_state_scissor,
-};
-
-void r600_set_constant_buffer_file(struct pipe_context *ctx,
-				   uint shader, uint index,
-				   struct pipe_resource *buffer)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, type, shader_class;
-	struct radeon_state *rstate, *rstates;
-	struct pipe_transfer *transfer;
-	u32 *ptr;
-
-	type = R600_STATE_CONSTANT;
-
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		shader_class = R600_SHADER_VS;
-		rstates = rctx->vs_constant;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		shader_class = R600_SHADER_PS;
-		rstates = rctx->ps_constant;
-		break;
-	default:
-		R600_ERR("unsupported %d\n", shader);
-		return;
-	}
-	if (buffer && buffer->width0 > 0) {
-		nconstant = buffer->width0 / 16;
-		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
-		if (ptr == NULL)
-			return;
-		for (i = 0; i < nconstant; i++) {
-			rstate = &rstates[i];
-			radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
-			if (radeon_state_pm4(rstate))
-				return;
-			radeon_draw_bind(&rctx->draw, rstate);
-		}
-		pipe_buffer_unmap(ctx, buffer, transfer);
-	}
-}
-
-void r600_set_constant_buffer_mem(struct pipe_context *ctx,
-				  uint shader, uint index,
-				  struct pipe_resource *buffer)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, type, shader_class, size;
-	struct radeon_state *rstate, *rstates;
-	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
-
-	type = R600_STATE_CBUF;
-
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		shader_class = R600_SHADER_VS;
-		rstates = rctx->vs_constant;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		shader_class = R600_SHADER_PS;
-		rstates = rctx->ps_constant;
-		break;
-	default:
-		R600_ERR("unsupported %d\n", shader);
-		return;
-	}
-
-	rstate = &rstates[0];
-
-#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
-
-	nconstant = buffer->width0 / 16;
-	size = ALIGN_DIVUP(nconstant, 16);
-		
-	radeon_state_init(rstate, rscreen->rw, type, 0, shader_class);
-	rstate->states[R600_VS_CBUF__ALU_CONST_BUFFER_SIZE_VS_0] = size;
-	rstate->states[R600_VS_CBUF__ALU_CONST_CACHE_VS_0] = 0;
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	if (radeon_state_pm4(rstate))
-		return;
-	radeon_draw_bind(&rctx->draw, rstate);
-}
-
diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h
index 0cf9c1c401..4f9b39a7fd 100644
--- a/src/gallium/drivers/r600/r600_opcodes.h
+++ b/src/gallium/drivers/r600/r600_opcodes.h
@@ -233,12 +233,6 @@
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CEIL                      0x00000012
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE                     0x00000013
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR                     0x00000014
-/* same up to here */
-/*
-#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA                      0x00000015
-#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR                0x00000016
-#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT                  0x00000018
-*/
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT                  0x00000015
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHR_INT                  0x00000016
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LSHL_INT                  0x00000017
@@ -336,9 +330,11 @@
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_CLAMPED_64      0x00000098
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SQRT_64                   0x00000099
 /* TODO Fill in more ALU */
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR          0x000000B1
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4                      0x000000BE
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE                 0x000000BF
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE                      0x000000C0
+#define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT                  0x000000CC
 
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY                      0x000000D6
 #define     EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_ZW                      0x000000D7
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_pipe.c
index 1711fabfc7..dd8fa4fcd7 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -19,37 +19,221 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
  */
 #include <stdio.h>
-#include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_public.h"
+#include <errno.h>
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_blitter.h>
+#include <util/u_double_list.h>
+#include <util/u_transfer.h>
+#include <util/u_surface.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <util/u_upload_mgr.h>
+#include <pipebuffer/pb_buffer.h>
+#include "r600.h"
+#include "r600d.h"
 #include "r600_resource.h"
+#include "r600_shader.h"
+#include "r600_pipe.h"
 #include "r600_state_inlines.h"
 
+/*
+ * pipe_context
+ */
+static void r600_flush(struct pipe_context *ctx, unsigned flags,
+			struct pipe_fence_handle **fence)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+#if 0
+	static int dc = 0;
+	char dname[256];
+#endif
+
+	if (!rctx->ctx.pm4_cdwords)
+		return;
+
+	u_upload_flush(rctx->upload_vb);
+	u_upload_flush(rctx->upload_ib);
+
+#if 0
+	sprintf(dname, "gallium-%08d.bof", dc);
+	if (dc < 20) {
+		r600_context_dump_bof(&rctx->ctx, dname);
+		R600_ERR("dumped %s\n", dname);
+	}
+	dc++;
+#endif
+	r600_context_flush(&rctx->ctx);
+}
+
+static void r600_destroy_context(struct pipe_context *context)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
+
+	r600_context_fini(&rctx->ctx);
+	for (int i = 0; i < R600_PIPE_NSTATES; i++) {
+		free(rctx->states[i]);
+	}
+
+	u_upload_destroy(rctx->upload_vb);
+	u_upload_destroy(rctx->upload_ib);
+
+	FREE(rctx->ps_resource);
+	FREE(rctx->vs_resource);
+	FREE(rctx);
+}
+
+static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
+{
+	struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
+	struct r600_screen* rscreen = (struct r600_screen *)screen;
+	enum chip_class class;
+
+	if (rctx == NULL)
+		return NULL;
+	rctx->context.winsys = rscreen->screen.winsys;
+	rctx->context.screen = screen;
+	rctx->context.priv = priv;
+	rctx->context.destroy = r600_destroy_context;
+	rctx->context.flush = r600_flush;
+
+	/* Easy accessing of screen/winsys. */
+	rctx->screen = rscreen;
+	rctx->radeon = rscreen->radeon;
+	rctx->family = r600_get_family(rctx->radeon);
+
+	r600_init_blit_functions(rctx);
+	r600_init_query_functions(rctx);
+	r600_init_context_resource_functions(rctx);
+
+	switch (r600_get_family(rctx->radeon)) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		rctx->context.draw_vbo = r600_draw_vbo;
+		r600_init_state_functions(rctx);
+		if (r600_context_init(&rctx->ctx, rctx->radeon)) {
+			r600_destroy_context(&rctx->context);
+			return NULL;
+		}
+		r600_init_config(rctx);
+		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		rctx->context.draw_vbo = evergreen_draw;
+		evergreen_init_state_functions(rctx);
+		if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
+			r600_destroy_context(&rctx->context);
+			return NULL;
+		}
+		evergreen_init_config(rctx);
+		break;
+	default:
+		R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
+					  PIPE_BIND_INDEX_BUFFER);
+	if (rctx->upload_ib == NULL) {
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
+					  PIPE_BIND_VERTEX_BUFFER);
+	if (rctx->upload_vb == NULL) {
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	rctx->blitter = util_blitter_create(&rctx->context);
+	if (rctx->blitter == NULL) {
+		FREE(rctx);
+		return NULL;
+	}
+
+	rctx->vs_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
+	if (!rctx->vs_resource) {
+		FREE(rctx);
+		return NULL;
+	}
+
+	rctx->ps_resource = CALLOC(R600_RESOURCE_ARRAY_SIZE, sizeof(struct r600_pipe_state));
+	if (!rctx->ps_resource) {
+		FREE(rctx);
+		return NULL;
+	}
+
+	class = r600_get_family_class(rctx->radeon);
+	if (class == R600 || class == R700)
+		rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
+	else
+		rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
+
+	r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth;
+
+	return &rctx->context;
+}
+
+/*
+ * pipe_screen
+ */
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
 	return "X.Org";
 }
 
+static const char *r600_get_family_name(enum radeon_family family)
+{
+	switch(family) {
+	case CHIP_R600: return "R600";
+	case CHIP_RV610: return "RV610";
+	case CHIP_RV630: return "RV630";
+	case CHIP_RV670: return "RV670";
+	case CHIP_RV620: return "RV620";
+	case CHIP_RV635: return "RV635";
+	case CHIP_RS780: return "RS780";
+	case CHIP_RS880: return "RS880";
+	case CHIP_RV770: return "RV770";
+	case CHIP_RV730: return "RV730";
+	case CHIP_RV710: return "RV710";
+	case CHIP_RV740: return "RV740";
+	case CHIP_CEDAR: return "CEDAR";
+	case CHIP_REDWOOD: return "REDWOOD";
+	case CHIP_JUNIPER: return "JUNIPER";
+	case CHIP_CYPRESS: return "CYPRESS";
+	case CHIP_HEMLOCK: return "HEMLOCK";
+	default: return "unknown";
+	}
+}
+
 static const char* r600_get_name(struct pipe_screen* pscreen)
 {
-	struct r600_screen *screen = r600_screen(pscreen);
-	enum radeon_family family = radeon_get_family(screen->rw);
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	enum radeon_family family = r600_get_family(rscreen->radeon);
 
-	if (family >= CHIP_R600 && family < CHIP_RV770)
-		return "R600 (HD2XXX,HD3XXX)";
-	else if (family < CHIP_CEDAR)
-		return "R700 (HD4XXX)";
-	else
-		return "EVERGREEN";
+	return r600_get_family_name(family);
 }
 
 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
@@ -72,6 +256,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_INDEP_BLEND_ENABLE:
 	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
 	case PIPE_CAP_DEPTH_CLAMP:
+	case PIPE_CAP_SHADER_STENCIL_EXPORT:
 		return 1;
 
 	/* Unsupported features (boolean caps). */
@@ -87,7 +272,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 		return 14;
 	case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 		/* FIXME allow this once infrastructure is there */
-		return 0;
+		return 16;
 	case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
 	case PIPE_CAP_MAX_COMBINED_SAMPLERS:
 		return 16;
@@ -104,15 +289,35 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 		return 0;
+
 	default:
 		R600_ERR("r600: unknown param %d\n", param);
 		return 0;
 	}
 }
 
+static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+	switch (param) {
+	case PIPE_CAP_MAX_LINE_WIDTH:
+	case PIPE_CAP_MAX_LINE_WIDTH_AA:
+	case PIPE_CAP_MAX_POINT_WIDTH:
+	case PIPE_CAP_MAX_POINT_WIDTH_AA:
+		return 8192.0f;
+	case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+		return 16.0f;
+	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+		return 16.0f;
+	default:
+		R600_ERR("r600: unsupported paramf %d\n", param);
+		return 0.0f;
+	}
+}
+
 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 {
-	switch(shader) {
+	switch(shader)
+	{
 	case PIPE_SHADER_FRAGMENT:
 	case PIPE_SHADER_VERTEX:
 		break;
@@ -155,24 +360,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
 	}
 }
 
-static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
-{
-	switch (param) {
-	case PIPE_CAP_MAX_LINE_WIDTH:
-	case PIPE_CAP_MAX_LINE_WIDTH_AA:
-	case PIPE_CAP_MAX_POINT_WIDTH:
-	case PIPE_CAP_MAX_POINT_WIDTH_AA:
-		return 8192.0f;
-	case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
-		return 16.0f;
-	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
-		return 16.0f;
-	default:
-		R600_ERR("r600: unsupported paramf %d\n", param);
-		return 0.0f;
-	}
-}
-
 static boolean r600_is_format_supported(struct pipe_screen* screen,
 					enum pipe_format format,
 					enum pipe_texture_target target,
@@ -226,58 +413,25 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
 
 static void r600_destroy_screen(struct pipe_screen* pscreen)
 {
-	struct r600_screen* rscreen = r600_screen(pscreen);
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
 
 	if (rscreen == NULL)
 		return;
 	FREE(rscreen);
 }
 
-struct pipe_screen *r600_screen_create(struct radeon *rw)
+
+struct pipe_screen *r600_screen_create(struct radeon *radeon)
 {
-	struct r600_screen* rscreen;
-	enum radeon_family family = radeon_get_family(rw);
+	struct r600_screen *rscreen;
 
 	rscreen = CALLOC_STRUCT(r600_screen);
 	if (rscreen == NULL) {
 		return NULL;
 	}
-	
-	/* don't enable mem constant for r600 yet */
-	rscreen->use_mem_constant = FALSE;
 
-	switch (family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-		rscreen->chip_class = R600;
-		break;
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-		rscreen->chip_class = R700;
-		break;
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-		rscreen->chip_class = EVERGREEN;
-		rscreen->use_mem_constant = TRUE;
-		break;
-	default:
-		FREE(rscreen);
-		return NULL;
-	}
-	radeon_set_mem_constant(rw, rscreen->use_mem_constant);
-	rscreen->rw = rw;
-	rscreen->screen.winsys = (struct pipe_winsys*)rw;
+	rscreen->radeon = radeon;
+	rscreen->screen.winsys = (struct pipe_winsys*)radeon;
 	rscreen->screen.destroy = r600_destroy_screen;
 	rscreen->screen.get_name = r600_get_name;
 	rscreen->screen.get_vendor = r600_get_vendor;
@@ -288,5 +442,8 @@ struct pipe_screen *r600_screen_create(struct radeon *rw)
 	rscreen->screen.context_create = r600_create_context;
 	r600_init_screen_texture_functions(&rscreen->screen);
 	r600_init_screen_resource_functions(&rscreen->screen);
+
+	rscreen->tiling_info = r600_get_tiling_info(radeon);
+
 	return &rscreen->screen;
 }
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
new file mode 100644
index 0000000000..35548329e4
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_PIPE_H
+#define R600_PIPE_H
+
+#include <pipe/p_state.h>
+#include <pipe/p_screen.h>
+#include <pipe/p_context.h>
+#include <util/u_math.h>
+#include "r600.h"
+#include "r600_public.h"
+#include "r600_shader.h"
+#include "r600_resource.h"
+
+enum r600_pipe_state_id {
+	R600_PIPE_STATE_BLEND = 0,
+	R600_PIPE_STATE_BLEND_COLOR,
+	R600_PIPE_STATE_CONFIG,
+	R600_PIPE_STATE_CLIP,
+	R600_PIPE_STATE_SCISSOR,
+	R600_PIPE_STATE_VIEWPORT,
+	R600_PIPE_STATE_RASTERIZER,
+	R600_PIPE_STATE_VGT,
+	R600_PIPE_STATE_FRAMEBUFFER,
+	R600_PIPE_STATE_DSA,
+	R600_PIPE_STATE_STENCIL_REF,
+	R600_PIPE_STATE_PS_SHADER,
+	R600_PIPE_STATE_VS_SHADER,
+	R600_PIPE_STATE_CONSTANT,
+	R600_PIPE_STATE_SAMPLER,
+	R600_PIPE_STATE_RESOURCE,
+	R600_PIPE_NSTATES
+};
+
+struct r600_screen {
+	struct pipe_screen		screen;
+	struct radeon			*radeon;
+	struct r600_tiling_info		*tiling_info;
+};
+
+struct r600_pipe_sampler_view {
+	struct pipe_sampler_view	base;
+	struct r600_pipe_state		state;
+};
+
+struct r600_pipe_rasterizer {
+	struct r600_pipe_state		rstate;
+	bool				flatshade;
+	unsigned			sprite_coord_enable;
+	float				offset_units;
+	float				offset_scale;
+};
+
+struct r600_pipe_blend {
+	struct r600_pipe_state		rstate;
+	unsigned			cb_target_mask;
+};
+
+struct r600_vertex_element
+{
+	unsigned			count;
+	unsigned			refcount;
+	struct pipe_vertex_element	elements[32];
+};
+
+struct r600_pipe_shader {
+	struct r600_shader		shader;
+	struct r600_pipe_state		rstate;
+	struct r600_bo			*bo;
+	struct r600_vertex_element	vertex_elements;
+};
+
+/* needed for blitter save */
+struct r600_textures_info {
+	struct r600_pipe_sampler_view   **views;
+	unsigned                        n_views;
+	void				**samplers;
+	unsigned                        n_samplers;
+};
+
+#define R600_CONSTANT_ARRAY_SIZE 256
+#define R600_RESOURCE_ARRAY_SIZE 160
+
+struct r600_pipe_context {
+	struct pipe_context		context;
+	struct blitter_context		*blitter;
+	struct pipe_framebuffer_state	*pframebuffer;
+	unsigned			family;
+	void				*custom_dsa_flush;
+	struct r600_screen		*screen;
+	struct radeon			*radeon;
+	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
+	struct r600_context		ctx;
+	struct r600_vertex_element	*vertex_elements;
+	struct pipe_framebuffer_state	framebuffer;
+	struct pipe_index_buffer	index_buffer;
+	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
+	unsigned			nvertex_buffer;
+	unsigned			cb_target_mask;
+	/* for saving when using blitter */
+	struct pipe_stencil_ref		stencil_ref;
+	struct pipe_viewport_state	viewport;
+	struct pipe_clip_state		clip;
+	struct r600_pipe_state		*vs_resource;
+	struct r600_pipe_state		*ps_resource;
+	struct r600_pipe_state		config;
+	struct r600_pipe_shader 	*ps_shader;
+	struct r600_pipe_shader 	*vs_shader;
+	struct r600_pipe_state		vs_const_buffer;
+	struct r600_pipe_state		ps_const_buffer;
+	struct r600_pipe_rasterizer	*rasterizer;
+	/* shader information */
+	unsigned			sprite_coord_enable;
+	bool				flatshade;
+	struct u_upload_mgr		*upload_vb;
+	struct u_upload_mgr		*upload_ib;
+	unsigned			any_user_vbs;
+	struct r600_textures_info       ps_samplers;
+
+};
+
+struct r600_drawl {
+	struct pipe_context	*ctx;
+	unsigned		mode;
+	unsigned		min_index;
+	unsigned		max_index;
+	unsigned		index_bias;
+	unsigned		start;
+	unsigned		count;
+	unsigned		index_size;
+	unsigned		index_buffer_offset;
+	struct pipe_resource	*index_buffer;
+};
+
+/* evergreen_state.c */
+void evergreen_init_state_functions(struct r600_pipe_context *rctx);
+void evergreen_init_config(struct r600_pipe_context *rctx);
+void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
+
+/* r600_blit.c */
+void r600_init_blit_functions(struct r600_pipe_context *rctx);
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
+/* r600_buffer.c */
+struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
+					 const struct pipe_resource *templ);
+struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
+					      void *ptr, unsigned bytes,
+					      unsigned bind);
+unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
+					 struct pipe_resource *buf,
+					 unsigned face, unsigned level);
+struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
+					      struct winsys_handle *whandle);
+int r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw);
+int r600_upload_user_buffers(struct r600_pipe_context *rctx);
+
+/* r600_query.c */
+void r600_init_query_functions(struct r600_pipe_context *rctx);
+
+/* r600_resource.c */
+void r600_init_context_resource_functions(struct r600_pipe_context *r600);
+
+/* r600_shader.c */
+int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader);
+int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens);
+int r600_find_vs_semantic_index(struct r600_shader *vs,
+				struct r600_shader *ps, int id);
+
+/* r600_state.c */
+void r600_init_state_functions(struct r600_pipe_context *rctx);
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void r600_init_config(struct r600_pipe_context *rctx);
+void r600_translate_index_buffer(struct r600_pipe_context *r600,
+					struct pipe_resource **index_buffer,
+					unsigned *index_size,
+					unsigned *start, unsigned count);
+void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
+/* r600_helper.h */
+int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
+
+/* r600_texture.c */
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
+uint32_t r600_translate_texformat(enum pipe_format format,
+				  const unsigned char *swizzle_view, 
+				  uint32_t *word4_p, uint32_t *yuv_format_p);
+
+/*
+ * common helpers
+ */
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+
+#endif
diff --git a/src/gallium/drivers/r600/r600_public.h b/src/gallium/drivers/r600/r600_public.h
index 1d89c9f9f6..f1970201e8 100644
--- a/src/gallium/drivers/r600/r600_public.h
+++ b/src/gallium/drivers/r600/r600_public.h
@@ -1,9 +1,28 @@
-
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
 #ifndef R600_PUBLIC_H
 #define R600_PUBLIC_H
 
-struct radeon;
-
-struct pipe_screen* r600_screen_create(struct radeon *rw);
+struct pipe_screen *r600_screen_create(struct radeon *radeon);
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 12900cce11..726668260c 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -19,231 +19,55 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
  */
-#include <errno.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include "r600_screen.h"
-#include "r600_context.h"
-
-static void r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate = &rquery->rstate;
-
-	radeon_state_fini(rstate);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_BEGIN, 0, 0);
-	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-	}
-}
-
-static void r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate = &rquery->rstate;
-
-	radeon_state_fini(rstate);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_END, 0, 0);
-	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-	}
-}
+#include "r600_pipe.h"
 
 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *q;
-
-	if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
-		return NULL;
-
-	q = CALLOC_STRUCT(r600_query);
-	if (!q)
-		return NULL;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
-	q->type = query_type;
-	q->buffer_size = 4096;
-
-	q->buffer = radeon_ws_bo(rscreen->rw, q->buffer_size, 1, 0);
-	if (!q->buffer) {
-		FREE(q);
-		return NULL;
-	}
-
-	LIST_ADDTAIL(&q->list, &rctx->query_list);
-
-	return (struct pipe_query *)q;
-}
-
-static void r600_destroy_query(struct pipe_context *ctx,
-			       struct pipe_query *query)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_query *q = r600_query(query);
-
-	radeon_ws_bo_reference(rscreen->rw, &q->buffer, NULL);
-	LIST_DEL(&q->list);
-	FREE(query);
+	return (struct pipe_query*)r600_context_query_create(&rctx->ctx, query_type);
 }
 
-static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquery)
+static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	u64 start, end;
-	u32 *results;
-	int i;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
-	radeon_ws_bo_wait(rscreen->rw, rquery->buffer);
-	results = radeon_ws_bo_map(rscreen->rw, rquery->buffer, 0, r600_context(ctx));
-	for (i = 0; i < rquery->num_results; i += 4) {
-		start = (u64)results[i] | (u64)results[i + 1] << 32;
-		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
-		if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
-			rquery->result += end - start;
-		}
-	}
-	radeon_ws_bo_unmap(rscreen->rw, rquery->buffer);
-	rquery->num_results = 0;
-}
-
-static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquery)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (rquery->num_results >= ((rquery->buffer_size >> 2) - 2)) {
-		/* running out of space */
-		if (!rquery->flushed) {
-			ctx->flush(ctx, 0, NULL);
-		}
-		r600_query_result(ctx, rquery);
-	}
-	r600_query_begin(rctx, rquery);
-	rquery->flushed = false;
-}
-
-static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rquery)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	r600_query_end(rctx, rquery);
-	rquery->num_results += 16;
+	r600_context_query_destroy(&rctx->ctx, (struct r600_query *)query);
 }
 
 static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = r600_query(query);
-	int r;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_query *rquery = (struct r600_query *)query;
 
-	rquery->state = R600_QUERY_STATE_STARTED;
+	rquery->result = 0;
 	rquery->num_results = 0;
-	rquery->flushed = false;
-	r600_query_resume(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	if (r == -EBUSY) {
-		/* this shouldn't happen */
-		R600_ERR("had to flush while emitting end query\n");
-		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	}
+	r600_query_begin(&rctx->ctx, (struct r600_query *)query);
 }
 
 static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = r600_query(query);
-	int r;
-
-	rquery->state &= ~R600_QUERY_STATE_STARTED;
-	rquery->state |= R600_QUERY_STATE_ENDED;
-	r600_query_suspend(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	if (r == -EBUSY) {
-		/* this shouldn't happen */
-		R600_ERR("had to flush while emitting end query\n");
-		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	}
-}
-
-void r600_queries_suspend(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery;
-	int r;
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			r600_query_suspend(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			if (r == -EBUSY) {
-				/* this shouldn't happen */
-				R600_ERR("had to flush while emitting end query\n");
-				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			}
-		}
-		rquery->state |= R600_QUERY_STATE_SUSPENDED;
-	}
-}
-
-void r600_queries_resume(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery;
-	int r;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			r600_query_resume(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			if (r == -EBUSY) {
-				/* this shouldn't happen */
-				R600_ERR("had to flush while emitting end query\n");
-				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			}
-		}
-		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
-	}
+	r600_query_end(&rctx->ctx, (struct r600_query *)query);
 }
 
 static boolean r600_get_query_result(struct pipe_context *ctx,
 					struct pipe_query *query,
 					boolean wait, void *vresult)
 {
-	struct r600_query *rquery = r600_query(query);
-	uint64_t *result = (uint64_t*)vresult;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_query *rquery = (struct r600_query *)query;
 
-	if (!rquery->flushed) {
+	if (rquery->num_results) {
 		ctx->flush(ctx, 0, NULL);
-		rquery->flushed = true;
 	}
-	r600_query_result(ctx, rquery);
-	*result = rquery->result;
-	rquery->result = 0;
-	return TRUE;
+	return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
 }
 
-void r600_init_query_functions(struct r600_context* rctx)
+void r600_init_query_functions(struct r600_pipe_context *rctx)
 {
-	LIST_INITHEAD(&rctx->query_list);
-
 	rctx->context.create_query = r600_create_query;
 	rctx->context.destroy_query = r600_destroy_query;
 	rctx->context.begin_query = r600_begin_query;
diff --git a/src/gallium/drivers/r600/r600_resource.c b/src/gallium/drivers/r600/r600_resource.c
index 05707740da..207642ccfa 100644
--- a/src/gallium/drivers/r600/r600_resource.c
+++ b/src/gallium/drivers/r600/r600_resource.c
@@ -21,9 +21,7 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "r600_screen.h"
+#include "r600_pipe.h"
 
 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
@@ -46,7 +44,16 @@ static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * scre
 	}
 }
 
-void r600_init_context_resource_functions(struct r600_context *r600)
+void r600_init_screen_resource_functions(struct pipe_screen *screen)
+{
+	screen->resource_create = r600_resource_create;
+	screen->resource_from_handle = r600_resource_from_handle;
+	screen->resource_get_handle = u_resource_get_handle_vtbl;
+	screen->resource_destroy = u_resource_destroy_vtbl;
+	screen->user_buffer_create = r600_user_buffer_create;
+}
+
+void r600_init_context_resource_functions(struct r600_pipe_context *r600)
 {
 	r600->context.get_transfer = u_get_transfer_vtbl;
 	r600->context.transfer_map = u_transfer_map_vtbl;
@@ -56,12 +63,3 @@ void r600_init_context_resource_functions(struct r600_context *r600)
 	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
 	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
 }
-
-void r600_init_screen_resource_functions(struct pipe_screen *screen)
-{
-	screen->resource_create = r600_resource_create;
-	screen->resource_from_handle = r600_resource_from_handle;
-	screen->resource_get_handle = u_resource_get_handle_vtbl;
-	screen->resource_destroy = u_resource_destroy_vtbl;
-	screen->user_buffer_create = r600_user_buffer_create;
-}
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 6ddb1ad32a..ef484aba4a 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -25,8 +25,15 @@
 
 #include "util/u_transfer.h"
 
-struct r600_context;
-struct r600_screen;
+/* Texture transfer. */
+struct r600_transfer {
+	/* Base class. */
+	struct pipe_transfer		transfer;
+	/* Buffer transfer. */
+	struct pipe_transfer		*buffer_transfer;
+	unsigned			offset;
+	struct pipe_resource		*linear_texture;
+};
 
 /* This gets further specialized into either buffer or texture
  * structures. Use the vtbl struct to choose between the two
@@ -34,7 +41,7 @@ struct r600_screen;
  */
 struct r600_resource {
 	struct u_resource		base;
-	struct radeon_ws_bo		*bo;
+	struct r600_bo			*bo;
 	u32				domain;
 	u32				flink;
 	u32				size;
@@ -42,27 +49,20 @@ struct r600_resource {
 
 struct r600_resource_texture {
 	struct r600_resource		resource;
-	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			width[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			height[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			pitch_override;
-	unsigned long			bpt;
-	unsigned long			size;
-	unsigned			tilled;
+	unsigned			offset[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned			pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned			pitch_in_pixels[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned			layer_size[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned			pitch_override;
+	unsigned			size;
+	unsigned			tiled;
 	unsigned			array_mode;
 	unsigned			tile_type;
 	unsigned			depth;
 	unsigned			dirty;
-	struct radeon_ws_bo		*uncompressed;
-	struct radeon_state		scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		cb[8][PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		db[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		viewport[PIPE_MAX_TEXTURE_LEVELS];
+	struct r600_resource_texture    *flushed_depth_texture;
 };
 
-void r600_init_context_resource_functions(struct r600_context *r600);
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
 /* r600_buffer */
@@ -103,7 +103,25 @@ static INLINE struct r600_resource_buffer *r600_buffer(struct pipe_resource *buf
 
 static INLINE boolean r600_buffer_is_user_buffer(struct pipe_resource *buffer)
 {
-    return r600_buffer(buffer)->user_buffer ? true : false;
+    return r600_buffer(buffer)->user_buffer ? TRUE : FALSE;
 }
 
+int r600_texture_depth_flush(struct pipe_context *ctx,
+			     struct pipe_resource *texture);
+
+extern int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
+/* r600_texture.c texture transfer functions. */
+struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
+						struct pipe_resource *texture,
+						struct pipe_subresource sr,
+						unsigned usage,
+						const struct pipe_box *box);
+void r600_texture_transfer_destroy(struct pipe_context *ctx,
+				   struct pipe_transfer *trans);
+void* r600_texture_transfer_map(struct pipe_context *ctx,
+				struct pipe_transfer* transfer);
+void r600_texture_transfer_unmap(struct pipe_context *ctx,
+				 struct pipe_transfer* transfer);
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
deleted file mode 100644
index 4be77865fb..0000000000
--- a/src/gallium/drivers/r600/r600_screen.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_SCREEN_H
-#define R600_SCREEN_H
-
-#include <pipe/p_state.h>
-#include <pipe/p_screen.h>
-#include <pipebuffer/pb_buffer.h>
-#include <xf86drm.h>
-#include <radeon_drm.h>
-#include "radeon.h"
-#include "util/u_transfer.h"
-#include "r600_resource.h"
-
-/* Texture transfer. */
-struct r600_transfer {
-	/* Base class. */
-	struct pipe_transfer		transfer;
-	/* Buffer transfer. */
-	struct pipe_transfer		*buffer_transfer;
-	unsigned			offset;
-	struct pipe_resource		*linear_texture;
-};
-
-enum chip_class {
-	R600,
-	R700,
-	EVERGREEN,
-};
-
-struct r600_screen {
-	struct pipe_screen		screen;
-	struct radeon			*rw;
-	enum chip_class			chip_class;
-	boolean use_mem_constant;
-};
-
-static INLINE struct r600_screen *r600_screen(struct pipe_screen *screen)
-{
-	return (struct r600_screen*)screen;
-}
-
-/* Buffer functions. */
-struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
-					 const struct pipe_resource *templ);
-struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
-					      void *ptr, unsigned bytes,
-					      unsigned bind);
-unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
-					 struct pipe_resource *buf,
-					 unsigned face, unsigned level);
-struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
-					      struct winsys_handle *whandle);
-
-/* r600_texture.c texture transfer functions. */
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-						struct pipe_resource *texture,
-						struct pipe_subresource sr,
-						unsigned usage,
-						const struct pipe_box *box);
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *trans);
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-				struct pipe_transfer* transfer);
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-				 struct pipe_transfer* transfer);
-int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level);
-int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-
-/* r600_blit.c */
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-
-/* helpers */
-int r600_conv_pipe_format(unsigned pformat, unsigned *format);
-int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
-
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-
-#endif
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 4da6850b0a..d1143985ea 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -25,9 +25,7 @@
 #include "tgsi/tgsi_scan.h"
 #include "tgsi/tgsi_dump.h"
 #include "util/u_format.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_shader.h"
+#include "r600_pipe.h"
 #include "r600_asm.h"
 #include "r600_sq.h"
 #include "r600_opcodes.h"
@@ -35,38 +33,227 @@
 #include <stdio.h>
 #include <errno.h>
 
+static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned spi_vs_out_id[10];
+	unsigned i, tmp;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	/* so far never got proper semantic id from tgsi */
+	for (i = 0; i < 10; i++) {
+		spi_vs_out_id[i] = 0;
+	}
+	for (i = 0; i < 32; i++) {
+		tmp = i << ((i & 3) * 8);
+		spi_vs_out_id[i / 4] |= tmp;
+	}
+	for (i = 0; i < 10; i++) {
+		r600_pipe_state_add_reg(rstate,
+					R_028614_SPI_VS_OUT_ID_0 + i * 4,
+					spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+	}
+
+	r600_pipe_state_add_reg(rstate,
+			R_0286C4_SPI_VS_OUT_CONFIG,
+			S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_028868_SQ_PGM_RESOURCES_VS,
+			S_028868_NUM_GPRS(rshader->bc.ngpr) |
+			S_028868_STACK_SIZE(rshader->bc.nstack),
+			0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_0288A4_SQ_PGM_RESOURCES_FS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_0288D0_SQ_PGM_CF_OFFSET_VS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_0288DC_SQ_PGM_CF_OFFSET_FS,
+			0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+			R_028858_SQ_PGM_START_VS,
+			r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate,
+			R_028894_SQ_PGM_START_FS,
+			r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+
+	r600_pipe_state_add_reg(rstate,
+				R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
+				0xFFFFFFFF, NULL);
 
-struct r600_shader_tgsi_instruction;
+}
 
-struct r600_shader_ctx {
-	struct tgsi_shader_info			info;
-	struct tgsi_parse_context		parse;
-	const struct tgsi_token			*tokens;
-	unsigned				type;
-	unsigned				file_offset[TGSI_FILE_COUNT];
-	unsigned				temp_reg;
-	struct r600_shader_tgsi_instruction	*inst_info;
-	struct r600_bc				*bc;
-	struct r600_shader			*shader;
-	u32					value[4];
-	u32					*literals;
-	u32					nliterals;
-	u32					max_driver_temp_used;
-};
+int r600_find_vs_semantic_index(struct r600_shader *vs,
+				struct r600_shader *ps, int id)
+{
+	struct r600_shader_io *input = &ps->input[id];
 
-struct r600_shader_tgsi_instruction {
-	unsigned	tgsi_opcode;
-	unsigned	is_op3;
-	unsigned	r600_opcode;
-	int (*process)(struct r600_shader_ctx *ctx);
-};
+	for (int i = 0; i < vs->noutput; i++) {
+		if (input->name == vs->output[i].name &&
+			input->sid == vs->output[i].sid) {
+			return i - 1;
+		}
+	}
+	return 0;
+}
 
-static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
-static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
+static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = &shader->rstate;
+	struct r600_shader *rshader = &shader->shader;
+	unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1;
+	int pos_index = -1, face_index = -1;
+
+	/* clear previous register */
+	rstate->nregs = 0;
+
+	for (i = 0; i < rshader->ninput; i++) {
+		tmp = S_028644_SEMANTIC(r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i));
+		if (rshader->input[i].centroid)
+			tmp |= S_028644_SEL_CENTROID(1);
+		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
+			tmp |= S_028644_SEL_LINEAR(1);
+
+		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+			pos_index = i;
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
+		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
+			face_index = i;
+		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
+			rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
+			tmp |= S_028644_PT_SPRITE_TEX(1);
+		}
+		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
+	}
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			r600_pipe_state_add_reg(rstate,
+						R_02880C_DB_SHADER_CONTROL,
+						S_02880C_Z_EXPORT_ENABLE(1),
+						S_02880C_Z_EXPORT_ENABLE(1), NULL);
+		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
+			r600_pipe_state_add_reg(rstate,
+						R_02880C_DB_SHADER_CONTROL,
+						S_02880C_STENCIL_REF_EXPORT_ENABLE(1),
+						S_02880C_STENCIL_REF_EXPORT_ENABLE(1), NULL);
+	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			num_cout++;
+		}
+	}
+	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
+	if (!exports_ps) {
+		/* always at least export 1 component per pixel */
+		exports_ps = 2;
+	}
+
+	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
+				S_0286CC_PERSP_GRADIENT_ENA(1);
+	spi_input_z = 0;
+	if (pos_index != -1) {
+		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
+					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
+					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
+					S_0286CC_BARYC_SAMPLE_CNTL(1));
+		spi_input_z |= 1;
+	}
+
+	spi_ps_in_control_1 = 0;
+	if (face_index != -1) {
+		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
+			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
+	}
+
+	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028840_SQ_PGM_START_PS,
+				r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+	r600_pipe_state_add_reg(rstate,
+				R_028850_SQ_PGM_RESOURCES_PS,
+				S_028868_NUM_GPRS(rshader->bc.ngpr) |
+				S_028868_STACK_SIZE(rshader->bc.nstack),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028854_SQ_PGM_EXPORTS_PS,
+				exports_ps, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_0288CC_SQ_PGM_CF_OFFSET_PS,
+				0x00000000, 0xFFFFFFFF, NULL);
+
+	if (rshader->uses_kill) {
+		/* only set some bits here, the other bits are set in the dsa state */
+		r600_pipe_state_add_reg(rstate,
+					R_02880C_DB_SHADER_CONTROL,
+					S_02880C_KILL_ENABLE(1),
+					S_02880C_KILL_ENABLE(1), NULL);
+	}
+	r600_pipe_state_add_reg(rstate,
+				R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
+				0xFFFFFFFF, NULL);
+}
 
-static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
 {
-	struct r600_context *rctx = r600_context(ctx);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_shader *rshader = &shader->shader;
+	void *ptr;
+
+	/* copy new shader */
+	if (shader->bo == NULL) {
+		shader->bo = r600_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
+		if (shader->bo == NULL) {
+			return -ENOMEM;
+		}
+		ptr = r600_bo_map(rctx->radeon, shader->bo, 0, NULL);
+		memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
+		r600_bo_unmap(rctx->radeon, shader->bo);
+	}
+	/* build state */
+	rshader->flat_shade = rctx->flatshade;
+	switch (rshader->processor_type) {
+	case TGSI_PROCESSOR_VERTEX:
+		if (rshader->family >= CHIP_CEDAR) {
+			evergreen_pipe_shader_vs(ctx, shader);
+		} else {
+			r600_pipe_shader_vs(ctx, shader);
+		}
+		break;
+	case TGSI_PROCESSOR_FRAGMENT:
+		if (rshader->family >= CHIP_CEDAR) {
+			evergreen_pipe_shader_ps(ctx, shader);
+		} else {
+			r600_pipe_shader_ps(ctx, shader);
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+	r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
+	return 0;
+}
+
+static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_shader *shader = &rshader->shader;
 	const struct util_format_description *desc;
 	enum pipe_format resource_format[160];
 	unsigned i, nresources = 0;
@@ -76,9 +263,16 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shad
 
 	if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
 		return 0;
+	/* doing a full memcmp fell over the refcount */
+	if ((rshader->vertex_elements.count == rctx->vertex_elements->count) &&
+	    (!memcmp(&rshader->vertex_elements.elements, &rctx->vertex_elements->elements, 32 * sizeof(struct pipe_vertex_element)))) {
+		return 0;
+	}
+	rshader->vertex_elements = *rctx->vertex_elements;
 	for (i = 0; i < rctx->vertex_elements->count; i++) {
 		resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
 	}
+	r600_bo_reference(rctx->radeon, &rshader->bo, NULL);
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
 		switch (cf->inst) {
 		case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
@@ -102,25 +296,40 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shad
 	return r600_bc_build(&shader->bc);
 }
 
-int r600_pipe_shader_create(struct pipe_context *ctx,
-			struct r600_context_state *rpshader,
-			const struct tgsi_token *tokens)
+int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *shader)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	int r;
+
+	if (shader == NULL)
+		return -EINVAL;
+	/* there should be enough input */
+	if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
+		R600_ERR("%d resources provided, expecting %d\n",
+			rctx->vertex_elements->count, shader->shader.bc.nresource);
+		return -EINVAL;
+	}
+	r = r600_shader_update(ctx, shader);
+	if (r)
+		return r;
+	return r600_pipe_shader(ctx, shader);
+}
+
+int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
+int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	int r;
 
 //fprintf(stderr, "--------------------------------------------------------------\n");
 //tgsi_dump(tokens, 0);
-	if (rpshader == NULL)
-		return -ENOMEM;
-	rpshader->shader.family = radeon_get_family(rscreen->rw);
-	rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
-	r = r600_shader_from_tgsi(tokens, &rpshader->shader);
+	shader->shader.family = r600_get_family(rctx->radeon);
+	r = r600_shader_from_tgsi(tokens, &shader->shader);
 	if (r) {
 		R600_ERR("translation from TGSI failed !\n");
 		return r;
 	}
-	r = r600_bc_build(&rpshader->shader.bc);
+	r = r600_bc_build(&shader->shader.bc);
 	if (r) {
 		R600_ERR("building bytecode failed !\n");
 		return r;
@@ -129,81 +338,41 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 	return 0;
 }
 
-static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *state;
-
-	state = &rpshader->rstate[0];
-	radeon_state_fini(&rpshader->rstate[0]);
-
-	return rctx->vtbl->vs_shader(rctx, rpshader, state);
-}
-
-static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *state;
-
-	state = &rpshader->rstate[0];
-	radeon_state_fini(state);
-
-	return rctx->vtbl->ps_shader(rctx, rpshader, state);
-}
-
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_shader *rshader = &rpshader->shader;
-	int r;
-	void *data;
+/*
+ * tgsi -> r600 shader
+ */
+struct r600_shader_tgsi_instruction;
 
-	/* copy new shader */
-	radeon_ws_bo_reference(rscreen->rw, &rpshader->bo, NULL);
-	rpshader->bo = NULL;
-	rpshader->bo = radeon_ws_bo(rscreen->rw, rshader->bc.ndw * 4,
-				    4096, 0);
-	if (rpshader->bo == NULL) {
-		return -ENOMEM;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, rpshader->bo, 0, rctx);
-	memcpy(data, rshader->bc.bytecode, rshader->bc.ndw * 4);
-	radeon_ws_bo_unmap(rscreen->rw, rpshader->bo);
-	/* build state */
-	rshader->flat_shade = rctx->flat_shade;
-	switch (rshader->processor_type) {
-	case TGSI_PROCESSOR_VERTEX:
-		r = r600_pipe_shader_vs(ctx, rpshader);
-		break;
-	case TGSI_PROCESSOR_FRAGMENT:
-		r = r600_pipe_shader_ps(ctx, rpshader);
-		break;
-	default:
-		r = -EINVAL;
-		break;
-	}
-	return r;
-}
+struct r600_shader_ctx {
+	struct tgsi_shader_info			info;
+	struct tgsi_parse_context		parse;
+	const struct tgsi_token			*tokens;
+	unsigned				type;
+	unsigned				file_offset[TGSI_FILE_COUNT];
+	unsigned				temp_reg;
+	struct r600_shader_tgsi_instruction	*inst_info;
+	struct r600_bc				*bc;
+	struct r600_shader			*shader;
+	u32					value[4];
+	u32					*literals;
+	u32					nliterals;
+	u32					max_driver_temp_used;
+	/* needed for evergreen interpolation */
+	boolean                                 input_centroid;
+	boolean                                 input_linear;
+	boolean                                 input_perspective;
+	int					num_interp_gpr;
+};
 
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	int r;
+struct r600_shader_tgsi_instruction {
+	unsigned	tgsi_opcode;
+	unsigned	is_op3;
+	unsigned	r600_opcode;
+	int (*process)(struct r600_shader_ctx *ctx);
+};
 
-	if (rpshader == NULL)
-		return -EINVAL;
-	/* there should be enough input */
-	if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
-		R600_ERR("%d resources provided, expecting %d\n",
-			rctx->vertex_elements->count, rpshader->shader.bc.nresource);
-		return -EINVAL;
-	}
-	r = r600_shader_update(ctx, &rpshader->shader);
-	if (r)
-		return r;
-	return r600_pipe_shader(ctx, rpshader);
-}
+static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
+static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
 
 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 {
@@ -225,11 +394,9 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 	}
 #endif
 	for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
-		if (i->Src[j].Register.Dimension ||
-			i->Src[j].Register.Absolute) {
-			R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
-				 i->Src[j].Register.Dimension,
-				 i->Src[j].Register.Absolute);
+		if (i->Src[j].Register.Dimension) {
+			R600_ERR("unsupported src %d (dimension %d)\n", j,
+				 i->Src[j].Register.Dimension);
 			return -EINVAL;
 		}
 	}
@@ -242,10 +409,33 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
-static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
+static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int input)
 {
 	int i, r;
 	struct r600_bc_alu alu;
+	int gpr = 0, base_chan = 0;
+	int ij_index = 0;
+
+	if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) {
+		ij_index = 0;
+		if (ctx->shader->input[input].centroid)
+			ij_index++;
+	} else if (ctx->shader->input[input].interpolate == TGSI_INTERPOLATE_LINEAR) {
+		ij_index = 0;
+		/* if we have perspective add one */
+		if (ctx->input_perspective)  {
+			ij_index++;
+			/* if we have perspective centroid */
+			if (ctx->input_centroid)
+				ij_index++;
+		}
+		if (ctx->shader->input[input].centroid)
+			ij_index++;
+	}
+		
+	/* work out gpr and base_chan from index */
+	gpr = ij_index / 2;
+	base_chan = (2 * (ij_index % 2)) + 1;
 
 	for (i = 0; i < 8; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -256,13 +446,16 @@ static int evergreen_interp_alu(struct r600_shader_ctx *ctx, int gpr)
 			alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INTERP_XY;
 
 		if ((i > 1) && (i < 6)) {
-			alu.dst.sel = ctx->shader->input[gpr].gpr;
+			alu.dst.sel = ctx->shader->input[input].gpr;
 			alu.dst.write = 1;
 		}
 
 		alu.dst.chan = i % 4;
-		alu.src[0].chan = (1 - (i % 2));
-		alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + gpr;
+
+		alu.src[0].sel = gpr;
+		alu.src[0].chan = (base_chan - (i % 2));
+
+		alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos;
 
 		alu.bank_swizzle_force = SQ_ALU_VEC_210;
 		if ((i % 4) == 3)
@@ -288,6 +481,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		ctx->shader->input[i].name = d->Semantic.Name;
 		ctx->shader->input[i].sid = d->Semantic.Index;
 		ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
+		ctx->shader->input[i].centroid = d->Declaration.Centroid;
 		ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
 		if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 			/* turn input into fetch */
@@ -304,13 +498,19 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 			vtx.dst_sel_y = 1;
 			vtx.dst_sel_z = 2;
 			vtx.dst_sel_w = 3;
+			vtx.use_const_fields = 1;
 			r = r600_bc_add_vtx(ctx->bc, &vtx);
 			if (r)
 				return r;
 		}
 		if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev == 2) {
 			/* turn input into interpolate on EG */
-			evergreen_interp_alu(ctx, i);
+			if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
+				if (ctx->shader->input[i].interpolate > 0) {
+					ctx->shader->input[i].lds_pos = ctx->shader->nlds++;
+					evergreen_interp_alu(ctx, i);
+				}
+			}
 		}
 		break;
 	case TGSI_FILE_OUTPUT:
@@ -337,6 +537,53 @@ static int r600_get_temp(struct r600_shader_ctx *ctx)
 	return ctx->temp_reg + ctx->max_driver_temp_used++;
 }
 
+/* 
+ * for evergreen we need to scan the shader to find the number of GPRs we need to
+ * reserve for interpolation.
+ *
+ * we need to know if we are going to emit
+ * any centroid inputs
+ * if perspective and linear are required
+*/
+static int evergreen_gpr_count(struct r600_shader_ctx *ctx)
+{
+	int i;
+	int num_baryc;
+
+	ctx->input_linear = FALSE;
+	ctx->input_perspective = FALSE;
+	ctx->input_centroid = FALSE;
+	ctx->num_interp_gpr = 1;
+
+	/* any centroid inputs */
+	for (i = 0; i < ctx->info.num_inputs; i++) {
+		/* skip position/face */
+		if (ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_POSITION ||
+		    ctx->info.input_semantic_name[i] == TGSI_SEMANTIC_FACE)
+			continue;
+		if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_LINEAR)
+			ctx->input_linear = TRUE;
+		if (ctx->info.input_interpolate[i] == TGSI_INTERPOLATE_PERSPECTIVE)
+			ctx->input_perspective = TRUE;
+		if (ctx->info.input_centroid[i])
+			ctx->input_centroid = TRUE;
+	}
+
+	num_baryc = 0;
+	/* ignoring sample for now */
+	if (ctx->input_perspective)
+		num_baryc++;
+	if (ctx->input_linear)
+		num_baryc++;
+	if (ctx->input_centroid)
+		num_baryc *= 2;
+
+	ctx->num_interp_gpr += (num_baryc + 1) >> 1;
+
+	/* TODO PULL MODEL and LINE STIPPLE, FIXED PT POS */
+	return ctx->num_interp_gpr;
+}
+
 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
 {
 	struct tgsi_full_immediate *immediate;
@@ -351,7 +598,6 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	r = r600_bc_init(ctx.bc, shader->family);
 	if (r)
 		return r;
-	ctx.bc->use_mem_constant = shader->use_mem_constant;
 	ctx.tokens = tokens;
 	tgsi_scan_shader(tokens, &ctx.info);
 	tgsi_parse_init(&ctx.parse, tokens);
@@ -383,14 +629,15 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
 	}
+	if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev == 2) {
+		ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
+	}
 	ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
 						ctx.info.file_count[TGSI_FILE_INPUT];
 	ctx.file_offset[TGSI_FILE_TEMPORARY] = ctx.file_offset[TGSI_FILE_OUTPUT] +
 						ctx.info.file_count[TGSI_FILE_OUTPUT];
-	if (ctx.shader->use_mem_constant)
-		ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
-	else
-		ctx.file_offset[TGSI_FILE_CONSTANT] = 256;
+
+	ctx.file_offset[TGSI_FILE_CONSTANT] = 128;
 
 	ctx.file_offset[TGSI_FILE_IMMEDIATE] = 253;
 	ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
@@ -481,7 +728,14 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
 				output[i].array_base = 61;
 				output[i].swizzle_x = 2;
-				output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
+				output[i].swizzle_y = 7;
+				output[i].swizzle_z = output[i].swizzle_w = 7;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+			} else if (shader->output[i].name == TGSI_SEMANTIC_STENCIL) {
+				output[i].array_base = 61;
+				output[i].swizzle_x = 7;
+				output[i].swizzle_y = 1;
+				output[i].swizzle_z = output[i].swizzle_w = 7;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
@@ -514,7 +768,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			output[i].barrier = 1;
 			output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
 			output[i].array_base = 0;
-			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
+			output[i].inst = BC_INST(ctx.bc, V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT);
 			noutput++;
 		}
 	}
@@ -587,6 +841,7 @@ static int tgsi_src(struct r600_shader_ctx *ctx,
 	if (tgsi_src->Register.Indirect)
 		r600_src->rel = V_SQ_REL_RELATIVE;
 	r600_src->neg = tgsi_src->Register.Negate;
+	r600_src->abs = tgsi_src->Register.Absolute;
 	r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
 	return 0;
 }
@@ -642,13 +897,14 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 		}
 	}
 	for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
-		if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
+		if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
 			int treg = r600_get_temp(ctx);
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
-				alu.src[0].sel = r600_src[j].sel;
+				alu.src[0].sel = r600_src[i].sel;
 				alu.src[0].chan = k;
+				alu.src[0].rel = r600_src[i].rel;
 				alu.dst.sel = treg;
 				alu.dst.chan = k;
 				alu.dst.write = 1;
@@ -658,7 +914,8 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 				if (r)
 					return r;
 			}
-			r600_src[j].sel = treg;
+			r600_src[i].sel = treg;
+			r600_src[i].rel =0;
 			j--;
 		}
 	}
@@ -677,13 +934,13 @@ static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_
 			nliteral++;
 		}
 	}
-	for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
-		if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
+	for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
+		if (j > 0 && inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
 			int treg = r600_get_temp(ctx);
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
-				alu.src[0].sel = r600_src[j].sel;
+				alu.src[0].sel = r600_src[i].sel;
 				alu.src[0].chan = k;
 				alu.dst.sel = treg;
 				alu.dst.chan = k;
@@ -694,11 +951,11 @@ static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_
 				if (r)
 					return r;
 			}
-			r = r600_bc_add_literal(ctx->bc, ctx->value);
+			r = r600_bc_add_literal(ctx->bc, &ctx->literals[inst->Src[i].Register.Index * 4]);
 			if (r)
 				return r;
-			r600_src[j].sel = treg;
-			j++;
+			r600_src[i].sel = treg;
+			j--;
 		}
 	}
 	return 0;
@@ -721,6 +978,9 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 	for (i = 0; i < lasti + 1; i++) {
 		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
 			continue;
@@ -791,6 +1051,9 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 
 	r = tgsi_split_literal_constant(ctx, r600_src);
 	if (r)
@@ -926,38 +1189,95 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 	struct r600_bc_alu alu;
 	int r;
 
-	r = tgsi_setup_trig(ctx, r600_src);
-	if (r)
-		return r;
-
+	/* We'll only need the trig stuff if we are going to write to the
+	 * X or Y components of the destination vector.
+	 */
+	if (likely(inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY)) {
+		r = tgsi_setup_trig(ctx, r600_src);
+		if (r)
+			return r;
+	}
 
 	/* dst.x = COS */
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
-	r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
-	if (r)
-		return r;
+	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
+		r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+		if (r)
+			return r;
 
-	alu.src[0].sel = ctx->temp_reg;
-	alu.src[0].chan = 0;
-	alu.last = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 0;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
 
 	/* dst.y = SIN */
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
-	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
-	if (r)
-		return r;
+	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
+		r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+		if (r)
+			return r;
+
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 0;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+
+	/* dst.z = 0.0; */
+	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+
+		r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
+		if (r)
+			return r;
+
+		alu.src[0].sel = V_SQ_ALU_SRC_0;
+		alu.src[0].chan = 0;
+
+		alu.last = 1;
+
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
+	}
+
+	/* dst.w = 1.0; */
+	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
+
+		r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
+		if (r)
+			return r;
+
+		alu.src[0].sel = V_SQ_ALU_SRC_1;
+		alu.src[0].chan = 0;
+
+		alu.last = 1;
+
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
+	}
 
-	alu.src[0].sel = ctx->temp_reg;
-	alu.src[0].chan = 0;
-	alu.last = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
 	return 0;
 }
 
@@ -1157,34 +1477,6 @@ static int tgsi_rsq(struct r600_shader_ctx *ctx)
 	return tgsi_helper_tempx_replicate(ctx);
 }
 
-static int tgsi_trans(struct r600_shader_ctx *ctx)
-{
-	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
-	struct r600_bc_alu alu;
-	int i, j, r;
-
-	for (i = 0; i < 4; i++) {
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		if (inst->Dst[0].Register.WriteMask & (1 << i)) {
-			alu.inst = ctx->inst_info->r600_opcode;
-			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-				r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
-				if (r)
-					return r;
-				alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
-			}
-			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
-			if (r)
-				return r;
-			alu.last = 1;
-			r = r600_bc_add_alu(ctx->bc, &alu);
-			if (r)
-				return r;
-		}
-	}
-	return 0;
-}
-
 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -1301,6 +1593,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 
 	/* tmp = (src > 0 ? 1 : src) */
 	for (i = 0; i < 4; i++) {
@@ -1397,6 +1692,9 @@ static int tgsi_op3(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 	/* do it in 2 step as op3 doesn't support writemask */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1429,6 +1727,9 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
@@ -1502,7 +1803,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
-		
+
 		for (i = 0; i < 3; i++) {
 			memset(&alu, 0, sizeof(struct r600_bc_alu));
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
@@ -1530,7 +1831,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
-		src_not_temp = false;
+		src_not_temp = FALSE;
 		src_gpr = ctx->temp_reg;
 	}
 
@@ -1558,6 +1859,11 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 				src_chan = 1;
 				src2_chan = 2;
 				break;
+			default:
+				assert(0);
+				src_chan = 0;
+				src2_chan = 0;
+				break;
 			}
 			r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 			if (r)
@@ -1641,7 +1947,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_literal(ctx->bc, lit_vals);
 		if (r)
 			return r;
-		src_not_temp = false;
+		src_not_temp = FALSE;
 		src_gpr = ctx->temp_reg;
 	}
 
@@ -1650,7 +1956,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			memset(&alu, 0, sizeof(struct r600_bc_alu));
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
 			alu.src[0].sel = src_gpr;
-			alu.src[0].chan = i;
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = i;
 			if (i == 3)
@@ -1670,14 +1976,16 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
 	tex.inst = opcode;
-	tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
-	tex.sampler_id = tex.resource_id;
+	tex.sampler_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
+	tex.resource_id = tex.sampler_id;
+	if (ctx->shader->processor_type == TGSI_PROCESSOR_VERTEX)
+		tex.resource_id += PIPE_MAX_ATTRIBS;
 	tex.src_gpr = src_gpr;
 	tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
-	tex.dst_sel_x = 0;
-	tex.dst_sel_y = 1;
-	tex.dst_sel_z = 2;
-	tex.dst_sel_w = 3;
+	tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
+	tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
+	tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
+	tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
 	tex.src_sel_x = 0;
 	tex.src_sel_y = 1;
 	tex.src_sel_z = 2;
@@ -1720,6 +2028,9 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 	/* 1 - src0 */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1799,6 +2110,9 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
 
 	if (inst->Dst[0].Register.WriteMask != 0xf)
 		use_temp = 1;
@@ -1850,7 +2164,10 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx)
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
-	
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
+
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
@@ -2293,7 +2610,40 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 }
 
 /* r6/7 only for now */
-static int tgsi_arl(struct r600_shader_ctx *ctx)
+static int tgsi_eg_arl(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int r;
+	
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+	alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR;
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.last = 1;
+	alu.dst.chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+	alu.last = 1;
+	r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
+	if (r)
+		return r;
+	return 0;
+}
+static int tgsi_r600_arl(struct r600_shader_ctx *ctx)
 {
 	/* TODO from r600c, ar values don't persist between clauses */
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -2313,6 +2663,7 @@ static int tgsi_arl(struct r600_shader_ctx *ctx)
 	r = r600_bc_add_alu_type(ctx->bc, &alu, CTX_INST(V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU));
 	if (r)
 		return r;
+	ctx->bc->cf_last->r6xx_uses_waterfall = 1;
 	return 0;
 }
 
@@ -2637,7 +2988,7 @@ static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
 }
 
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
+	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_r600_arl},
 	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_LIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
 
@@ -2718,7 +3069,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_NRM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DP2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_TXL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXL,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
 	{TGSI_OPCODE_BRK,	0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
 	{TGSI_OPCODE_IF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
 	/* gap */
@@ -2801,7 +3152,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 };
 
 static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_eg_arl},
 	{TGSI_OPCODE_MOV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_LIT,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
 	{TGSI_OPCODE_RCP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
@@ -2876,7 +3227,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_NRM,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DIV,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DP2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_TXL,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXL,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
 	{TGSI_OPCODE_BRK,	0, EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
 	{TGSI_OPCODE_IF,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
 	/* gap */
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 06dd65038d..f8bc595139 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -31,6 +31,8 @@ struct r600_shader_io {
 	unsigned		done;
 	int			sid;
 	unsigned		interpolate;
+	boolean                 centroid;
+	unsigned		lds_pos; /* for evergreen */
 };
 
 struct r600_shader {
@@ -39,11 +41,11 @@ struct r600_shader {
 	boolean			flat_shade;
 	unsigned		ninput;
 	unsigned		noutput;
+	unsigned		nlds;
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
 	enum radeon_family	family;
 	boolean			uses_kill;
-	boolean			use_mem_constant;
 };
 
 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 4dcdc492fc..00234f956a 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -19,184 +19,566 @@
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
+ */
+
+/* TODO:
+ *	- fix mask for depth control & cull for query
  */
 #include <stdio.h>
 #include <errno.h>
-#include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "util/u_pack_color.h"
-#include "r600_screen.h"
-#include "r600_context.h"
+#include <pipe/p_defines.h>
+#include <pipe/p_state.h>
+#include <pipe/p_context.h>
+#include <tgsi/tgsi_scan.h>
+#include <tgsi/tgsi_parse.h>
+#include <tgsi/tgsi_util.h>
+#include <util/u_double_list.h>
+#include <util/u_pack_color.h>
+#include <util/u_memory.h>
+#include <util/u_inlines.h>
+#include <util/u_upload_mgr.h>
+#include <util/u_index_modify.h>
+#include <util/u_framebuffer.h>
+#include <pipebuffer/pb_buffer.h>
+#include "r600.h"
+#include "r600d.h"
 #include "r600_resource.h"
+#include "r600_shader.h"
+#include "r600_pipe.h"
+#include "r600_state_inlines.h"
 
-static struct r600_context_state *r600_new_context_state(unsigned type)
+static void r600_draw_common(struct r600_drawl *draw)
 {
-	struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
-	if (rstate == NULL)
-		return NULL;
-	rstate->type = type;
-	rstate->refcount = 1;
-	return rstate;
-}
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
+	struct r600_pipe_state *rstate;
+	struct r600_resource *rbuffer;
+	unsigned i, j, offset, prim;
+	u32 vgt_dma_index_type, vgt_draw_initiator, mask;
+	struct pipe_vertex_buffer *vertex_buffer;
+	struct r600_draw rdraw;
+	struct r600_pipe_state vgt;
+
+	switch (draw->index_size) {
+	case 2:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 0;
+		break;
+	case 4:
+		vgt_draw_initiator = 0;
+		vgt_dma_index_type = 1;
+		break;
+	case 0:
+		vgt_draw_initiator = 2;
+		vgt_dma_index_type = 0;
+		break;
+	default:
+		R600_ERR("unsupported index size %d\n", draw->index_size);
+		return;
+	}
+	if (r600_conv_pipe_prim(draw->mode, &prim))
+		return;
 
-static void *r600_create_blend_state(struct pipe_context *ctx,
-					const struct pipe_blend_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
 
-	rstate = r600_new_context_state(pipe_blend_type);
-	rstate->state.blend = *state;
-	rctx->vtbl->blend(rctx, &rstate->rstate[0], &rstate->state.blend);
-	
-	return rstate;
+	/* rebuild vertex shader if input format changed */
+	if (r600_pipe_shader_update(&rctx->context, rctx->vs_shader))
+		return;
+	if (r600_pipe_shader_update(&rctx->context, rctx->ps_shader))
+		return;
+
+	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+		uint32_t word2, format;
+
+		rstate = &rctx->vs_resource[i];
+		rstate->id = R600_PIPE_STATE_RESOURCE;
+		rstate->nregs = 0;
+
+		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
+		vertex_buffer = &rctx->vertex_buffer[j];
+		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+		offset = rctx->vertex_elements->elements[i].src_offset +
+			vertex_buffer->buffer_offset +
+			r600_bo_offset(rbuffer->bo);
+
+		format = r600_translate_vertex_data_type(rctx->vertex_elements->elements[i].src_format);
+
+		word2 = format | S_038008_STRIDE(vertex_buffer->stride);
+
+		r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
+		r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2, word2, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
+		r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
+	}
+
+	mask = 0;
+	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
+		mask |= (0xF << (i * 4));
+	}
+
+	vgt.id = R600_PIPE_STATE_VGT;
+	vgt.nregs = 0;
+	r600_pipe_state_add_reg(&vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028408_VGT_INDX_OFFSET, draw->index_bias, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028400_VGT_MAX_VTX_INDX, draw->max_index, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028404_VGT_MIN_VTX_INDX, draw->min_index, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(&vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0xFFFFFFFF, NULL);
+	/* build late state */
+	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
+		float offset_units = rctx->rasterizer->offset_units;
+		unsigned offset_db_fmt_cntl = 0, depth;
+
+		switch (rctx->framebuffer.zsbuf->texture->format) {
+		case PIPE_FORMAT_Z24X8_UNORM:
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			depth = -24;
+			offset_units *= 2.0f;
+			break;
+		case PIPE_FORMAT_Z32_FLOAT:
+			depth = -23;
+			offset_units *= 1.0f;
+			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			depth = -16;
+			offset_units *= 4.0f;
+			break;
+		default:
+			return;
+		}
+		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+		r600_pipe_state_add_reg(&vgt,
+				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
+				fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
+				fui(offset_units), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
+				fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
+				fui(offset_units), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&vgt,
+				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+				offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
+	}
+	r600_context_pipe_state_set(&rctx->ctx, &vgt);
+
+	rdraw.vgt_num_indices = draw->count;
+	rdraw.vgt_num_instances = 1;
+	rdraw.vgt_index_type = vgt_dma_index_type;
+	rdraw.vgt_draw_initiator = vgt_draw_initiator;
+	rdraw.indices = NULL;
+	if (draw->index_buffer) {
+		rbuffer = (struct r600_resource*)draw->index_buffer;
+		rdraw.indices = rbuffer->bo;
+		rdraw.indices_bo_offset = draw->index_buffer_offset;
+	}
+	r600_context_draw(&rctx->ctx, &rdraw);
 }
 
-static void *r600_create_dsa_state(struct pipe_context *ctx,
-				   const struct pipe_depth_stencil_alpha_state *state)
+void r600_translate_index_buffer(struct r600_pipe_context *r600,
+					struct pipe_resource **index_buffer,
+					unsigned *index_size,
+					unsigned *start, unsigned count)
 {
-	struct r600_context_state *rstate;
+	switch (*index_size) {
+	case 1:
+		util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
+		*index_size = 2;
+		*start = 0;
+		break;
 
-	rstate = r600_new_context_state(pipe_dsa_type);
-	rstate->state.dsa = *state;
-	return rstate;
+	case 2:
+		if (*start % 2 != 0) {
+			util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
+			*start = 0;
+		}
+		break;
+
+	case 4:
+		break;
+	}
 }
 
-static void *r600_create_rs_state(struct pipe_context *ctx,
-					const struct pipe_rasterizer_state *state)
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_drawl draw;
 
-	rstate = r600_new_context_state(pipe_rasterizer_type);
-	rstate->state.rasterizer = *state;
-	return rstate;
+	if (rctx->any_user_vbs) {
+		r600_upload_user_buffers(rctx);
+		rctx->any_user_vbs = FALSE;
+	}
+
+	memset(&draw, 0, sizeof(struct r600_drawl));
+	draw.ctx = ctx;
+	draw.mode = info->mode;
+	draw.start = info->start;
+	draw.count = info->count;
+	if (info->indexed && rctx->index_buffer.buffer) {
+		draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
+		draw.min_index = info->min_index;
+		draw.max_index = info->max_index;
+		draw.index_bias = info->index_bias;
+
+		r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
+					    &rctx->index_buffer.index_size,
+					    &draw.start,
+					    info->count);
+
+		draw.index_size = rctx->index_buffer.index_size;
+		pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
+		draw.index_buffer_offset = draw.start * draw.index_size;
+		draw.start = 0;
+		r600_upload_index_buffer(rctx, &draw);
+	} else {
+		draw.index_size = 0;
+		draw.index_buffer = NULL;
+		draw.min_index = info->min_index;
+		draw.max_index = info->max_index;
+		draw.index_bias = info->start;
+	}
+	r600_draw_common(&draw);
+
+	pipe_resource_reference(&draw.index_buffer, NULL);
 }
 
-static void *r600_create_sampler_state(struct pipe_context *ctx,
-					const struct pipe_sampler_state *state)
+static void r600_set_blend_color(struct pipe_context *ctx,
+					const struct pipe_blend_color *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 
-	rstate = r600_new_context_state(pipe_sampler_type);
-	rstate->state.sampler = *state;
-	rctx->vtbl->sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
-	rctx->vtbl->sampler_border(rctx, &rstate->rstate[1], &rstate->state.sampler, 0);
-	return rstate;
+	if (rstate == NULL)
+		return;
+
+	rstate->id = R600_PIPE_STATE_BLEND_COLOR;
+	r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
+	free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
+	rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static void r600_remove_sampler_view(struct r600_shader_sampler_states *sampler,
-				     struct r600_context_state *rstate)
+static void *r600_create_blend_state(struct pipe_context *ctx,
+					const struct pipe_blend_state *state)
 {
-	int i, j;
-	
-	for (i = 0; i < sampler->nview; i++) {
-		for (j = 0; j < rstate->nrstate; j++) {
-			if (sampler->view[i] == &rstate->rstate[j])
-				sampler->view[i] = NULL;
+	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
+	struct r600_pipe_state *rstate;
+	u32 color_control, target_mask;
+
+	if (blend == NULL) {
+		return NULL;
+	}
+	rstate = &blend->rstate;
+
+	rstate->id = R600_PIPE_STATE_BLEND;
+
+	target_mask = 0;
+	color_control = S_028808_PER_MRT_BLEND(1);
+	if (state->logicop_enable) {
+		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
+	} else {
+		color_control |= (0xcc << 16);
+	}
+	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
+	if (state->independent_blend_enable) {
+		for (int i = 0; i < 8; i++) {
+			if (state->rt[i].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (state->rt[i].colormask << (4 * i));
+		}
+	} else {
+		for (int i = 0; i < 8; i++) {
+			if (state->rt[0].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (state->rt[0].colormask << (4 * i));
 		}
 	}
-}
-static void r600_sampler_view_destroy(struct pipe_context *ctx,
-				      struct pipe_sampler_view *state)
-{
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-	struct r600_context *rctx = r600_context(ctx);
+	blend->cb_target_mask = target_mask;
+	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
+				color_control, 0xFFFFFFFF, NULL);
+
+	for (int i = 0; i < 8; i++) {
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+		uint32_t bc = 0;
+
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
+			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
+		}
 
-	/* need to search list of vs/ps sampler views and remove it from any - uggh */
-	r600_remove_sampler_view(&rctx->ps_sampler, rstate);
-	r600_remove_sampler_view(&rctx->vs_sampler, rstate);
-	r600_context_state_decref(rstate);
+		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
+		if (i == 0) {
+			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
+		}
+	}
+	return rstate;
 }
 
-static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
-							struct pipe_resource *texture,
-							const struct pipe_sampler_view *state)
+static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context_state *rstate;
-	struct r600_context *rctx = r600_context(ctx);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
+	struct r600_pipe_state *rstate;
 
-	rstate = r600_new_context_state(pipe_sampler_view_type);
-	rstate->state.sampler_view = *state;
-	rstate->state.sampler_view.texture = NULL;
-	pipe_reference(NULL, &texture->reference);
-	rstate->state.sampler_view.texture = texture;
-	rstate->state.sampler_view.reference.count = 1;
-	rstate->state.sampler_view.context = ctx;
-	rctx->vtbl->resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
-	return &rstate->state.sampler_view;
+	if (state == NULL)
+		return;
+	rstate = &blend->rstate;
+	rctx->states[rstate->id] = rstate;
+	rctx->cb_target_mask = blend->cb_target_mask;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static void r600_set_sampler_view(struct pipe_context *ctx,
-				  unsigned count,
-				  struct pipe_sampler_view **views,
-				  struct r600_shader_sampler_states *sampler,
-				  unsigned shader_id)
+static void *r600_create_dsa_state(struct pipe_context *ctx,
+				   const struct pipe_depth_stencil_alpha_state *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	unsigned i;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 
-	for (i = 0; i < sampler->nview; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->view[i]);
+	if (rstate == NULL) {
+		return NULL;
 	}
 
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)views[i];
-		if (rstate) {
-			rstate->nrstate = 0;
+	rstate->id = R600_PIPE_STATE_DSA;
+	/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
+	/* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
+	 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
+	 * be set if shader use texkill instruction
+	 */
+	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+
+	/* stencil */
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+
+
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 		}
 	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)views[i];
-		if (rstate) {
-			if (rstate->nrstate >= R600_MAX_RSTATE)
-				continue;
-			if (rstate->nrstate) {
-				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
-			}
-			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, shader_id);
-			sampler->view[i] = &rstate->rstate[rstate->nrstate];
-			rstate->nrstate++;
+
+	/* alpha */
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
+		alpha_ref = fui(state->alpha.ref_value);
+	}
+
+	/* misc */
+	db_render_control = 0;
+	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
+		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
+	/* TODO db_render_override depends on query */
+	r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028430_DB_STENCILREFMASK, stencil_ref_mask,
+				0xFFFFFFFF & C_028430_STENCILREF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
+				0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
+	r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
+
+	return rstate;
+}
+
+static void *r600_create_rs_state(struct pipe_context *ctx,
+					const struct pipe_rasterizer_state *state)
+{
+	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
+	struct r600_pipe_state *rstate;
+	unsigned tmp;
+	unsigned prov_vtx = 1, polygon_dual_mode;
+	unsigned clip_rule;
+
+	if (rs == NULL) {
+		return NULL;
+	}
+
+	rstate = &rs->rstate;
+	rs->flatshade = state->flatshade;
+	rs->sprite_coord_enable = state->sprite_coord_enable;
+
+	clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
+	/* offset */
+	rs->offset_units = state->offset_units;
+	rs->offset_scale = state->offset_scale * 12.0f;
+
+	rstate->id = R600_PIPE_STATE_RASTERIZER;
+	if (state->flatshade_first)
+		prov_vtx = 0;
+	tmp = 0x00000001;
+	if (state->sprite_coord_enable) {
+		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
+			S_0286D4_PNT_SPRITE_OVRD_X(2) |
+			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+			S_0286D4_PNT_SPRITE_OVRD_W(1);
+		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 		}
 	}
-	sampler->nview = count;
+	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
+
+	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
+				state->fill_back != PIPE_POLYGON_MODE_FILL);
+	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
+		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+		S_028814_FACE(!state->front_ccw) |
+		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
+		S_028814_POLY_MODE(polygon_dual_mode) |
+		S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
+		S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
+			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	/* point size 12.4 fixed point */
+	tmp = (unsigned)(state->point_size * 8.0);
+	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
+
+	tmp = (unsigned)(state->line_width * 8.0);
+	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
+
+	return rstate;
 }
 
-static void r600_set_ps_sampler_view(struct pipe_context *ctx,
-					unsigned count,
-					struct pipe_sampler_view **views)
+static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	r600_set_sampler_view(ctx, count, views, &rctx->ps_sampler, R600_SHADER_PS);
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	if (state == NULL)
+		return;
+
+	rctx->flatshade = rs->flatshade;
+	rctx->sprite_coord_enable = rs->sprite_coord_enable;
+	rctx->rasterizer = rs;
+
+	rctx->states[rs->rstate.id] = &rs->rstate;
+	r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 }
 
-static void r600_set_vs_sampler_view(struct pipe_context *ctx,
-					unsigned count,
-					struct pipe_sampler_view **views)
+static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	r600_set_sampler_view(ctx, count, views, &rctx->vs_sampler, R600_SHADER_VS);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
+
+	if (rctx->rasterizer == rs) {
+		rctx->rasterizer = NULL;
+	}
+	if (rctx->states[rs->rstate.id] == &rs->rstate) {
+		rctx->states[rs->rstate.id] = NULL;
+	}
+	free(rs);
 }
 
-static void *r600_create_shader_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *state)
+static void *r600_create_sampler_state(struct pipe_context *ctx,
+					const struct pipe_sampler_state *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	int r;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	union util_color uc;
 
-	rstate = r600_new_context_state(pipe_shader_type);
-	rstate->state.shader = *state;
-	r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
-	if (r) {
-		r600_context_state_decref(rstate);
+	if (rstate == NULL) {
 		return NULL;
 	}
+
+	rstate->id = R600_PIPE_STATE_SAMPLER;
+	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
+	r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
+			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
+	/* FIXME LOD it depends on texture base level ... */
+	r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
+			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
+	if (uc.ui) {
+		r600_pipe_state_add_reg(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
+	}
 	return rstate;
 }
 
@@ -208,192 +590,242 @@ static void *r600_create_vertex_elements(struct pipe_context *ctx,
 
 	assert(count < 32);
 	v->count = count;
-	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 	v->refcount = 1;
+	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
 	return v;
 }
 
-static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+				      struct pipe_sampler_view *state)
 {
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+	struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 
-	if (v == NULL)
-		return;
-	if (--v->refcount)
-		return;
-	free(v);
+	pipe_resource_reference(&state->texture, NULL);
+	FREE(resource);
 }
 
-static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
+							struct pipe_resource *texture,
+							const struct pipe_sampler_view *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
+	struct r600_pipe_state *rstate;
+	const struct util_format_description *desc;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
+	unsigned format;
+	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
+	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
+	struct r600_bo *bo[2];
 
-	r600_delete_vertex_element(ctx, rctx->vertex_elements);
-	rctx->vertex_elements = v;
-	if (v) {
-		v->refcount++;
+	if (resource == NULL)
+		return NULL;
+	rstate = &resource->state;
+
+	/* initialize base object */
+	resource->base = *state;
+	resource->base.texture = NULL;
+	pipe_reference(NULL, &texture->reference);
+	resource->base.texture = texture;
+	resource->base.reference.count = 1;
+	resource->base.context = ctx;
+
+	swizzle[0] = state->swizzle_r;
+	swizzle[1] = state->swizzle_g;
+	swizzle[2] = state->swizzle_b;
+	swizzle[3] = state->swizzle_a;
+	format = r600_translate_texformat(state->format,
+					  swizzle,
+					  &word4, &yuv_format);
+	if (format == ~0) {
+		format = 0;
+	}
+	desc = util_format_description(state->format);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", state->format);
+	}
+	tmp = (struct r600_resource_texture*)texture;
+	rbuffer = &tmp->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	/* FIXME depth texture decompression */
+	if (tmp->depth) {
+		r600_texture_depth_flush(ctx, texture);
+		tmp = (struct r600_resource_texture*)texture;
+		rbuffer = &tmp->flushed_depth_texture->resource;
+		bo[0] = rbuffer->bo;
+		bo[1] = rbuffer->bo;
 	}
+	pitch = align(tmp->pitch_in_pixels[0], 8);
+	if (tmp->tiled) {
+		array_mode = tmp->array_mode;
+		tile_type = tmp->tile_type;
+	}
+
+	/* FIXME properly handle first level != 0 */
+	r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
+				S_038000_DIM(r600_tex_dim(texture->target)) |
+				S_038000_TILE_MODE(array_mode) |
+				S_038000_TILE_TYPE(tile_type) |
+				S_038000_PITCH((pitch / 8) - 1) |
+				S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_038004_RESOURCE0_WORD1,
+				S_038004_TEX_HEIGHT(texture->height0 - 1) |
+				S_038004_TEX_DEPTH(texture->depth0 - 1) |
+				S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_038008_RESOURCE0_WORD2,
+				(tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate, R_03800C_RESOURCE0_WORD3,
+				(tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]);
+	r600_pipe_state_add_reg(rstate, R_038010_RESOURCE0_WORD4,
+				word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
+				S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
+				S_038010_REQUEST_SIZE(1) |
+				S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_038014_RESOURCE0_WORD5,
+				S_038014_LAST_LEVEL(state->last_level) |
+				S_038014_BASE_ARRAY(0) |
+				S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
+				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+
+	return &resource->base;
 }
 
-static void r600_bind_rasterizer_state(struct pipe_context *ctx, void *state)
+static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 
-	if (state == NULL)
-		return;
-	rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
-	rctx->rasterizer = r600_context_state_incref(rstate);
+	for (int i = 0; i < count; i++) {
+		if (resource[i]) {
+			r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, i + PIPE_MAX_ATTRIBS);
+		}
+	}
 }
 
-static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
+static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
+					struct pipe_sampler_view **views)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
 
-	if (state == NULL)
-		return;
-	rctx->blend = r600_context_state_decref(rctx->blend);
-	rctx->blend = r600_context_state_incref(rstate);
+	rctx->ps_samplers.views = resource;
+	rctx->ps_samplers.n_views = count;
 
+	for (int i = 0; i < count; i++) {
+		if (resource[i]) {
+			r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
+		}
+	}
 }
 
-static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
+static void r600_bind_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 
 	if (state == NULL)
 		return;
-	rctx->dsa = r600_context_state_decref(rctx->dsa);
-	rctx->dsa = r600_context_state_incref(rstate);
-}
-
-static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
-	rctx->ps_shader = r600_context_state_incref(rstate);
+	rctx->states[rstate->id] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 
-	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
-	rctx->vs_shader = r600_context_state_incref(rstate);
-}
+	rctx->ps_samplers.samplers = states;
+	rctx->ps_samplers.n_samplers = count;
 
-static void r600_bind_sampler_shader(struct pipe_context *ctx,
-				     unsigned count, void **states,
-				     struct r600_shader_sampler_states *sampler, unsigned shader_id)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	unsigned i;
-
-	for (i = 0; i < sampler->nsampler; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->sampler[i]);
-	}
-	for (i = 0; i < sampler->nborder; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->border[i]);
+	for (int i = 0; i < count; i++) {
+		r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
 	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)states[i];
-		if (rstate) {
-			rstate->nrstate = 0;
-		}
-	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)states[i];
-		if (rstate) {
-			if (rstate->nrstate >= R600_MAX_RSTATE)
-				continue;
-			if (rstate->nrstate) {
-				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
-				memcpy(&rstate->rstate[rstate->nrstate+1], &rstate->rstate[1], sizeof(struct radeon_state));
-			}
-			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, shader_id);
-			radeon_state_convert(&rstate->rstate[rstate->nrstate + 1], R600_STATE_SAMPLER_BORDER, i, shader_id);
-			sampler->sampler[i] = &rstate->rstate[rstate->nrstate];
-			sampler->border[i] = &rstate->rstate[rstate->nrstate + 1];
-			rstate->nrstate += 2;
-		}
-	}
-	sampler->nsampler = count;
-	sampler->nborder = count;
 }
 
-static void r600_bind_ps_sampler(struct pipe_context *ctx,
-					unsigned count, void **states)
+static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	r600_bind_sampler_shader(ctx, count, states, &rctx->ps_sampler, R600_SHADER_PS);	
-}
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
 
-static void r600_bind_vs_sampler(struct pipe_context *ctx,
-					unsigned count, void **states)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	r600_bind_sampler_shader(ctx, count, states, &rctx->vs_sampler, R600_SHADER_VS);	
+	for (int i = 0; i < count; i++) {
+		r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
+	}
 }
 
 static void r600_delete_state(struct pipe_context *ctx, void *state)
 {
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 
-	r600_context_state_decref(rstate);
+	if (rctx->states[rstate->id] == rstate) {
+		rctx->states[rstate->id] = NULL;
+	}
+	for (int i = 0; i < rstate->nregs; i++) {
+		r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
+	}
+	free(rstate);
 }
 
-static void r600_set_blend_color(struct pipe_context *ctx,
-					const struct pipe_blend_color *color)
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 
-	rctx->blend_color = *color;
+	if (v == NULL)
+		return;
+	if (--v->refcount)
+		return;
+	free(v);
 }
 
 static void r600_set_clip_state(struct pipe_context *ctx,
 				const struct pipe_clip_state *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 
-	r600_context_state_decref(rctx->clip);
+	if (rstate == NULL)
+		return;
 
-	rstate = r600_new_context_state(pipe_clip_type);
-	rstate->state.clip = *state;
-	rctx->vtbl->ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
-	rctx->clip = rstate;
+	rctx->clip = *state;
+	rstate->id = R600_PIPE_STATE_CLIP;
+	for (int i = 0; i < state->nr; i++) {
+		r600_pipe_state_add_reg(rstate,
+					R_028E20_PA_CL_UCP0_X + i * 4,
+					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_028E24_PA_CL_UCP0_Y + i * 4,
+					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_028E28_PA_CL_UCP0_Z + i * 4,
+					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate,
+					R_028E2C_PA_CL_UCP0_W + i * 4,
+					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
+	}
+	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
+			S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
+			S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
+			S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_CLIP]);
+	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
-					const struct pipe_framebuffer_state *state)
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	int i;
-
-	r600_context_state_decref(rctx->framebuffer);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 
-	rstate = r600_new_context_state(pipe_framebuffer_type);
-	rstate->state.framebuffer = *state;
-	for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
-		pipe_reference(NULL, &state->cbufs[i]->reference);
-	}
-	pipe_reference(NULL, &state->zsbuf->reference);
-	rctx->framebuffer = rstate;
-	for (i = 0; i < state->nr_cbufs; i++) {
-		rctx->vtbl->cb(rctx, &rstate->rstate[i+1], state, i);
-	}
-	if (state->zsbuf) {
-		rctx->vtbl->db(rctx, &rstate->rstate[0], state);
+	r600_delete_vertex_element(ctx, rctx->vertex_elements);
+	rctx->vertex_elements = v;
+	if (v) {
+		v->refcount++;
+//		rctx->vs_rebuild = TRUE;
 	}
-	return;
 }
 
 static void r600_set_polygon_stipple(struct pipe_context *ctx,
@@ -408,55 +840,296 @@ static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask
 static void r600_set_scissor_state(struct pipe_context *ctx,
 					const struct pipe_scissor_state *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tl, br;
 
-	r600_context_state_decref(rctx->scissor);
+	if (rstate == NULL)
+		return;
 
-	rstate = r600_new_context_state(pipe_scissor_type);
-	rstate->state.scissor = *state;
-	rctx->scissor = rstate;
+	rstate->id = R600_PIPE_STATE_SCISSOR;
+	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	r600_pipe_state_add_reg(rstate,
+				R_028210_PA_SC_CLIPRECT_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028214_PA_SC_CLIPRECT_0_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028218_PA_SC_CLIPRECT_1_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_02821C_PA_SC_CLIPRECT_1_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028220_PA_SC_CLIPRECT_2_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028224_PA_SC_CLIPRECT_2_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028228_PA_SC_CLIPRECT_3_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_02822C_PA_SC_CLIPRECT_3_BR, br,
+				0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
+	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
 static void r600_set_stencil_ref(struct pipe_context *ctx,
 				const struct pipe_stencil_ref *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 tmp;
 
-	r600_context_state_decref(rctx->stencil_ref);
+	if (rstate == NULL)
+		return;
 
-	rstate = r600_new_context_state(pipe_stencil_ref_type);
-	rstate->state.stencil_ref = *state;
-	rctx->stencil_ref = rstate;
+	rctx->stencil_ref = *state;
+	rstate->id = R600_PIPE_STATE_STENCIL_REF;
+	tmp = S_028430_STENCILREF(state->ref_value[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_028430_DB_STENCILREFMASK, tmp,
+				~C_028430_STENCILREF, NULL);
+	tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
+	r600_pipe_state_add_reg(rstate,
+				R_028434_DB_STENCILREFMASK_BF, tmp,
+				~C_028434_STENCILREF_BF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
+	rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static void r600_set_vertex_buffers(struct pipe_context *ctx,
-					unsigned count,
-					const struct pipe_vertex_buffer *buffers)
+static void r600_set_viewport_state(struct pipe_context *ctx,
+					const struct pipe_viewport_state *state)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned i;
-	boolean any_user_buffers = FALSE;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 
-	for (i = 0; i < rctx->nvertex_buffer; i++) {
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	if (rstate == NULL)
+		return;
+
+	rctx->viewport = *state;
+	rstate->id = R600_PIPE_STATE_VIEWPORT;
+	r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
+	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
+}
+
+static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state, int cb)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+	struct r600_bo *bo[3];
+
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	bo[0] = rbuffer->bo;
+	bo[1] = rbuffer->bo;
+	bo[2] = rbuffer->bo;
+
+	pitch = rtex->pitch_in_pixels[level] / 8 - 1;
+	slice = rtex->pitch_in_pixels[level] * state->cbufs[cb]->height / 64 - 1;
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_ARRAY_MODE(rtex->array_mode);
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 
+		color_info |= S_0280A0_SOURCE_FORMAT(1);
+
+	r600_pipe_state_add_reg(rstate,
+				R_028040_CB_COLOR0_BASE + cb * 4,
+				(state->cbufs[cb]->offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_0280A0_CB_COLOR0_INFO + cb * 4,
+				color_info, 0xFFFFFFFF, bo[0]);
+	r600_pipe_state_add_reg(rstate,
+				R_028060_CB_COLOR0_SIZE + cb * 4,
+				S_028060_PITCH_TILE_MAX(pitch) |
+				S_028060_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028080_CB_COLOR0_VIEW + cb * 4,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_0280E0_CB_COLOR0_FRAG + cb * 4,
+				r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
+	r600_pipe_state_add_reg(rstate,
+				R_0280C0_CB_COLOR0_TILE + cb * 4,
+				r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
+	r600_pipe_state_add_reg(rstate,
+				R_028100_CB_COLOR0_MASK + cb * 4,
+				0x00000000, 0xFFFFFFFF, NULL);
+}
+
+static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
+			const struct pipe_framebuffer_state *state)
+{
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level;
+	unsigned pitch, slice, format;
+
+	if (state->zsbuf == NULL)
+		return;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tiled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	level = state->zsbuf->level;
+	pitch = rtex->pitch_in_pixels[level] / 8 - 1;
+	slice = rtex->pitch_in_pixels[level] * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+
+	r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
+				(state->zsbuf->offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
+	r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
+				S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
+				S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
+				0xFFFFFFFF, rbuffer->bo);
+	r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
+				(state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
+}
+
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+					const struct pipe_framebuffer_state *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
+	u32 shader_mask, tl, br, shader_control, target_mask;
+
+	if (rstate == NULL)
+		return;
+
+	/* unreference old buffer and reference new one */
+	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
+
+	util_copy_framebuffer_state(&rctx->framebuffer, state);
+	
+	rctx->pframebuffer = &rctx->framebuffer;
+
+	/* build states */
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		r600_cb(rctx, rstate, state, i);
 	}
-	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
-	for (i = 0; i < count; i++) {
-		rctx->vertex_buffer[i].buffer = NULL;
-		if (r600_buffer_is_user_buffer(buffers[i].buffer))
-			any_user_buffers = TRUE;
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	if (state->zsbuf) {
+		r600_db(rctx, rstate, state);
 	}
-	rctx->any_user_vbs = any_user_buffers;
-	rctx->nvertex_buffer = count;
+
+	target_mask = 0x00000000;
+	target_mask = 0xFFFFFFFF;
+	shader_mask = 0;
+	shader_control = 0;
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		target_mask ^= 0xf << (i * 4);
+		shader_mask |= 0xf << (i * 4);
+		shader_control |= 1 << i;
+	}
+	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
+
+	r600_pipe_state_add_reg(rstate,
+				R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
+				0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
+				0xFFFFFFFF, NULL);
+	if (rctx->family >= CHIP_RV770) {
+		r600_pipe_state_add_reg(rstate,
+					R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
+					0xFFFFFFFF, NULL);
+	}
+
+	r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
+				shader_control, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
+				0x00000000, target_mask, NULL);
+	r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
+				shader_mask, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
+				0x01000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
+				0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
+				0x000000FF, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
+				0xFFFFFFFF, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
+				0xFFFFFFFF, 0xFFFFFFFF, NULL);
+
+	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
+	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
 static void r600_set_index_buffer(struct pipe_context *ctx,
 				  const struct pipe_index_buffer *ib)
 {
-	struct r600_context *rctx = r600_context(ctx);
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
 	if (ib) {
 		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
@@ -469,21 +1142,113 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 	/* TODO make this more like a state */
 }
 
-static void r600_set_viewport_state(struct pipe_context *ctx,
-					const struct pipe_viewport_state *state)
+static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+					const struct pipe_vertex_buffer *buffers)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 
-	r600_context_state_decref(rctx->viewport);
+	for (int i = 0; i < rctx->nvertex_buffer; i++) {
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	}
+	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+	for (int i = 0; i < count; i++) {
+		rctx->vertex_buffer[i].buffer = NULL;
+		if (r600_buffer_is_user_buffer(buffers[i].buffer))
+			rctx->any_user_vbs = TRUE;
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	}
+	rctx->nvertex_buffer = count;
+}
 
-	rstate = r600_new_context_state(pipe_viewport_type);
-	rstate->state.viewport = *state;
-	rctx->vtbl->viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
-	rctx->viewport = rstate;
+static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+					struct pipe_resource *buffer)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_resource *rbuffer = (struct r600_resource*)buffer;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		rctx->vs_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->vs_const_buffer,
+					R_028980_ALU_CONST_CACHE_VS_0,
+					r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		rctx->ps_const_buffer.nregs = 0;
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+					ALIGN_DIVUP(buffer->width0 >> 4, 16),
+					0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(&rctx->ps_const_buffer,
+					R_028940_ALU_CONST_CACHE_PS_0,
+					r600_bo_offset(rbuffer->bo) >> 8, 0xFFFFFFFF, rbuffer->bo);
+		r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
+		break;
+	default:
+		R600_ERR("unsupported %d\n", shader);
+		return;
+	}
 }
 
-void r600_init_state_functions(struct r600_context *rctx)
+static void *r600_create_shader_state(struct pipe_context *ctx,
+					const struct pipe_shader_state *state)
+{
+	struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
+	int r;
+
+	r =  r600_pipe_shader_create(ctx, shader, state->tokens);
+	if (r) {
+		return NULL;
+	}
+	return shader;
+}
+
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->ps_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+	/* TODO delete old shader */
+	rctx->vs_shader = (struct r600_pipe_shader *)state;
+}
+
+static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->ps_shader == shader) {
+		rctx->ps_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
+
+	if (rctx->vs_shader == shader) {
+		rctx->vs_shader = NULL;
+	}
+	/* TODO proper delete */
+	free(shader);
+}
+
+void r600_init_state_functions(struct r600_pipe_context *rctx)
 {
 	rctx->context.create_blend_state = r600_create_blend_state;
 	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
@@ -494,30 +1259,23 @@ void r600_init_state_functions(struct r600_context *rctx)
 	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
 	rctx->context.create_vs_state = r600_create_shader_state;
 	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
+	rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
 	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
 	rctx->context.bind_fs_state = r600_bind_ps_shader;
-	rctx->context.bind_rasterizer_state = r600_bind_rasterizer_state;
+	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
 	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
 	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
 	rctx->context.bind_vs_state = r600_bind_vs_shader;
 	rctx->context.delete_blend_state = r600_delete_state;
 	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.delete_fs_state = r600_delete_state;
-	rctx->context.delete_rasterizer_state = r600_delete_state;
+	rctx->context.delete_fs_state = r600_delete_ps_shader;
+	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
 	rctx->context.delete_sampler_state = r600_delete_state;
 	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
-	rctx->context.delete_vs_state = r600_delete_state;
+	rctx->context.delete_vs_state = r600_delete_vs_shader;
 	rctx->context.set_blend_color = r600_set_blend_color;
 	rctx->context.set_clip_state = r600_set_clip_state;
-
-	if (rctx->screen->chip_class == EVERGREEN)
-		rctx->context.set_constant_buffer = eg_set_constant_buffer;
-	else if (rctx->screen->use_mem_constant)
-		rctx->context.set_constant_buffer = r600_set_constant_buffer_mem;
-	else
-		rctx->context.set_constant_buffer = r600_set_constant_buffer_file;
-
+	rctx->context.set_constant_buffer = r600_set_constant_buffer;
 	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
 	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
 	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
@@ -531,169 +1289,291 @@ void r600_init_state_functions(struct r600_context *rctx)
 	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
 }
 
-struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
+void r600_init_config(struct r600_pipe_context *rctx)
 {
-	if (rstate == NULL)
-		return NULL;
-	rstate->refcount++;
-	return rstate;
-}
-
-struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
-{
-	unsigned i;
-
-	if (rstate == NULL)
-		return NULL;
-	if (--rstate->refcount)
-		return NULL;
-	switch (rstate->type) {
-	case pipe_sampler_view_type:
-		pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
-		break;
-	case pipe_framebuffer_type:
-		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
-			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
-		}
-		pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
+	int ps_prio;
+	int vs_prio;
+	int gs_prio;
+	int es_prio;
+	int num_ps_gprs;
+	int num_vs_gprs;
+	int num_gs_gprs;
+	int num_es_gprs;
+	int num_temp_gprs;
+	int num_ps_threads;
+	int num_vs_threads;
+	int num_gs_threads;
+	int num_es_threads;
+	int num_ps_stack_entries;
+	int num_vs_stack_entries;
+	int num_gs_stack_entries;
+	int num_es_stack_entries;
+	enum radeon_family family;
+	struct r600_pipe_state *rstate = &rctx->config;
+	u32 tmp;
+
+	family = r600_get_family(rctx->radeon);
+	ps_prio = 0;
+	vs_prio = 1;
+	gs_prio = 2;
+	es_prio = 3;
+	switch (family) {
+	case CHIP_R600:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
 		break;
-	case pipe_viewport_type:
-	case pipe_depth_type:
-	case pipe_rasterizer_type:
-	case pipe_poly_stipple_type:
-	case pipe_scissor_type:
-	case pipe_clip_type:
-	case pipe_stencil_type:
-	case pipe_alpha_type:
-	case pipe_dsa_type:
-	case pipe_blend_type:
-	case pipe_stencil_ref_type:
-	case pipe_shader_type:
-	case pipe_sampler_type:
+	case CHIP_RV630:
+	case CHIP_RV635:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 40;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
 		break;
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
 	default:
-		R600_ERR("invalid type %d\n", rstate->type);
-		return NULL;
-	}
-	radeon_state_fini(&rstate->rstate[0]);
-	FREE(rstate);
-	return NULL;
-}
-
-static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shader_sampler_states *sampler)
-{
-	int i;
-
-	for (i = 0; i < sampler->nsampler; i++) {
-		if (sampler->sampler[i])
-			radeon_draw_bind(&rctx->draw, sampler->sampler[i]);
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV670:
+		num_ps_gprs = 144;
+		num_vs_gprs = 40;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 136;
+		num_vs_threads = 48;
+		num_gs_threads = 4;
+		num_es_threads = 4;
+		num_ps_stack_entries = 40;
+		num_vs_stack_entries = 40;
+		num_gs_stack_entries = 32;
+		num_es_stack_entries = 16;
+		break;
+	case CHIP_RV770:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 256;
+		num_vs_stack_entries = 256;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV730:
+	case CHIP_RV740:
+		num_ps_gprs = 84;
+		num_vs_gprs = 36;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 188;
+		num_vs_threads = 60;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
+	case CHIP_RV710:
+		num_ps_gprs = 192;
+		num_vs_gprs = 56;
+		num_temp_gprs = 4;
+		num_gs_gprs = 0;
+		num_es_gprs = 0;
+		num_ps_threads = 144;
+		num_vs_threads = 48;
+		num_gs_threads = 0;
+		num_es_threads = 0;
+		num_ps_stack_entries = 128;
+		num_vs_stack_entries = 128;
+		num_gs_stack_entries = 0;
+		num_es_stack_entries = 0;
+		break;
 	}
 
-	for (i = 0; i < sampler->nborder; i++) {
-		if (sampler->border[i])
-			radeon_draw_bind(&rctx->draw, sampler->border[i]);
-	}
+	rstate->id = R600_PIPE_STATE_CONFIG;
 
-	for (i = 0; i < sampler->nview; i++) {
-		if (sampler->view[i])
-			radeon_draw_bind(&rctx->draw, sampler->view[i]);
+	/* SQ_CONFIG */
+	tmp = 0;
+	switch (family) {
+	case CHIP_RV610:
+	case CHIP_RV620:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV710:
+		break;
+	default:
+		tmp |= S_008C00_VC_ENABLE(1);
+		break;
 	}
-}
-
-
-static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct pipe_surface *surf;
-	int i;
-
-	radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
-
-	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		surf = rctx->framebuffer->state.framebuffer.cbufs[i];
-		
-		rtex = (struct r600_resource_texture*)surf->texture;
-		rbuffer = &rtex->resource;
-		/* just need to the bo to the flush list */
-		radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], rbuffer->bo);
-		flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
+	tmp |= S_008C00_DX9_CONSTS(0);
+	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	tmp |= S_008C00_PS_PRIO(ps_prio);
+	tmp |= S_008C00_VS_PRIO(vs_prio);
+	tmp |= S_008C00_GS_PRIO(gs_prio);
+	tmp |= S_008C00_ES_PRIO(es_prio);
+	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_GPR_RESOURCE_MGMT_1 */
+	tmp = 0;
+	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_GPR_RESOURCE_MGMT_2 */
+	tmp = 0;
+	tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_THREAD_RESOURCE_MGMT */
+	tmp = 0;
+	tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_STACK_RESOURCE_MGMT_1 */
+	tmp = 0;
+	tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
+
+	/* SQ_STACK_RESOURCE_MGMT_2 */
+	tmp = 0;
+	tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
+
+	if (family >= CHIP_RV770) {
+		r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
+	} else {
+		r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
+		r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
 	}
-	flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	return radeon_state_pm4(flush);
+	r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
+
+	r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
+	r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
-static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
+void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
 {
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct pipe_surface *surf;
-
-	surf = rctx->framebuffer->state.framebuffer.zsbuf;
-
-	if (!surf)
-		return 0;
-		
-	radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
-	rtex = (struct r600_resource_texture*)surf->texture;
-	rbuffer = &rtex->resource;
-	/* just need to the bo to the flush list */
-	radeon_ws_bo_reference(rscreen->rw, &flush->bo[0], rbuffer->bo);
-	flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-
-	flush->nbo = 1;
-	return radeon_state_pm4(flush);
-}
-
-int r600_context_hw_states(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned i;
-	
-	/* build new states */
-	rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer);
-	rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
-	rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
-	rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
-							       
-	/* setup flushes */
-	setup_db_flush(rctx, &rctx->hw_states.db_flush);
-	setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
-
-	/* bind states */
-	radeon_draw_bind(&rctx->draw, &rctx->config);
-
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
-
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
-
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
-
-	if (rctx->viewport) {
-		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
-	}
-	if (rctx->blend) {
-		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
-	}
-	if (rctx->clip) {
-		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
-	}
-	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
-	}
-	if (rctx->framebuffer->state.framebuffer.zsbuf) {
-		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_pipe_state *rstate;
+	boolean quirk = false;
+
+	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
+		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
+		quirk = true;
+
+	memset(&dsa, 0, sizeof(dsa));
+
+	if (quirk) {
+		dsa.depth.enabled = 1;
+		dsa.depth.func = PIPE_FUNC_LEQUAL;
+		dsa.stencil[0].enabled = 1;
+		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+		dsa.stencil[0].writemask = 0xff;
 	}
 
-	r600_bind_shader_sampler(rctx, &rctx->vs_sampler);
-	r600_bind_shader_sampler(rctx, &rctx->ps_sampler);
-
-	return 0;
+	rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	r600_pipe_state_add_reg(rstate,
+				R_02880C_DB_SHADER_CONTROL,
+				0x0,
+				S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+	r600_pipe_state_add_reg(rstate,
+				R_028D0C_DB_RENDER_CONTROL,
+				S_028D0C_DEPTH_COPY_ENABLE(1) |
+				S_028D0C_STENCIL_COPY_ENABLE(1) |
+				S_028D0C_COPY_CENTROID(1),
+				S_028D0C_DEPTH_COPY_ENABLE(1) |
+				S_028D0C_STENCIL_COPY_ENABLE(1) |
+				S_028D0C_COPY_CENTROID(1), NULL);
+	return rstate;
 }
diff --git a/src/gallium/drivers/r600/r600_state2.c b/src/gallium/drivers/r600/r600_state2.c
deleted file mode 100644
index 86c10a877d..0000000000
--- a/src/gallium/drivers/r600/r600_state2.c
+++ /dev/null
@@ -1,2228 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/* TODO:
- *	- fix mask for depth control & cull for query
- */
-#include <stdio.h>
-#include <errno.h>
-#include <pipe/p_defines.h>
-#include <pipe/p_state.h>
-#include <pipe/p_context.h>
-#include <tgsi/tgsi_scan.h>
-#include <tgsi/tgsi_parse.h>
-#include <tgsi/tgsi_util.h>
-#include <util/u_blitter.h>
-#include <util/u_double_list.h>
-#include <util/u_transfer.h>
-#include <util/u_surface.h>
-#include <util/u_pack_color.h>
-#include <util/u_memory.h>
-#include <util/u_inlines.h>
-#include <pipebuffer/pb_buffer.h>
-#include "r600.h"
-#include "r600d.h"
-#include "r700_sq.h"
-struct radeon_state {
-	unsigned dummy;
-};
-#include "r600_resource.h"
-#include "r600_shader.h"
-
-
-uint32_t r600_translate_texformat(enum pipe_format format,
-				  const unsigned char *swizzle_view, 
-				  uint32_t *word4_p, uint32_t *yuv_format_p);
-
-#include "r600_state_inlines.h"
-
-enum chip_class {
-	R600,
-	R700,
-	EVERGREEN,
-};
-
-enum r600_pipe_state_id {
-	R600_PIPE_STATE_BLEND = 0,
-	R600_PIPE_STATE_BLEND_COLOR,
-	R600_PIPE_STATE_CONFIG,
-	R600_PIPE_STATE_CLIP,
-	R600_PIPE_STATE_SCISSOR,
-	R600_PIPE_STATE_VIEWPORT,
-	R600_PIPE_STATE_RASTERIZER,
-	R600_PIPE_STATE_VGT,
-	R600_PIPE_STATE_FRAMEBUFFER,
-	R600_PIPE_STATE_DSA,
-	R600_PIPE_STATE_STENCIL_REF,
-	R600_PIPE_STATE_PS_SHADER,
-	R600_PIPE_STATE_VS_SHADER,
-	R600_PIPE_STATE_CONSTANT,
-	R600_PIPE_STATE_SAMPLER,
-	R600_PIPE_STATE_RESOURCE,
-	R600_PIPE_NSTATES
-};
-
-struct r600_screen {
-	struct pipe_screen		screen;
-	struct radeon			*radeon;
-	unsigned			chip_class;
-};
-
-struct r600_pipe_sampler_view {
-	struct pipe_sampler_view	base;
-	struct r600_pipe_state		state;
-};
-
-struct r600_pipe_rasterizer {
-	struct r600_pipe_state		rstate;
-	bool				flatshade;
-	unsigned			sprite_coord_enable;
-};
-
-struct r600_pipe_blend {
-	struct r600_pipe_state		rstate;
-	unsigned			cb_target_mask;
-};
-
-struct r600_pipe_shader {
-	struct r600_shader		shader;
-	struct r600_pipe_state		rstate;
-	struct radeon_ws_bo		*bo;
-};
-
-struct r600_vertex_element
-{
-	unsigned			count;
-	unsigned			refcount;
-	struct pipe_vertex_element	elements[32];
-};
-
-struct r600_pipe_context {
-	struct pipe_context		context;
-	struct r600_screen		*screen;
-	struct radeon			*radeon;
-	struct blitter_context		*blitter;
-	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
-	struct r600_context		ctx;
-	struct r600_vertex_element	*vertex_elements;
-	struct pipe_framebuffer_state	framebuffer;
-	struct pipe_index_buffer	index_buffer;
-	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
-	unsigned			nvertex_buffer;
-	unsigned			cb_target_mask;
-	/* for saving when using blitter */
-	struct pipe_stencil_ref		stencil_ref;
-	struct pipe_viewport_state	viewport;
-	struct pipe_clip_state		clip;
-	unsigned			vs_nconst;
-	unsigned			ps_nconst;
-	struct r600_pipe_state		vs_const[256];
-	struct r600_pipe_state		ps_const[256];
-	struct r600_pipe_state		vs_resource[160];
-	struct r600_pipe_state		ps_resource[160];
-	struct r600_pipe_state		config;
-	struct r600_pipe_shader 	*ps_shader;
-	struct r600_pipe_shader 	*vs_shader;
-	/* shader information */
-	bool				ps_rebuild;
-	bool				vs_rebuild;
-	unsigned			sprite_coord_enable;
-	bool				flatshade;
-};
-
-static INLINE u32 S_FIXED(float value, u32 frac_bits)
-{
-	return value * (1 << frac_bits);
-}
-
-/* r600_shader.c */
-static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = &shader->rstate;
-	struct r600_shader *rshader = &shader->shader;
-	unsigned spi_vs_out_id[10];
-	unsigned i, tmp;
-
-	/* clear previous register */
-	rstate->nregs = 0;
-
-	/* so far never got proper semantic id from tgsi */
-	for (i = 0; i < 10; i++) {
-		spi_vs_out_id[i] = 0;
-	}
-	for (i = 0; i < 32; i++) {
-		tmp = i << ((i & 3) * 8);
-		spi_vs_out_id[i / 4] |= tmp;
-	}
-	for (i = 0; i < 10; i++) {
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-					R_028614_SPI_VS_OUT_ID_0 + i * 4,
-					spi_vs_out_id[i], 0xFFFFFFFF, NULL);
-	}
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_0286C4_SPI_VS_OUT_CONFIG,
-			S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
-			0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_028868_SQ_PGM_RESOURCES_VS,
-			S_028868_NUM_GPRS(rshader->bc.ngpr) |
-			S_028868_STACK_SIZE(rshader->bc.nstack),
-			0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_0288A4_SQ_PGM_RESOURCES_FS,
-			0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_0288D0_SQ_PGM_CF_OFFSET_VS,
-			0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_0288DC_SQ_PGM_CF_OFFSET_FS,
-			0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_028858_SQ_PGM_START_VS,
-			0x00000000, 0xFFFFFFFF, shader->bo);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-			R_028894_SQ_PGM_START_FS,
-			0x00000000, 0xFFFFFFFF, shader->bo);
-	rctx->vs_rebuild = false;
-}
-
-static void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = &shader->rstate;
-	struct r600_shader *rshader = &shader->shader;
-	unsigned i, tmp, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z;
-	boolean have_pos = FALSE;
-
-	/* clear previous register */
-	rstate->nregs = 0;
-
-	for (i = 0; i < rshader->ninput; i++) {
-		tmp = S_028644_SEMANTIC(i);
-		tmp |= S_028644_SEL_CENTROID(1);
-		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
-			have_pos = TRUE;
-		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
-		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
-			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
-		}
-		if (rctx->sprite_coord_enable & (1 << i)) {
-			tmp |= S_028644_PT_SPRITE_TEX(1);
-		}
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp, 0xFFFFFFFF, NULL);
-	}
-
-	exports_ps = 0;
-	num_cout = 0;
-	for (i = 0; i < rshader->noutput; i++) {
-		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
-			exports_ps |= 1;
-		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
-			exports_ps |= (1 << (num_cout+1));
-			num_cout++;
-		}
-	}
-	if (!exports_ps) {
-		/* always at least export 1 component per pixel */
-		exports_ps = 2;
-	}
-
-	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
-				S_0286CC_PERSP_GRADIENT_ENA(1);
-	spi_input_z = 0;
-	if (have_pos) {
-		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
-					S_0286CC_BARYC_SAMPLE_CNTL(1);
-		spi_input_z |= 1;
-	}
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D0_SPI_PS_IN_CONTROL_1, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028840_SQ_PGM_START_PS,
-				0x00000000, 0xFFFFFFFF, shader->bo);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028850_SQ_PGM_RESOURCES_PS,
-				S_028868_NUM_GPRS(rshader->bc.ngpr) |
-				S_028868_STACK_SIZE(rshader->bc.nstack),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028854_SQ_PGM_EXPORTS_PS,
-				exports_ps, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_0288CC_SQ_PGM_CF_OFFSET_PS,
-				0x00000000, 0xFFFFFFFF, NULL);
-	rctx->ps_rebuild = false;
-}
-
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_shader *rshader = &shader->shader;
-	void *ptr;
-
-	/* copy new shader */
-	if (shader->bo == NULL) {
-		shader->bo = radeon_ws_bo(rctx->radeon, rshader->bc.ndw * 4, 4096, 0);
-		if (shader->bo == NULL) {
-			return -ENOMEM;
-		}
-		ptr = radeon_ws_bo_map(rctx->radeon, shader->bo, 0, NULL);
-		memcpy(ptr, rshader->bc.bytecode, rshader->bc.ndw * 4);
-		radeon_ws_bo_unmap(rctx->radeon, shader->bo);
-	}
-	/* build state */
-	rshader->flat_shade = rctx->flatshade;
-	switch (rshader->processor_type) {
-	case TGSI_PROCESSOR_VERTEX:
-		r600_pipe_shader_vs(ctx, shader);
-		break;
-	case TGSI_PROCESSOR_FRAGMENT:
-		r600_pipe_shader_ps(ctx, shader);
-		break;
-	default:
-		return -EINVAL;
-	}
-	r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
-	return 0;
-}
-
-static int r600_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rshader)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_shader *shader = &rshader->shader;
-	const struct util_format_description *desc;
-	enum pipe_format resource_format[160];
-	unsigned i, nresources = 0;
-	struct r600_bc *bc = &shader->bc;
-	struct r600_bc_cf *cf;
-	struct r600_bc_vtx *vtx;
-
-	if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
-		return 0;
-	for (i = 0; i < rctx->vertex_elements->count; i++) {
-		resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
-	}
-	radeon_ws_bo_reference(rctx->radeon, &rshader->bo, NULL);
-	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
-		switch (cf->inst) {
-		case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-		case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
-			LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
-				desc = util_format_description(resource_format[vtx->buffer_id]);
-				if (desc == NULL) {
-					R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
-					return -EINVAL;
-				}
-				vtx->dst_sel_x = desc->swizzle[0];
-				vtx->dst_sel_y = desc->swizzle[1];
-				vtx->dst_sel_z = desc->swizzle[2];
-				vtx->dst_sel_w = desc->swizzle[3];
-			}
-			break;
-		default:
-			break;
-		}
-	}
-	return r600_bc_build(&shader->bc);
-}
-
-static int r600_pipe_shader_update2(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	int r;
-
-	if (shader == NULL)
-		return -EINVAL;
-	if (shader->bo) {
-		switch (shader->shader.processor_type) {
-		case TGSI_PROCESSOR_VERTEX:
-			if (!rctx->vs_rebuild)
-				return 0;
-			break;
-		case TGSI_PROCESSOR_FRAGMENT:
-			if (!rctx->ps_rebuild)
-				return 0;
-			break;
-		default:
-			return -EINVAL;
-		}
-	}
-	/* there should be enough input */
-	if (rctx->vertex_elements->count < shader->shader.bc.nresource) {
-		R600_ERR("%d resources provided, expecting %d\n",
-			rctx->vertex_elements->count, shader->shader.bc.nresource);
-		return -EINVAL;
-	}
-	r = r600_shader_update(ctx, shader);
-	if (r)
-		return r;
-	return r600_pipe_shader(ctx, shader);
-}
-
-int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader);
-static int r600_pipe_shader_create2(struct pipe_context *ctx, struct r600_pipe_shader *shader, const struct tgsi_token *tokens)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	int r;
-
-//fprintf(stderr, "--------------------------------------------------------------\n");
-//tgsi_dump(tokens, 0);
-	shader->shader.family = r600_get_family(rctx->radeon);
-	r = r600_shader_from_tgsi(tokens, &shader->shader);
-	if (r) {
-		R600_ERR("translation from TGSI failed !\n");
-		return r;
-	}
-	r = r600_bc_build(&shader->shader.bc);
-	if (r) {
-		R600_ERR("building bytecode failed !\n");
-		return r;
-	}
-//fprintf(stderr, "______________________________________________________________\n");
-	return 0;
-}
-/* r600_shader.c END */
-
-static const char* r600_get_vendor(struct pipe_screen* pscreen)
-{
-	return "X.Org";
-}
-
-static const char* r600_get_name(struct pipe_screen* pscreen)
-{
-	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
-	enum radeon_family family = r600_get_family(rscreen->radeon);
-
-	if (family >= CHIP_R600 && family < CHIP_RV770)
-		return "R600 (HD2XXX,HD3XXX)";
-	else
-		return "R700 (HD4XXX)";
-}
-
-static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
-{
-	switch (param) {
-	/* Supported features (boolean caps). */
-	case PIPE_CAP_NPOT_TEXTURES:
-	case PIPE_CAP_TWO_SIDED_STENCIL:
-	case PIPE_CAP_GLSL:
-	case PIPE_CAP_DUAL_SOURCE_BLEND:
-	case PIPE_CAP_ANISOTROPIC_FILTER:
-	case PIPE_CAP_POINT_SPRITE:
-	case PIPE_CAP_OCCLUSION_QUERY:
-	case PIPE_CAP_TEXTURE_SHADOW_MAP:
-	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
-	case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
-	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
-	case PIPE_CAP_SM3:
-	case PIPE_CAP_TEXTURE_SWIZZLE:
-	case PIPE_CAP_INDEP_BLEND_ENABLE:
-	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
-	case PIPE_CAP_DEPTH_CLAMP:
-		return 1;
-
-	/* Unsupported features (boolean caps). */
-	case PIPE_CAP_TIMER_QUERY:
-	case PIPE_CAP_STREAM_OUTPUT:
-	case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
-		return 0;
-
-	/* Texturing. */
-	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
-	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
-	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-		return 14;
-	case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
-		/* FIXME allow this once infrastructure is there */
-		return 0;
-	case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
-	case PIPE_CAP_MAX_COMBINED_SAMPLERS:
-		return 16;
-
-	/* Render targets. */
-	case PIPE_CAP_MAX_RENDER_TARGETS:
-		/* FIXME some r6xx are buggy and can only do 4 */
-		return 8;
-
-	/* Fragment coordinate conventions. */
-	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
-		return 1;
-	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
-		return 0;
-
-	default:
-		R600_ERR("r600: unknown param %d\n", param);
-		return 0;
-	}
-}
-
-static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
-{
-	switch (param) {
-	case PIPE_CAP_MAX_LINE_WIDTH:
-	case PIPE_CAP_MAX_LINE_WIDTH_AA:
-	case PIPE_CAP_MAX_POINT_WIDTH:
-	case PIPE_CAP_MAX_POINT_WIDTH_AA:
-		return 8192.0f;
-	case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
-		return 16.0f;
-	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
-		return 16.0f;
-	default:
-		R600_ERR("r600: unsupported paramf %d\n", param);
-		return 0.0f;
-	}
-}
-
-static boolean r600_is_format_supported(struct pipe_screen* screen,
-					enum pipe_format format,
-					enum pipe_texture_target target,
-					unsigned sample_count,
-					unsigned usage,
-					unsigned geom_flags)
-{
-	unsigned retval = 0;
-	if (target >= PIPE_MAX_TEXTURE_TYPES) {
-		R600_ERR("r600: unsupported texture type %d\n", target);
-		return FALSE;
-	}
-
-	/* Multisample */
-	if (sample_count > 1)
-		return FALSE;
-
-	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
-	    r600_is_sampler_format_supported(format)) {
-		retval |= PIPE_BIND_SAMPLER_VIEW;
-	}
-
-	if ((usage & (PIPE_BIND_RENDER_TARGET |
-                  PIPE_BIND_DISPLAY_TARGET |
-                  PIPE_BIND_SCANOUT |
-                  PIPE_BIND_SHARED)) &&
-	    r600_is_colorbuffer_format_supported(format)) {
-		retval |= usage &
-			(PIPE_BIND_RENDER_TARGET |
-			 PIPE_BIND_DISPLAY_TARGET |
-			 PIPE_BIND_SCANOUT |
-			 PIPE_BIND_SHARED);
-	}
-
-	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-	    r600_is_zs_format_supported(format)) {
-		retval |= PIPE_BIND_DEPTH_STENCIL;
-	}
-
-	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
-	    r600_is_vertex_format_supported(format))
-		retval |= PIPE_BIND_VERTEX_BUFFER;
-
-	if (usage & PIPE_BIND_TRANSFER_READ)
-		retval |= PIPE_BIND_TRANSFER_READ;
-	if (usage & PIPE_BIND_TRANSFER_WRITE)
-		retval |= PIPE_BIND_TRANSFER_WRITE;
-
-	return retval == usage;
-}
-
-static void r600_destroy_screen(struct pipe_screen* pscreen)
-{
-	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
-
-	if (rscreen == NULL)
-		return;
-	FREE(rscreen);
-}
-
-struct r600_drawl {
-	struct pipe_context	*ctx;
-	unsigned		mode;
-	unsigned		start;
-	unsigned		count;
-	unsigned		index_size;
-	struct pipe_resource	*index_buffer;
-};
-
-int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
-static void r600_draw_common(struct r600_drawl *draw)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)draw->ctx;
-	struct r600_pipe_state *rstate;
-	struct r600_resource *rbuffer;
-	unsigned i, j, offset, format, prim;
-	u32 vgt_dma_index_type, vgt_draw_initiator, mask;
-	struct pipe_vertex_buffer *vertex_buffer;
-	struct r600_draw rdraw;
-	struct r600_pipe_state vgt;
-
-	switch (draw->index_size) {
-	case 2:
-		vgt_draw_initiator = 0;
-		vgt_dma_index_type = 0;
-		break;
-	case 4:
-		vgt_draw_initiator = 0;
-		vgt_dma_index_type = 1;
-		break;
-	case 0:
-		vgt_draw_initiator = 2;
-		vgt_dma_index_type = 0;
-		break;
-	default:
-		R600_ERR("unsupported index size %d\n", draw->index_size);
-		return;
-	}
-	if (r600_conv_pipe_prim(draw->mode, &prim))
-		return;
-
-	/* rebuild vertex shader if input format changed */
-	if (r600_pipe_shader_update2(&rctx->context, rctx->vs_shader))
-		return;
-	if (r600_pipe_shader_update2(&rctx->context, rctx->ps_shader))
-		return;
-
-	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
-		rstate = &rctx->vs_resource[i];
-		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		vertex_buffer = &rctx->vertex_buffer[j];
-		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
-		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
-		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		rstate->id = R600_PIPE_STATE_RESOURCE;
-		rstate->nregs = 0;
-
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0, offset, 0xFFFFFFFF, rbuffer->bo);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1, rbuffer->size - offset - 1, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE,
-					R_038008_RESOURCE0_WORD2,
-					S_038008_STRIDE(vertex_buffer->stride) |
-					S_038008_DATA_FORMAT(format),
-					0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6, 0xC0000000, 0xFFFFFFFF, NULL);
-		r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, i);
-	}
-
-	mask = 0;
-	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
-		mask |= (0xF << (i * 4));
-	}
-
-	vgt.id = R600_PIPE_STATE_VGT;
-	vgt.nregs = 0;
-	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONFIG, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028408_VGT_INDX_OFFSET, draw->start, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(&vgt, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
-	r600_context_pipe_state_set(&rctx->ctx, &vgt);
-
-	rdraw.vgt_num_indices = draw->count;
-	rdraw.vgt_num_instances = 1;
-	rdraw.vgt_index_type = vgt_dma_index_type;
-	rdraw.vgt_draw_initiator = vgt_draw_initiator;
-	rdraw.indices = NULL;
-	if (draw->index_buffer) {
-		rbuffer = (struct r600_resource*)draw->index_buffer;
-		rdraw.indices = rbuffer->bo;
-	}
-	r600_context_draw(&rctx->ctx, &rdraw);
-}
-
-static void r600_draw_vbo2(struct pipe_context *ctx, const struct pipe_draw_info *info)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_drawl draw;
-
-	assert(info->index_bias == 0);
-
-	draw.ctx = ctx;
-	draw.mode = info->mode;
-	draw.start = info->start;
-	draw.count = info->count;
-	if (info->indexed && rctx->index_buffer.buffer) {
-		draw.index_size = rctx->index_buffer.index_size;
-		draw.index_buffer = rctx->index_buffer.buffer;
-		assert(rctx->index_buffer.offset %
-				rctx->index_buffer.index_size == 0);
-		draw.start += rctx->index_buffer.offset /
-			rctx->index_buffer.index_size;
-	} else {
-		draw.index_size = 0;
-		draw.index_buffer = NULL;
-	}
-	r600_draw_common(&draw);
-}
-
-static void r600_flush2(struct pipe_context *ctx, unsigned flags,
-			struct pipe_fence_handle **fence)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-#if 0
-	static int dc = 0;
-	char dname[256];
-#endif
-
-	if (!rctx->ctx.pm4_cdwords)
-		return;
-
-#if 0
-	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 2) {
-		r600_context_dump_bof(&rctx->ctx, dname);
-		R600_ERR("dumped %s\n", dname);
-	}
-	dc++;
-#endif
-	r600_context_flush(&rctx->ctx);
-}
-
-static void r600_destroy_context(struct pipe_context *context)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)context;
-
-	r600_context_fini(&rctx->ctx);
-	for (int i = 0; i < R600_PIPE_NSTATES; i++) {
-		free(rctx->states[i]);
-	}
-	FREE(rctx);
-}
-
-static void r600_blitter_save_states(struct pipe_context *ctx)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
-	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);
-	if (rctx->states[R600_PIPE_STATE_STENCIL_REF]) {
-		util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
-	}
-	util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
-	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
-	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
-	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
-	if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
-		util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
-	}
-	if (rctx->states[R600_PIPE_STATE_CLIP]) {
-		util_blitter_save_clip(rctx->blitter, &rctx->clip);
-	}
-	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer, rctx->vertex_buffer);
-
-	rctx->vertex_elements = NULL;
-
-	/* TODO queries */
-}
-
-static void r600_clear(struct pipe_context *ctx, unsigned buffers,
-			const float *rgba, double depth, unsigned stencil)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_clear(rctx->blitter, fb->width, fb->height,
-				fb->nr_cbufs, buffers, rgba, depth,
-				stencil);
-}
-
-static void r600_clear_render_target(struct pipe_context *ctx,
-				     struct pipe_surface *dst,
-				     const float *rgba,
-				     unsigned dstx, unsigned dsty,
-				     unsigned width, unsigned height)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
-
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
-					 dstx, dsty, width, height);
-}
-
-static void r600_clear_depth_stencil(struct pipe_context *ctx,
-				     struct pipe_surface *dst,
-				     unsigned clear_flags,
-				     double depth,
-				     unsigned stencil,
-				     unsigned dstx, unsigned dsty,
-				     unsigned width, unsigned height)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
-
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
-					 dstx, dsty, width, height);
-}
-
-
-static void r600_resource_copy_region(struct pipe_context *ctx,
-				      struct pipe_resource *dst,
-				      struct pipe_subresource subdst,
-				      unsigned dstx, unsigned dsty, unsigned dstz,
-				      struct pipe_resource *src,
-				      struct pipe_subresource subsrc,
-				      unsigned srcx, unsigned srcy, unsigned srcz,
-				      unsigned width, unsigned height)
-{
-	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
-				  src, subsrc, srcx, srcy, srcz, width, height);
-}
-
-static void r600_init_blit_functions2(struct r600_pipe_context *rctx)
-{
-	rctx->context.clear = r600_clear;
-	rctx->context.clear_render_target = r600_clear_render_target;
-	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
-	rctx->context.resource_copy_region = r600_resource_copy_region;
-}
-
-static void r600_init_context_resource_functions2(struct r600_pipe_context *r600)
-{
-	r600->context.get_transfer = u_get_transfer_vtbl;
-	r600->context.transfer_map = u_transfer_map_vtbl;
-	r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
-	r600->context.transfer_unmap = u_transfer_unmap_vtbl;
-	r600->context.transfer_destroy = u_transfer_destroy_vtbl;
-	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
-	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
-}
-
-static void r600_set_blend_color(struct pipe_context *ctx,
-					const struct pipe_blend_color *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-
-	if (rstate == NULL)
-		return;
-
-	rstate->id = R600_PIPE_STATE_BLEND_COLOR;
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
-	free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
-	rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void *r600_create_blend_state(struct pipe_context *ctx,
-					const struct pipe_blend_state *state)
-{
-	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
-	struct r600_pipe_state *rstate;
-	u32 color_control, target_mask;
-
-	if (blend == NULL) {
-		return NULL;
-	}
-	rstate = &blend->rstate;
-
-	rstate->id = R600_PIPE_STATE_BLEND;
-
-	target_mask = 0;
-	color_control = S_028808_PER_MRT_BLEND(1);
-	if (state->logicop_enable) {
-		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
-	} else {
-		color_control |= (0xcc << 16);
-	}
-	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
-	if (state->independent_blend_enable) {
-		for (int i = 0; i < 8; i++) {
-			if (state->rt[i].blend_enable) {
-				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
-			}
-			target_mask |= (state->rt[i].colormask << (4 * i));
-		}
-	} else {
-		for (int i = 0; i < 8; i++) {
-			if (state->rt[0].blend_enable) {
-				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
-			}
-			target_mask |= (state->rt[0].colormask << (4 * i));
-		}
-	}
-	blend->cb_target_mask = target_mask;
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028808_CB_COLOR_CONTROL,
-				color_control, 0xFFFFFFFF, NULL);
-
-	for (int i = 0; i < 8; i++) {
-		unsigned eqRGB = state->rt[i].rgb_func;
-		unsigned srcRGB = state->rt[i].rgb_src_factor;
-		unsigned dstRGB = state->rt[i].rgb_dst_factor;
-		
-		unsigned eqA = state->rt[i].alpha_func;
-		unsigned srcA = state->rt[i].alpha_src_factor;
-		unsigned dstA = state->rt[i].alpha_dst_factor;
-		uint32_t bc = 0;
-
-		if (!state->rt[i].blend_enable)
-			continue;
-
-		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
-		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
-		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
-
-		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
-			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
-			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
-			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
-			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
-		}
-
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
-		if (i == 0) {
-			r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
-		}
-	}
-	return rstate;
-}
-
-static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
-	struct r600_pipe_state *rstate;
-
-	if (state == NULL)
-		return;
-	rstate = &blend->rstate;
-	rctx->states[rstate->id] = rstate;
-	rctx->cb_target_mask = blend->cb_target_mask;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void *r600_create_dsa_state(struct pipe_context *ctx,
-				   const struct pipe_depth_stencil_alpha_state *state)
-{
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
-	unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
-
-	if (rstate == NULL) {
-		return NULL;
-	}
-
-	rstate->id = R600_PIPE_STATE_DSA;
-	/* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
-	/* db_shader_control is 0xFFFFFFBE as Z_EXPORT_ENABLE (bit 0) will be
-	 * set by fragment shader if it export Z and KILL_ENABLE (bit 6) will
-	 * be set if shader use texkill instruction
-	 */
-	db_shader_control = 0x210;
-	stencil_ref_mask = 0;
-	stencil_ref_mask_bf = 0;
-	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
-		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
-		S_028800_ZFUNC(state->depth.func);
-
-	/* stencil */
-	if (state->stencil[0].enabled) {
-		db_depth_control |= S_028800_STENCIL_ENABLE(1);
-		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
-		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
-		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
-		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-
-
-		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
-			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
-		if (state->stencil[1].enabled) {
-			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
-			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
-			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
-			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
-			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
-			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
-				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
-		}
-	}
-
-	/* alpha */
-	alpha_test_control = 0;
-	alpha_ref = 0;
-	if (state->alpha.enabled) {
-		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
-		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
-		alpha_ref = fui(state->alpha.ref_value);
-	}
-
-	/* misc */
-	db_render_control = 0;
-	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
-	/* TODO db_render_override depends on query */
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028430_DB_STENCILREFMASK, stencil_ref_mask,
-				0xFFFFFFFF & C_028430_STENCILREF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
-				0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBE, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
-
-	return rstate;
-}
-
-static void *r600_create_rs_state(struct pipe_context *ctx,
-					const struct pipe_rasterizer_state *state)
-{
-	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
-	struct r600_pipe_state *rstate;
-	float offset_units = 0, offset_scale = 0;
-	unsigned offset_db_fmt_cntl = 0;
-	unsigned tmp;
-	unsigned prov_vtx = 1;
-
-	if (rs == NULL) {
-		return NULL;
-	}
-
-	rstate = &rs->rstate;
-	rs->flatshade = state->flatshade;
-	rs->sprite_coord_enable = state->sprite_coord_enable;
-
-	rstate->id = R600_PIPE_STATE_RASTERIZER;
-	if (state->flatshade_first)
-		prov_vtx = 0;
-	tmp = 0x00000001;
-	if (state->sprite_coord_enable) {
-		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
-			S_0286D4_PNT_SPRITE_OVRD_X(2) |
-			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
-			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
-			S_0286D4_PNT_SPRITE_OVRD_W(1);
-		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
-			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
-		}
-	}
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028814_PA_SU_SC_MODE_CNTL,
-		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
-		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
-		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-		S_028814_FACE(!state->front_ccw) |
-		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02881C_PA_CL_VS_OUT_CNTL,
-			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
-			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	/* point size 12.4 fixed point */
-	tmp = (unsigned)(state->point_size * 8.0);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units), 0xFFFFFFFF, NULL);
-	return rstate;
-}
-
-static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	if (state == NULL)
-		return;
-
-	if (rctx->flatshade != rs->flatshade) {
-		rctx->ps_rebuild = true;
-	}
-	if (rctx->sprite_coord_enable != rs->sprite_coord_enable) {
-		rctx->ps_rebuild = true;
-	}
-	rctx->flatshade = rs->flatshade;
-	rctx->sprite_coord_enable = rs->sprite_coord_enable;
-
-	rctx->states[rs->rstate.id] = &rs->rstate;
-	r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
-}
-
-static void r600_delete_rs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
-
-	if (rctx->states[rs->rstate.id] == &rs->rstate) {
-		rctx->states[rs->rstate.id] = NULL;
-	}
-	free(rs);
-}
-
-static void *r600_create_sampler_state(struct pipe_context *ctx,
-					const struct pipe_sampler_state *state)
-{
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-	union util_color uc;
-
-	if (rstate == NULL) {
-		return NULL;
-	}
-
-	rstate->id = R600_PIPE_STATE_SAMPLER;
-	util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
-			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
-			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
-			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
-			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
-			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
-			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
-			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
-			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
-	/* FIXME LOD it depends on texture base level ... */
-	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
-			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
-			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
-			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_SAMPLER, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
-	if (uc.ui) {
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
-	}
-	return rstate;
-}
-
-static void *r600_create_vertex_elements(struct pipe_context *ctx,
-				unsigned count,
-				const struct pipe_vertex_element *elements)
-{
-	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
-
-	assert(count < 32);
-	v->count = count;
-	v->refcount = 1;
-	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
-	return v;
-}
-
-static void r600_sampler_view_destroy(struct pipe_context *ctx,
-				      struct pipe_sampler_view *state)
-{
-	struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
-
-	pipe_resource_reference(&state->texture, NULL);
-	FREE(resource);
-}
-
-static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
-							struct pipe_resource *texture,
-							const struct pipe_sampler_view *state)
-{
-	struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
-	struct r600_pipe_state *rstate;
-	const struct util_format_description *desc;
-	struct r600_resource_texture *tmp;
-	struct r600_resource *rbuffer;
-	unsigned format;
-	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
-	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
-	struct radeon_ws_bo *bo[2];
-
-	if (resource == NULL)
-		return NULL;
-	rstate = &resource->state;
-
-	/* initialize base object */
-	resource->base = *state;
-	resource->base.texture = NULL;
-	pipe_reference(NULL, &texture->reference);
-	resource->base.texture = texture;
-	resource->base.reference.count = 1;
-	resource->base.context = ctx;
-
-	swizzle[0] = state->swizzle_r;
-	swizzle[1] = state->swizzle_g;
-	swizzle[2] = state->swizzle_b;
-	swizzle[3] = state->swizzle_a;
-	format = r600_translate_texformat(texture->format,
-					  swizzle,
-					  &word4, &yuv_format);
-	if (format == ~0) {
-		format = 0;
-	}
-	desc = util_format_description(texture->format);
-	if (desc == NULL) {
-		R600_ERR("unknow format %d\n", texture->format);
-	}
-	tmp = (struct r600_resource_texture*)texture;
-	rbuffer = &tmp->resource;
-	bo[0] = rbuffer->bo;
-	bo[1] = rbuffer->bo;
-	/* FIXME depth texture decompression */
-	if (tmp->depth) {
-#if 0
-		r = r600_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		bo[0] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-		bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
-#endif
-	}
-	pitch = (tmp->pitch[0] / tmp->bpt);
-	pitch = (pitch + 0x7) & ~0x7;
-
-	/* FIXME properly handle first level != 0 */
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,
-				S_038000_DIM(r600_tex_dim(texture->target)) |
-				S_038000_TILE_MODE(array_mode) |
-				S_038000_TILE_TYPE(tile_type) |
-				S_038000_PITCH((pitch / 8) - 1) |
-				S_038000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038004_RESOURCE0_WORD1,
-				S_038004_TEX_HEIGHT(texture->height0 - 1) |
-				S_038004_TEX_DEPTH(texture->depth0 - 1) |
-				S_038004_DATA_FORMAT(format), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038008_RESOURCE0_WORD2,
-				tmp->offset[0] >> 8, 0xFFFFFFFF, bo[0]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_03800C_RESOURCE0_WORD3,
-				tmp->offset[1] >> 8, 0xFFFFFFFF, bo[1]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038010_RESOURCE0_WORD4,
-				word4 | S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
-				S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
-				S_038010_REQUEST_SIZE(1) |
-				S_038010_BASE_LEVEL(state->first_level), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038014_RESOURCE0_WORD5,
-				S_038014_LAST_LEVEL(state->last_level) |
-				S_038014_BASE_ARRAY(0) |
-				S_038014_LAST_ARRAY(0), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038018_RESOURCE0_WORD6,
-				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
-
-	return &resource->base;
-}
-
-static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
-					struct pipe_sampler_view **views)
-{
-	/* TODO */
-	assert(1);
-}
-
-static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
-					struct pipe_sampler_view **views)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
-
-	for (int i = 0; i < count; i++) {
-		if (resource[i]) {
-			r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, i);
-		}
-	}
-}
-
-static void r600_bind_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
-
-	if (state == NULL)
-		return;
-	rctx->states[rstate->id] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
-
-	for (int i = 0; i < count; i++) {
-		r600_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i);
-	}
-}
-
-static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state **rstates = (struct r600_pipe_state **)states;
-
-	/* TODO implement */
-	for (int i = 0; i < count; i++) {
-		r600_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i);
-	}
-}
-
-static void r600_delete_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
-
-	if (rctx->states[rstate->id] == rstate) {
-		rctx->states[rstate->id] = NULL;
-	}
-	for (int i = 0; i < rstate->nregs; i++) {
-		radeon_ws_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
-	}
-	free(rstate);
-}
-
-static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
-{
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
-
-	if (v == NULL)
-		return;
-	if (--v->refcount)
-		return;
-	free(v);
-}
-
-static void r600_set_clip_state(struct pipe_context *ctx,
-				const struct pipe_clip_state *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-
-	if (rstate == NULL)
-		return;
-
-	rctx->clip = *state;
-	rstate->id = R600_PIPE_STATE_CLIP;
-	for (int i = 0; i < state->nr; i++) {
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-					R_028E20_PA_CL_UCP0_X + i * 4,
-					fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-					R_028E24_PA_CL_UCP0_Y + i * 4,
-					fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-					R_028E28_PA_CL_UCP0_Z + i * 4,
-					fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-					R_028E2C_PA_CL_UCP0_W + i * 4,
-					fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
-	}
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028810_PA_CL_CLIP_CNTL,
-			S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
-			S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
-			S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
-
-	free(rctx->states[R600_PIPE_STATE_CLIP]);
-	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
-
-	r600_delete_vertex_element(ctx, rctx->vertex_elements);
-	rctx->vertex_elements = v;
-	if (v) {
-		v->refcount++;
-		rctx->vs_rebuild = true;
-	}
-}
-
-static void r600_set_polygon_stipple(struct pipe_context *ctx,
-					 const struct pipe_poly_stipple *state)
-{
-}
-
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
-{
-}
-
-static void r600_set_scissor_state(struct pipe_context *ctx,
-					const struct pipe_scissor_state *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-	u32 tl, br;
-
-	if (rstate == NULL)
-		return;
-
-	rstate->id = R600_PIPE_STATE_SCISSOR;
-	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
-	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028210_PA_SC_CLIPRECT_0_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028214_PA_SC_CLIPRECT_0_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028218_PA_SC_CLIPRECT_1_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_02821C_PA_SC_CLIPRECT_1_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028220_PA_SC_CLIPRECT_2_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028224_PA_SC_CLIPRECT_2_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028228_PA_SC_CLIPRECT_3_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_02822C_PA_SC_CLIPRECT_3_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_02820C_PA_SC_CLIPRECT_RULE, 0x0000FFFF,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
-				0xFFFFFFFF, NULL);
-
-	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
-	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_set_stencil_ref(struct pipe_context *ctx,
-				const struct pipe_stencil_ref *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-	u32 tmp;
-
-	if (rstate == NULL)
-		return;
-
-	rctx->stencil_ref = *state;
-	rstate->id = R600_PIPE_STATE_STENCIL_REF;
-	tmp = S_028430_STENCILREF(state->ref_value[0]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028430_DB_STENCILREFMASK, tmp,
-				~C_028430_STENCILREF, NULL);
-	tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028434_DB_STENCILREFMASK_BF, tmp,
-				~C_028434_STENCILREF_BF, NULL);
-
-	free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
-	rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_set_viewport_state(struct pipe_context *ctx,
-					const struct pipe_viewport_state *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-
-	if (rstate == NULL)
-		return;
-
-	rctx->viewport = *state;
-	rstate->id = R600_PIPE_STATE_VIEWPORT;
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
-
-	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
-	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
-			const struct pipe_framebuffer_state *state, int cb)
-{
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-	struct radeon_ws_bo *bo[3];
-
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	bo[0] = rbuffer->bo;
-	bo[1] = rbuffer->bo;
-	bo[2] = rbuffer->bo;
-
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028040_CB_COLOR0_BASE + cb * 4,
-				state->cbufs[cb]->offset >> 8, 0xFFFFFFFF, bo[0]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_0280A0_CB_COLOR0_INFO + cb * 4,
-				color_info, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028060_CB_COLOR0_SIZE + cb * 4,
-				S_028060_PITCH_TILE_MAX(pitch) |
-				S_028060_SLICE_TILE_MAX(slice),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028080_CB_COLOR0_VIEW + cb * 4,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_0280E0_CB_COLOR0_FRAG + cb * 4,
-				0x00000000, 0xFFFFFFFF, bo[1]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_0280C0_CB_COLOR0_TILE + cb * 4,
-				0x00000000, 0xFFFFFFFF, bo[2]);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028100_CB_COLOR0_MASK + cb * 4,
-				0x00000000, 0xFFFFFFFF, NULL);
-}
-
-static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
-			const struct pipe_framebuffer_state *state)
-{
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	if (state->zsbuf == NULL)
-		return;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02800C_DB_DEPTH_BASE,
-				state->zsbuf->offset >> 8, 0xFFFFFFFF, rbuffer->bo);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028000_DB_DEPTH_SIZE,
-				S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028010_DB_DEPTH_INFO,
-				S_028010_ARRAY_MODE(rtex->array_mode) | S_028010_FORMAT(format),
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028D34_DB_PREFETCH_LIMIT,
-				(state->zsbuf->height / 8) - 1, 0xFFFFFFFF, NULL);
-}
-
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
-					const struct pipe_framebuffer_state *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
-	u32 shader_mask, tl, br, shader_control, target_mask;
-
-	if (rstate == NULL)
-		return;
-
-	/* unreference old buffer and reference new one */
-	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
-	for (int i = 0; i < rctx->framebuffer.nr_cbufs; i++) {
-		pipe_surface_reference(&rctx->framebuffer.cbufs[i], state->cbufs[i]);
-	}
-	pipe_surface_reference(&rctx->framebuffer.zsbuf, state->zsbuf);
-	rctx->framebuffer = *state;
-
-	/* build states */
-	for (int i = 0; i < state->nr_cbufs; i++) {
-		r600_cb(rctx, rstate, state, i);
-	}
-	if (state->zsbuf) {
-		r600_db(rctx, rstate, state);
-	}
-
-	target_mask = 0x00000000;
-	target_mask = 0xFFFFFFFF;
-	shader_mask = 0;
-	shader_control = 0;
-	for (int i = 0; i < state->nr_cbufs; i++) {
-		target_mask ^= 0xf << (i * 4);
-		shader_mask |= 0xf << (i * 4);
-		shader_control |= 1 << i;
-	}
-	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
-	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
-				0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT,
-				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
-				0xFFFFFFFF, NULL);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0287A0_CB_SHADER_CONTROL,
-				shader_control, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028238_CB_TARGET_MASK,
-				0x00000000, target_mask, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02823C_CB_SHADER_MASK,
-				shader_mask, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C04_PA_SC_AA_CONFIG,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C30_CB_CLRCMP_CONTROL,
-				0x01000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C34_CB_CLRCMP_SRC,
-				0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C38_CB_CLRCMP_DST,
-				0x000000FF, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C3C_CB_CLRCMP_MSK,
-				0xFFFFFFFF, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028C48_PA_SC_AA_MASK,
-				0xFFFFFFFF, 0xFFFFFFFF, NULL);
-
-	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
-	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static void r600_set_index_buffer(struct pipe_context *ctx,
-				  const struct pipe_index_buffer *ib)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	if (ib) {
-		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
-		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
-	} else {
-		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
-		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
-	}
-
-	/* TODO make this more like a state */
-}
-
-static void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
-					const struct pipe_vertex_buffer *buffers)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	for (int i = 0; i < rctx->nvertex_buffer; i++) {
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
-	}
-	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
-	for (int i = 0; i < count; i++) {
-		rctx->vertex_buffer[i].buffer = NULL;
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
-	}
-	rctx->nvertex_buffer = count;
-}
-
-static void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
-					struct pipe_resource *buffer)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_state *rstate;
-	struct pipe_transfer *transfer;
-	unsigned *nconst = NULL;
-	u32 *ptr, offset;
-
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		rstate = rctx->vs_const;
-		nconst = &rctx->vs_nconst;
-		offset = R_030000_SQ_ALU_CONSTANT0_0 + 0x1000;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		rstate = rctx->ps_const;
-		nconst = &rctx->ps_nconst;
-		offset = R_030000_SQ_ALU_CONSTANT0_0;
-		break;
-	default:
-		R600_ERR("unsupported %d\n", shader);
-		return;
-	}
-	if (buffer && buffer->width0 > 0) {
-		*nconst = buffer->width0 / 16;
-		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
-		if (ptr == NULL)
-			return;
-		for (int i = 0; i < *nconst; i++, offset += 0x10) {
-			rstate[i].nregs = 0;
-			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x0, ptr[i * 4 + 0], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x4, ptr[i * 4 + 1], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0x8, ptr[i * 4 + 2], 0xFFFFFFFF, NULL);
-			r600_pipe_state_add_reg(&rstate[i], R600_GROUP_ALU_CONST, offset + 0xC, ptr[i * 4 + 3], 0xFFFFFFFF, NULL);
-			r600_context_pipe_state_set(&rctx->ctx, &rstate[i]);
-		}
-		pipe_buffer_unmap(ctx, buffer, transfer);
-	}
-}
-
-static void *r600_create_shader_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *state)
-{
-	struct r600_pipe_shader *shader =  CALLOC_STRUCT(r600_pipe_shader);
-	int r;
-
-	r =  r600_pipe_shader_create2(ctx, shader, state->tokens);
-	if (r) {
-		return NULL;
-	}
-	return shader;
-}
-
-static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	/* TODO delete old shader */
-	rctx->ps_shader = (struct r600_pipe_shader *)state;
-}
-
-static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-
-	/* TODO delete old shader */
-	rctx->vs_shader = (struct r600_pipe_shader *)state;
-}
-
-static void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
-
-	if (rctx->ps_shader == shader) {
-		rctx->ps_shader = NULL;
-	}
-	/* TODO proper delete */
-	free(shader);
-}
-
-static void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
-	struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
-
-	if (rctx->vs_shader == shader) {
-		rctx->vs_shader = NULL;
-	}
-	/* TODO proper delete */
-	free(shader);
-}
-
-static void r600_init_state_functions2(struct r600_pipe_context *rctx)
-{
-	rctx->context.create_blend_state = r600_create_blend_state;
-	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
-	rctx->context.create_fs_state = r600_create_shader_state;
-	rctx->context.create_rasterizer_state = r600_create_rs_state;
-	rctx->context.create_sampler_state = r600_create_sampler_state;
-	rctx->context.create_sampler_view = r600_create_sampler_view;
-	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
-	rctx->context.create_vs_state = r600_create_shader_state;
-	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
-	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
-	rctx->context.bind_fs_state = r600_bind_ps_shader;
-	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
-	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
-	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
-	rctx->context.bind_vs_state = r600_bind_vs_shader;
-	rctx->context.delete_blend_state = r600_delete_state;
-	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.delete_fs_state = r600_delete_ps_shader;
-	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
-	rctx->context.delete_sampler_state = r600_delete_state;
-	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
-	rctx->context.delete_vs_state = r600_delete_vs_shader;
-	rctx->context.set_blend_color = r600_set_blend_color;
-	rctx->context.set_clip_state = r600_set_clip_state;
-	rctx->context.set_constant_buffer = r600_set_constant_buffer;
-	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
-	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
-	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
-	rctx->context.set_sample_mask = r600_set_sample_mask;
-	rctx->context.set_scissor_state = r600_set_scissor_state;
-	rctx->context.set_stencil_ref = r600_set_stencil_ref;
-	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
-	rctx->context.set_index_buffer = r600_set_index_buffer;
-	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
-	rctx->context.set_viewport_state = r600_set_viewport_state;
-	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
-}
-
-static void r600_init_config2(struct r600_pipe_context *rctx)
-{
-	int ps_prio;
-	int vs_prio;
-	int gs_prio;
-	int es_prio;
-	int num_ps_gprs;
-	int num_vs_gprs;
-	int num_gs_gprs;
-	int num_es_gprs;
-	int num_temp_gprs;
-	int num_ps_threads;
-	int num_vs_threads;
-	int num_gs_threads;
-	int num_es_threads;
-	int num_ps_stack_entries;
-	int num_vs_stack_entries;
-	int num_gs_stack_entries;
-	int num_es_stack_entries;
-	enum radeon_family family;
-	struct r600_pipe_state *rstate = &rctx->config;
-	u32 tmp;
-
-	family = r600_get_family(rctx->radeon);
-	ps_prio = 0;
-	vs_prio = 1;
-	gs_prio = 2;
-	es_prio = 3;
-	switch (family) {
-	case CHIP_R600:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV630:
-	case CHIP_RV635:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 144;
-		num_vs_threads = 40;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV610:
-	case CHIP_RV620:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	default:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV670:
-		num_ps_gprs = 144;
-		num_vs_gprs = 40;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 136;
-		num_vs_threads = 48;
-		num_gs_threads = 4;
-		num_es_threads = 4;
-		num_ps_stack_entries = 40;
-		num_vs_stack_entries = 40;
-		num_gs_stack_entries = 32;
-		num_es_stack_entries = 16;
-		break;
-	case CHIP_RV770:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 188;
-		num_vs_threads = 60;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 256;
-		num_vs_stack_entries = 256;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV730:
-	case CHIP_RV740:
-		num_ps_gprs = 84;
-		num_vs_gprs = 36;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 188;
-		num_vs_threads = 60;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	case CHIP_RV710:
-		num_ps_gprs = 192;
-		num_vs_gprs = 56;
-		num_temp_gprs = 4;
-		num_gs_gprs = 0;
-		num_es_gprs = 0;
-		num_ps_threads = 144;
-		num_vs_threads = 48;
-		num_gs_threads = 0;
-		num_es_threads = 0;
-		num_ps_stack_entries = 128;
-		num_vs_stack_entries = 128;
-		num_gs_stack_entries = 0;
-		num_es_stack_entries = 0;
-		break;
-	}
-
-	rstate->id = R600_PIPE_STATE_CONFIG;
-
-	/* SQ_CONFIG */
-	tmp = 0;
-	switch (family) {
-	case CHIP_RV610:
-	case CHIP_RV620:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	case CHIP_RV710:
-		break;
-	default:
-		tmp |= S_008C00_VC_ENABLE(1);
-		break;
-	}
-	tmp |= S_008C00_DX9_CONSTS(1);
-	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	tmp |= S_008C00_PS_PRIO(ps_prio);
-	tmp |= S_008C00_VS_PRIO(vs_prio);
-	tmp |= S_008C00_GS_PRIO(gs_prio);
-	tmp |= S_008C00_ES_PRIO(es_prio);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
-
-	/* SQ_GPR_RESOURCE_MGMT_1 */
-	tmp = 0;
-	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
-
-	/* SQ_GPR_RESOURCE_MGMT_2 */
-	tmp = 0;
-	tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	tmp |= S_008C08_NUM_GS_GPRS(num_es_gprs);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
-
-	/* SQ_THREAD_RESOURCE_MGMT */
-	tmp = 0;
-	tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
-
-	/* SQ_STACK_RESOURCE_MGMT_1 */
-	tmp = 0;
-	tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
-
-	/* SQ_STACK_RESOURCE_MGMT_2 */
-	tmp = 0;
-	tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
-
-	if (family >= CHIP_RV770) {
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000002, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00514000, 0xFFFFFFFF, NULL);
-	} else {
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009508_TA_CNTL_AUX, 0x07000003, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONFIG, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
-		r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A4C_PA_SC_MODE_CNTL, 0x00004010, 0xFFFFFFFF, NULL);
-	}
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
-
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028400_VGT_MAX_VTX_INDX, 0x00FFFFFF, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028404_VGT_MIN_VTX_INDX, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_pipe_state_add_reg(rstate, R600_GROUP_CONTEXT, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
-	r600_context_pipe_state_set(&rctx->ctx, rstate);
-}
-
-static struct pipe_context *r600_create_context2(struct pipe_screen *screen, void *priv)
-{
-	struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
-	struct r600_screen* rscreen = (struct r600_screen *)screen;
-
-	if (rctx == NULL)
-		return NULL;
-	rctx->context.winsys = rscreen->screen.winsys;
-	rctx->context.screen = screen;
-	rctx->context.priv = priv;
-	rctx->context.destroy = r600_destroy_context;
-	rctx->context.draw_vbo = r600_draw_vbo2;
-	rctx->context.flush = r600_flush2;
-
-	/* Easy accessing of screen/winsys. */
-	rctx->screen = rscreen;
-	rctx->radeon = rscreen->radeon;
-
-	r600_init_blit_functions2(rctx);
-	r600_init_state_functions2(rctx);
-	r600_init_context_resource_functions2(rctx);
-
-	rctx->blitter = util_blitter_create(&rctx->context);
-	if (rctx->blitter == NULL) {
-		FREE(rctx);
-		return NULL;
-	}
-
-	if (r600_context_init(&rctx->ctx, rctx->radeon)) {
-		r600_destroy_context(&rctx->context);
-		return NULL;
-	}
-
-	r600_init_config2(rctx);
-
-	return &rctx->context;
-}
-
-static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
-{
-	switch(shader)
-	{
-	case PIPE_SHADER_FRAGMENT:
-	case PIPE_SHADER_VERTEX:
-		break;
-	case PIPE_SHADER_GEOMETRY:
-		/* TODO: support and enable geometry programs */
-		return 0;
-	default:
-		/* TODO: support tessellation on Evergreen */
-		return 0;
-	}
-
-	/* TODO: all these should be fixed, since r600 surely supports much more! */
-	switch (param) {
-	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
-		return 16384;
-	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
-		return 8; /* FIXME */
-	case PIPE_SHADER_CAP_MAX_INPUTS:
-		if(shader == PIPE_SHADER_FRAGMENT)
-			return 10;
-		else
-			return 16;
-	case PIPE_SHADER_CAP_MAX_TEMPS:
-		return 256; //max native temporaries
-	case PIPE_SHADER_CAP_MAX_ADDRS:
-		return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
-	case PIPE_SHADER_CAP_MAX_CONSTS:
-		return 256; //max native parameters
-	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
-		return 1;
-	case PIPE_SHADER_CAP_MAX_PREDS:
-		return 0; /* FIXME */
-	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
-		/* TODO: support this! */
-		return 0;
-	default:
-		return 0;
-	}
-}
-
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-struct pipe_screen *r600_screen_create2(struct radeon *radeon)
-{
-	struct r600_screen *rscreen;
-	enum radeon_family family = r600_get_family(radeon);
-
-	rscreen = CALLOC_STRUCT(r600_screen);
-	if (rscreen == NULL) {
-		return NULL;
-	}
-
-	switch (family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-		rscreen->chip_class = R600;
-		break;
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-		rscreen->chip_class = R700;
-		break;
-	default:
-		FREE(rscreen);
-		return NULL;
-	}
-	rscreen->radeon = radeon;
-	rscreen->screen.winsys = (struct pipe_winsys*)radeon;
-	rscreen->screen.destroy = r600_destroy_screen;
-	rscreen->screen.get_name = r600_get_name;
-	rscreen->screen.get_vendor = r600_get_vendor;
-	rscreen->screen.get_param = r600_get_param;
-	rscreen->screen.get_shader_param = r600_get_shader_param;
-	rscreen->screen.get_paramf = r600_get_paramf;
-	rscreen->screen.is_format_supported = r600_is_format_supported;
-	rscreen->screen.context_create = r600_create_context2;
-	r600_init_screen_texture_functions(&rscreen->screen);
-	r600_init_screen_resource_functions(&rscreen->screen);
-
-	return &rscreen->screen;
-}
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index b4c21d9e12..1c1978f8ab 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -25,6 +25,7 @@
 
 #include "util/u_format.h"
 #include "r600d.h"
+#include "r600_formats.h"
 
 static INLINE uint32_t r600_translate_blend_function(int blend_func)
 {
@@ -123,6 +124,21 @@ static INLINE uint32_t r600_translate_stencil_op(int s_op)
 	return 0;
 }
 
+static INLINE uint32_t r600_translate_fill(uint32_t func)
+{
+	switch(func) {
+	case PIPE_POLYGON_MODE_FILL:
+		return 2;
+	case PIPE_POLYGON_MODE_LINE:
+		return 1;
+	case PIPE_POLYGON_MODE_POINT:
+		return 0;
+	default:
+		assert(0);
+		return 0;
+	}
+}
+
 /* translates straight */
 static INLINE uint32_t r600_translate_ds_func(int func)
 {
@@ -136,17 +152,17 @@ static inline unsigned r600_tex_wrap(unsigned wrap)
 	case PIPE_TEX_WRAP_REPEAT:
 		return V_03C000_SQ_TEX_WRAP;
 	case PIPE_TEX_WRAP_CLAMP:
-		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
-	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 		return V_03C000_SQ_TEX_CLAMP_BORDER;
 	case PIPE_TEX_WRAP_MIRROR_REPEAT:
 		return V_03C000_SQ_TEX_MIRROR;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 	}
@@ -283,6 +299,17 @@ static inline uint32_t r600_translate_colorswap(enum pipe_format format)
 	case PIPE_FORMAT_B4G4R4A4_UNORM:
 	case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_0280A0_SWAP_STD;
+
 		/* 32-bit buffers. */
 
 	case PIPE_FORMAT_A8B8G8R8_SRGB:
@@ -310,22 +337,29 @@ static inline uint32_t r600_translate_colorswap(enum pipe_format format)
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 		return V_0280A0_SWAP_STD;
 
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_0280A0_SWAP_STD;
+
 	case PIPE_FORMAT_R10G10B10A2_UNORM:
 	case PIPE_FORMAT_R10G10B10X2_SNORM:
 	case PIPE_FORMAT_B10G10R10A2_UNORM:
 	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 		return V_0280A0_SWAP_STD_REV;
 
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_0280A0_SWAP_STD;
+
 		/* 64-bit buffers. */
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
 	case PIPE_FORMAT_R16G16B16A16_SNORM:
-		//		return V_0280A0_COLOR_16_16_16_16;
+		//		return FMT_16_16_16_16;
 	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-		//		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+		//		return FMT_16_16_16_16_FLOAT;
 
 		/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		//		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+		//		return FMT_32_32_32_32_FLOAT;
 		return 0;
 	default:
 		R600_ERR("unsupported colorswap format %d\n", format);
@@ -357,6 +391,16 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return V_0280A0_COLOR_4_4_4_4;
 
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_0280A0_COLOR_16;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_0280A0_COLOR_8_8;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_0280A0_COLOR_16;
+
 		/* 32-bit buffers. */
 	case PIPE_FORMAT_A8B8G8R8_SRGB:
 	case PIPE_FORMAT_A8B8G8R8_UNORM:
@@ -383,18 +427,41 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 		return V_0280A0_COLOR_8_24;
 
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_0280A0_COLOR_24_8;
+
 	case PIPE_FORMAT_R32_FLOAT:
 		return V_0280A0_COLOR_32_FLOAT;
 
+	case PIPE_FORMAT_R16G16_FLOAT:
+		return V_0280A0_COLOR_16_16_FLOAT;
+
+	case PIPE_FORMAT_R16G16_SSCALED:
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_0280A0_COLOR_16_16;
+
+
 		/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16_USCALED:
+	case PIPE_FORMAT_R16G16B16A16_USCALED:
+	case PIPE_FORMAT_R16G16B16_SSCALED:
+	case PIPE_FORMAT_R16G16B16A16_SSCALED:
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
 	case PIPE_FORMAT_R16G16B16A16_SNORM:
 		return V_0280A0_COLOR_16_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_FLOAT:
 	case PIPE_FORMAT_R16G16B16A16_FLOAT:
 		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+
 	case PIPE_FORMAT_R32G32_FLOAT:
 		return V_0280A0_COLOR_32_32_FLOAT;
 
+	case PIPE_FORMAT_R32G32_USCALED:
+	case PIPE_FORMAT_R32G32_SSCALED:
+		return V_0280A0_COLOR_32_32;
+
 		/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32_FLOAT:
 	  	return V_0280A0_COLOR_32_32_32_FLOAT;
@@ -405,7 +472,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_UYVY:
 	case PIPE_FORMAT_YUYV:
 	default:
-		R600_ERR("unsupported color format %d\n", format);
+		R600_ERR("unsupported color format %d %s\n", format, util_format_name(format));
 		return ~0; /* Unsupported. */
 	}
 }
@@ -431,4 +498,139 @@ static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
 	return r600_translate_colorformat(format) != ~0;
 }
 
+static INLINE uint32_t r600_translate_vertex_data_type(enum pipe_format format)
+{
+	uint32_t result = 0;
+	const struct util_format_description *desc;
+	unsigned i;
+
+	desc = util_format_description(format);
+	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
+		goto out_unknown;
+	}
+
+	/* Find the first non-VOID channel. */
+	for (i = 0; i < 4; i++) {
+		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+			break;
+		}
+	}
+
+	switch (desc->channel[i].type) {
+		/* Half-floats, floats, doubles */
+        case UTIL_FORMAT_TYPE_FLOAT:
+		switch (desc->channel[i].size) {
+                case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_16_FLOAT;
+				break;
+			case 2:
+				result = FMT_16_16_FLOAT;
+				break;
+			case 3:
+				result = FMT_16_16_16_FLOAT;
+				break;
+			case 4:
+				result = FMT_16_16_16_16_FLOAT;
+				break;
+			}
+			break;
+                case 32:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_32_FLOAT;
+				break;
+			case 2:
+				result = FMT_32_32_FLOAT;
+				break;
+			case 3:
+				result = FMT_32_32_32_FLOAT;
+				break;
+			case 4:
+				result = FMT_32_32_32_32_FLOAT;
+				break;
+			}
+			break;
+                default:
+			goto out_unknown;
+		}
+		break;
+		/* Unsigned ints */
+        case UTIL_FORMAT_TYPE_UNSIGNED:
+		/* Signed ints */
+        case UTIL_FORMAT_TYPE_SIGNED:
+		switch (desc->channel[i].size) {
+                case 8:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_8;
+				break;
+			case 2:
+				result = FMT_8_8;
+				break;
+			case 3:
+			//	result = FMT_8_8_8; /* fails piglit draw-vertices test */
+			//	break;
+			case 4:
+				result = FMT_8_8_8_8;
+				break;
+			}
+			break;
+                case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_16;
+				break;
+			case 2:
+				result = FMT_16_16;
+				break;
+			case 3:
+			//	result = FMT_16_16_16; /* fails piglit draw-vertices test */
+			//	break;
+			case 4:
+				result = FMT_16_16_16_16;
+				break;
+			}
+			break;
+                case 32:
+			switch (desc->nr_channels) {
+			case 1:
+				result = FMT_32;
+				break;
+			case 2:
+				result = FMT_32_32;
+				break;
+			case 3:
+				result = FMT_32_32_32;
+				break;
+			case 4:
+				result = FMT_32_32_32_32;
+				break;
+			}
+			break;
+                default:
+			goto out_unknown;
+		}
+		break;
+        default:
+		goto out_unknown;
+	}
+	
+	result = S_038008_DATA_FORMAT(result);
+
+	if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+		result |= S_038008_FORMAT_COMP_ALL(1);
+	}
+	if (desc->channel[i].normalized) {
+		result |= S_038008_NUM_FORMAT_ALL(0);
+	} else {
+		result |= S_038008_NUM_FORMAT_ALL(2);
+	}
+	return result;
+out_unknown:
+	R600_ERR("unsupported vertex format %s\n", util_format_name(format));
+	return ~0;
+}
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_states_inc.h b/src/gallium/drivers/r600/r600_states_inc.h
index de717f3536..1c8075ebdb 100644
--- a/src/gallium/drivers/r600/r600_states_inc.h
+++ b/src/gallium/drivers/r600/r600_states_inc.h
@@ -15,35 +15,34 @@
 #define R600_CONFIG__DB_WATERMARKS		10
 #define R600_CONFIG__SX_MISC		11
 #define R600_CONFIG__SPI_THREAD_GROUPING		12
-#define R600_CONFIG__CB_SHADER_CONTROL		13
-#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE		14
-#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE		15
-#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE		16
-#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE		17
-#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE		18
-#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE		19
-#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE		20
-#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE		21
-#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE		22
-#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL		23
-#define R600_CONFIG__VGT_HOS_CNTL		24
-#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL		25
-#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL		26
-#define R600_CONFIG__VGT_HOS_REUSE_DEPTH		27
-#define R600_CONFIG__VGT_GROUP_PRIM_TYPE		28
-#define R600_CONFIG__VGT_GROUP_FIRST_DECR		29
-#define R600_CONFIG__VGT_GROUP_DECR		30
-#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL		31
-#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL		32
-#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL		33
-#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL		34
-#define R600_CONFIG__VGT_GS_MODE		35
-#define R600_CONFIG__PA_SC_MODE_CNTL		36
-#define R600_CONFIG__VGT_STRMOUT_EN		37
-#define R600_CONFIG__VGT_REUSE_OFF		38
-#define R600_CONFIG__VGT_VTX_CNT_EN		39
-#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN		40
-#define R600_CONFIG_SIZE		41
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE		13
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE		14
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE		15
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE		16
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE		17
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE		18
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE		19
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE		20
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE		21
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL		22
+#define R600_CONFIG__VGT_HOS_CNTL		23
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL		24
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL		25
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH		26
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE		27
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR		28
+#define R600_CONFIG__VGT_GROUP_DECR		29
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL		30
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL		31
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL		32
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL		33
+#define R600_CONFIG__VGT_GS_MODE		34
+#define R600_CONFIG__PA_SC_MODE_CNTL		35
+#define R600_CONFIG__VGT_STRMOUT_EN		36
+#define R600_CONFIG__VGT_REUSE_OFF		37
+#define R600_CONFIG__VGT_VTX_CNT_EN		38
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN		39
+#define R600_CONFIG_SIZE		40
 #define R600_CONFIG_PM4 128		
 
 /* R600_CB_CNTL */
@@ -65,7 +64,8 @@
 #define R600_CB_CNTL__CB_CLRCMP_DST		15
 #define R600_CB_CNTL__CB_CLRCMP_MSK		16
 #define R600_CB_CNTL__PA_SC_AA_MASK		17
-#define R600_CB_CNTL_SIZE		18
+#define R600_CB_CNTL__CB_SHADER_CONTROL		18
+#define R600_CB_CNTL_SIZE		19
 #define R600_CB_CNTL_PM4 128		
 
 /* R600_RASTERIZER */
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 274679d127..152cd9210f 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -31,11 +31,11 @@
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
 #include "state_tracker/drm_driver.h"
-#include "r600_screen.h"
-#include "r600_context.h"
+#include "r600_pipe.h"
 #include "r600_resource.h"
 #include "r600_state_inlines.h"
 #include "r600d.h"
+#include "r600_formats.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
@@ -54,11 +54,30 @@ static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_t
 				transfer->box.width, transfer->box.height);
 }
 
-static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
+
+/* Copy from a detiled texture to a tiled one. */
+static void r600_copy_into_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+{
+	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+	struct pipe_resource *texture = transfer->resource;
+	struct pipe_subresource subsrc;
+
+	subsrc.face = 0;
+	subsrc.level = 0;
+	ctx->resource_copy_region(ctx, texture, transfer->sr,
+				  transfer->box.x, transfer->box.y, transfer->box.z,
+				  rtransfer->linear_texture, subsrc,
+				  0, 0, 0,
+				  transfer->box.width, transfer->box.height);
+
+	ctx->flush(ctx, 0, NULL);
+}
+
+static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 					unsigned level, unsigned zslice,
 					unsigned face)
 {
-	unsigned long offset = rtex->offset[level];
+	unsigned offset = rtex->offset[level];
 
 	switch (rtex->resource.base.b.target) {
 	case PIPE_TEXTURE_3D:
@@ -73,73 +92,128 @@ static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
 	}
 }
 
-static void r600_setup_miptree(struct r600_resource_texture *rtex)
+static unsigned r600_texture_get_stride(struct pipe_screen *screen,
+					struct r600_resource_texture *rtex,
+					unsigned level)
+{
+	struct pipe_resource *ptex = &rtex->resource.base.b;
+	struct radeon *radeon = (struct radeon *)screen->winsys;
+	enum chip_class chipc = r600_get_family_class(radeon);
+	unsigned width, stride;
+	
+	if (rtex->pitch_override)
+		return rtex->pitch_override;
+
+	width = u_minify(ptex->width0, level);
+
+	stride = util_format_get_stride(ptex->format, align(width, 64));
+	if (chipc == EVERGREEN)
+		stride = align(stride, 512);
+	else
+		stride = align(stride, 256);
+	return stride;
+}
+
+static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
+					  struct r600_resource_texture *rtex,
+					  unsigned level)
+{
+	struct pipe_resource *ptex = &rtex->resource.base.b;
+	unsigned height;
+
+	height = u_minify(ptex->height0, level);
+	height = util_next_power_of_two(height);
+	return util_format_get_nblocksy(ptex->format, height);
+}
+
+/* Get a width in pixels from a stride in bytes. */
+static unsigned pitch_to_width(enum pipe_format format,
+                                unsigned pitch_in_bytes)
+{
+    return (pitch_in_bytes / util_format_get_blocksize(format)) *
+            util_format_get_blockwidth(format);
+}
+
+static void r600_setup_miptree(struct pipe_screen *screen,
+			       struct r600_resource_texture *rtex)
 {
 	struct pipe_resource *ptex = &rtex->resource.base.b;
-	unsigned long w, h, pitch, size, layer_size, i, offset;
+	struct radeon *radeon = (struct radeon *)screen->winsys;
+	enum chip_class chipc = r600_get_family_class(radeon);
+	unsigned pitch, size, layer_size, i, offset;
+	unsigned nblocksy;
 
-	rtex->bpt = util_format_get_blocksize(ptex->format);
 	for (i = 0, offset = 0; i <= ptex->last_level; i++) {
-		w = u_minify(ptex->width0, i);
-		h = u_minify(ptex->height0, i);
-		h = util_next_power_of_two(h);
-		pitch = util_format_get_stride(ptex->format, align(w, 64));
-		pitch = align(pitch, 256);
-		layer_size = pitch * h;
-		if (ptex->target == PIPE_TEXTURE_CUBE)
-			size = layer_size * 6;
+		pitch = r600_texture_get_stride(screen, rtex, i);
+		nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
+
+		layer_size = pitch * nblocksy;
+
+		if (ptex->target == PIPE_TEXTURE_CUBE) {
+			if (chipc >= R700)
+				size = layer_size * 8;
+			else
+				size = layer_size * 6;
+		}
 		else
 			size = layer_size * u_minify(ptex->depth0, i);
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
-		rtex->pitch[i] = pitch;
-		rtex->width[i] = w;
-		rtex->height[i] = h;
+		rtex->pitch_in_bytes[i] = pitch;
+		rtex->pitch_in_pixels[i] = pitch_to_width(ptex->format, pitch);
 		offset += size;
 	}
 	rtex->size = offset;
 }
 
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
-						const struct pipe_resource *templ)
+static struct r600_resource_texture *
+r600_texture_create_object(struct pipe_screen *screen,
+			   const struct pipe_resource *base,
+			   unsigned array_mode,
+			   unsigned pitch_in_bytes_override,
+			   unsigned max_buffer_size,
+			   struct r600_bo *bo)
 {
 	struct r600_resource_texture *rtex;
 	struct r600_resource *resource;
 	struct radeon *radeon = (struct radeon *)screen->winsys;
 
 	rtex = CALLOC_STRUCT(r600_resource_texture);
-	if (!rtex) {
+	if (rtex == NULL)
 		return NULL;
-	}
+
 	resource = &rtex->resource;
-	resource->base.b = *templ;
+	resource->base.b = *base;
 	resource->base.vtbl = &r600_texture_vtbl;
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
-	r600_setup_miptree(rtex);
-
-	/* FIXME alignment 4096 enought ? too much ? */
+	resource->bo = bo;
 	resource->domain = r600_domain_from_usage(resource->base.b.bind);
+	rtex->pitch_override = pitch_in_bytes_override;
+	rtex->array_mode = array_mode;
+
+	r600_setup_miptree(screen, rtex);
+
 	resource->size = rtex->size;
-	resource->bo = radeon_ws_bo(radeon, rtex->size, 4096, 0);
-	if (resource->bo == NULL) {
-		FREE(rtex);
-		return NULL;
+
+	if (!resource->bo) {
+		resource->bo = r600_bo(radeon, rtex->size, 4096, 0);
+		if (!resource->bo) {
+			FREE(rtex);
+			return NULL;
+		}
 	}
-	return &resource->base.b;
+	return rtex;
 }
 
-static void r600_texture_destroy_state(struct pipe_resource *ptexture)
+struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
+						const struct pipe_resource *templ)
 {
-	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
+	unsigned array_mode = 0;
+
+	return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
+								  0, 0, NULL);
 
-	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_fini(&rtexture->scissor[i]);
-		radeon_state_fini(&rtexture->db[i]);
-		for (int j = 0; j < 8; j++) {
-			radeon_state_fini(&rtexture->cb[j][i]);
-		}
-	}
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
@@ -149,13 +223,12 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	struct r600_resource *resource = &rtex->resource;
 	struct radeon *radeon = (struct radeon *)screen->winsys;
 
+	if (rtex->flushed_depth_texture)
+		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
+
 	if (resource->bo) {
-		radeon_ws_bo_reference(radeon, &resource->bo, NULL);
+		r600_bo_reference(radeon, &resource->bo, NULL);
 	}
-	if (rtex->uncompressed) {
-		radeon_ws_bo_reference(radeon, &rtex->uncompressed, NULL);
-	}
-	r600_texture_destroy_state(ptex);
 	FREE(rtex);
 }
 
@@ -166,7 +239,7 @@ static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 	struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
-	unsigned long offset;
+	unsigned offset;
 
 	if (surface == NULL)
 		return NULL;
@@ -191,46 +264,28 @@ static void r600_tex_surface_destroy(struct pipe_surface *surface)
 	FREE(surface);
 }
 
+
 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 					       const struct pipe_resource *templ,
 					       struct winsys_handle *whandle)
 {
 	struct radeon *rw = (struct radeon*)screen->winsys;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *resource;
-	struct radeon_ws_bo *bo = NULL;
+	struct r600_bo *bo = NULL;
 
 	/* Support only 2D textures without mipmaps */
 	if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
 	      templ->depth0 != 1 || templ->last_level != 0)
 		return NULL;
 
-	rtex = CALLOC_STRUCT(r600_resource_texture);
-	if (rtex == NULL)
-		return NULL;
-
-	bo = radeon_ws_bo_handle(rw, whandle->handle);
+	bo = r600_bo_handle(rw, whandle->handle);
 	if (bo == NULL) {
-		FREE(rtex);
 		return NULL;
 	}
 
-	resource = &rtex->resource;
-	resource->base.b = *templ;
-	resource->base.vtbl = &r600_texture_vtbl;
-	pipe_reference_init(&resource->base.b.reference, 1);
-	resource->base.b.screen = screen;
-	resource->bo = bo;
-	rtex->depth = 0;
-	rtex->pitch_override = whandle->stride;
-	rtex->bpt = util_format_get_blocksize(templ->format);
-	rtex->pitch[0] = whandle->stride;
-	rtex->width[0] = templ->width0;
-	rtex->height[0] = templ->height0;
-	rtex->offset[0] = 0;
-	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
-
-	return &resource->base.b;
+	return (struct pipe_resource *)r600_texture_create_object(screen, templ, 0,
+								  whandle->stride,
+								  0,
+								  bo);
 }
 
 static unsigned int r600_texture_is_referenced(struct pipe_context *context,
@@ -241,6 +296,41 @@ static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 }
 
+int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
+int r600_texture_depth_flush(struct pipe_context *ctx,
+			     struct pipe_resource *texture)
+{
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct pipe_resource resource;
+
+	if (rtex->flushed_depth_texture)
+		goto out;
+
+	resource.target = PIPE_TEXTURE_2D;
+	resource.format = texture->format;
+	resource.width0 = texture->width0;
+	resource.height0 = texture->height0;
+	resource.depth0 = 1;
+	resource.last_level = 0;
+	resource.nr_samples = 0;
+	resource.usage = PIPE_USAGE_DYNAMIC;
+	resource.bind = 0;
+	resource.flags = 0;
+
+	resource.bind |= PIPE_BIND_RENDER_TARGET;
+
+	rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+	if (rtex->flushed_depth_texture == NULL) {
+		R600_ERR("failed to create temporary texture to hold untiled copy\n");
+		return -ENOMEM;
+	}
+
+out:
+	r600_blit_uncompress_depth_ptr(ctx, rtex);
+	return 0;
+}
+
 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 						struct pipe_resource *texture,
 						struct pipe_subresource sr,
@@ -250,6 +340,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 	struct pipe_resource resource;
 	struct r600_transfer *trans;
+	int r;
 
 	trans = CALLOC_STRUCT(r600_transfer);
 	if (trans == NULL)
@@ -258,14 +349,22 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.sr = sr;
 	trans->transfer.usage = usage;
 	trans->transfer.box = *box;
-	trans->transfer.stride = rtex->pitch[sr.level];
+	trans->transfer.stride = rtex->pitch_in_bytes[sr.level];
 	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
-	if (rtex->tilled && !rtex->depth) {
+	if (rtex->depth) {
+		r = r600_texture_depth_flush(ctx, texture);
+		if (r < 0) {
+			R600_ERR("failed to create temporary texture to hold untiled copy\n");
+			pipe_resource_reference(&trans->transfer.resource, NULL);
+			FREE(trans);
+			return NULL;
+		}
+	} else if (rtex->tiled) {
 		resource.target = PIPE_TEXTURE_2D;
 		resource.format = texture->format;
 		resource.width0 = box->width;
 		resource.height0 = box->height;
-		resource.depth0 = 0;
+		resource.depth0 = 1;
 		resource.last_level = 0;
 		resource.nr_samples = 0;
 		resource.usage = PIPE_USAGE_DYNAMIC;
@@ -289,6 +388,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 			FREE(trans);
 			return NULL;
 		}
+
+		trans->transfer.stride =
+		  ((struct r600_resource_texture *)trans->linear_texture)->pitch_in_bytes[0];
 		if (usage & PIPE_TRANSFER_READ) {
 			/* We cannot map a tiled texture directly because the data is
 			 * in a different order, therefore we do detiling using a blit. */
@@ -304,10 +406,17 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 				   struct pipe_transfer *transfer)
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 
 	if (rtransfer->linear_texture) {
+		if (transfer->usage & PIPE_TRANSFER_WRITE) {
+			r600_copy_into_tiled_texture(ctx, rtransfer);
+		}
 		pipe_resource_reference(&rtransfer->linear_texture, NULL);
 	}
+	if (rtex->flushed_depth_texture) {
+		pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL);
+	}
 	pipe_resource_reference(&transfer->resource, NULL);
 	FREE(transfer);
 }
@@ -315,40 +424,31 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 void* r600_texture_transfer_map(struct pipe_context *ctx,
 				struct pipe_transfer* transfer)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct radeon_ws_bo *bo;
+	struct r600_bo *bo;
 	enum pipe_format format = transfer->resource->format;
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
-	struct r600_resource_texture *rtex;
-	unsigned long offset = 0;
+	unsigned offset = 0;
 	char *map;
-	int r;
 
-	ctx->flush(ctx, 0, NULL);
 	if (rtransfer->linear_texture) {
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		rtex = (struct r600_resource_texture*)transfer->resource;
-		if (rtex->depth && rscreen->chip_class != EVERGREEN) {
-			r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
-			if (r) {
-				return NULL;
-			}
-			r600_flush(ctx, 0, NULL);
-			bo = rtex->uncompressed;
-		} else {
+		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+		if (rtex->flushed_depth_texture)
+			bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
+		else
 			bo = ((struct r600_resource *)transfer->resource)->bo;
-		}
+
 		offset = rtransfer->offset +
 			transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 			transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 	}
-	map = radeon_ws_bo_map(radeon, bo, 0, r600_context(ctx));
+	map = r600_bo_map(radeon, bo, 0, ctx);
 	if (!map) {
 		return NULL;
 	}
-	radeon_ws_bo_wait(radeon, bo);
 
 	return map + offset;
 }
@@ -358,20 +458,20 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
-	struct r600_resource_texture *rtex;
-	struct radeon_ws_bo *bo;
+	struct r600_bo *bo;
 
 	if (rtransfer->linear_texture) {
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		rtex = (struct r600_resource_texture*)transfer->resource;
-		if (rtex->depth) {
-			bo = rtex->uncompressed;
+		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+		if (rtex->flushed_depth_texture) {
+			bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 		} else {
 			bo = ((struct r600_resource *)transfer->resource)->bo;
 		}
 	}
-	radeon_ws_bo_unmap(radeon, bo);
+	r600_bo_unmap(radeon, bo);
 }
 
 struct u_resource_vtbl r600_texture_vtbl =
@@ -466,13 +566,23 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 	case UTIL_FORMAT_COLORSPACE_ZS:
 		switch (format) {
 		case PIPE_FORMAT_Z16_UNORM:
-			result = V_0280A0_COLOR_16;
+			result = FMT_16;
 			goto out_word4;
+		case PIPE_FORMAT_X24S8_USCALED:
+			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 		case PIPE_FORMAT_Z24X8_UNORM:
-			result = V_0280A0_COLOR_8_24;
-			goto out_word4;
 		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-			result = V_0280A0_COLOR_8_24;
+			result = FMT_8_24;
+			goto out_word4;
+		case PIPE_FORMAT_S8X24_USCALED:
+			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
+		case PIPE_FORMAT_X8Z24_UNORM:
+		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+			result = FMT_24_8;
+			goto out_word4;
+		case PIPE_FORMAT_S8_USCALED:
+			result = V_0280A0_COLOR_8;
+			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 			goto out_word4;
 		default:
 			goto out_unknown;
@@ -526,7 +636,7 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 			if (desc->channel[0].size == 5 &&
 			    desc->channel[1].size == 6 &&
 			    desc->channel[2].size == 5) {
-				result = V_0280A0_COLOR_5_6_5;
+				result = FMT_5_6_5;
 				goto out_word4;
 			}
 			goto out_unknown;
@@ -535,14 +645,14 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 			    desc->channel[1].size == 5 &&
 			    desc->channel[2].size == 5 &&
 			    desc->channel[3].size == 1) {
-				result = V_0280A0_COLOR_1_5_5_5;
+				result = FMT_1_5_5_5;
 				goto out_word4;
 			}
 			if (desc->channel[0].size == 10 &&
 			    desc->channel[1].size == 10 &&
 			    desc->channel[2].size == 10 &&
 			    desc->channel[3].size == 2) {
-				result = V_0280A0_COLOR_10_10_10_2;
+				result = FMT_10_10_10_2;
 				goto out_word4;
 			}
 			goto out_unknown;
@@ -550,79 +660,89 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 		goto out_unknown;
 	}
 
+	/* Find the first non-VOID channel. */
+	for (i = 0; i < 4; i++) {
+		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+			break;
+		}
+	}
+
+	if (i == 4)
+		goto out_unknown;
+
 	/* uniform formats */
-	switch (desc->channel[0].type) {
+	switch (desc->channel[i].type) {
 	case UTIL_FORMAT_TYPE_UNSIGNED:
 	case UTIL_FORMAT_TYPE_SIGNED:
-		if (!desc->channel[0].normalized &&
+		if (!desc->channel[i].normalized &&
 		    desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
 			goto out_unknown;
 		}
 
-		switch (desc->channel[0].size) {
+		switch (desc->channel[i].size) {
 		case 4:
 			switch (desc->nr_channels) {
 			case 2:
-				result = V_0280A0_COLOR_4_4;
+				result = FMT_4_4;
 				goto out_word4;
 			case 4:
-				result = V_0280A0_COLOR_4_4_4_4;
+				result = FMT_4_4_4_4;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 8:
 			switch (desc->nr_channels) {
 			case 1:
-				result = V_0280A0_COLOR_8;
+				result = FMT_8;
 				goto out_word4;
 			case 2:
-				result = V_0280A0_COLOR_8_8;
+				result = FMT_8_8;
 				goto out_word4;
 			case 4:
-				result = V_0280A0_COLOR_8_8_8_8;
+				result = FMT_8_8_8_8;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 16:
 			switch (desc->nr_channels) {
 			case 1:
-				result = V_0280A0_COLOR_16;
+				result = FMT_16;
 				goto out_word4;
 			case 2:
-				result = V_0280A0_COLOR_16_16;
+				result = FMT_16_16;
 				goto out_word4;
 			case 4:
-				result = V_0280A0_COLOR_16_16_16_16;
+				result = FMT_16_16_16_16;
 				goto out_word4;
 			}
 		}
 		goto out_unknown;
 
 	case UTIL_FORMAT_TYPE_FLOAT:
-		switch (desc->channel[0].size) {
+		switch (desc->channel[i].size) {
 		case 16:
 			switch (desc->nr_channels) {
 			case 1:
-				result = V_0280A0_COLOR_16_FLOAT;
+				result = FMT_16_FLOAT;
 				goto out_word4;
 			case 2:
-				result = V_0280A0_COLOR_16_16_FLOAT;
+				result = FMT_16_16_FLOAT;
 				goto out_word4;
 			case 4:
-				result = V_0280A0_COLOR_16_16_16_16_FLOAT;
+				result = FMT_16_16_16_16_FLOAT;
 				goto out_word4;
 			}
 			goto out_unknown;
 		case 32:
 			switch (desc->nr_channels) {
 			case 1:
-				result = V_0280A0_COLOR_32_FLOAT;
+				result = FMT_32_FLOAT;
 				goto out_word4;
 			case 2:
-				result = V_0280A0_COLOR_32_32_FLOAT;
+				result = FMT_32_32_FLOAT;
 				goto out_word4;
 			case 4:
-				result = V_0280A0_COLOR_32_32_32_32_FLOAT;
+				result = FMT_32_32_32_32_FLOAT;
 				goto out_word4;
 			}
 		}
@@ -638,81 +758,3 @@ out_unknown:
 //	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 	return ~0;
 }
-
-int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	int r;
-
-	if (!rtexture->depth) {
-		/* This shouldn't happen maybe print a warning */
-		return 0;
-	}
-	if (rtexture->uncompressed && !rtexture->dirty) {
-		/* Uncompressed bo already in good state */
-		return 0;
-	}
-
-	/* allocate uncompressed texture */
-	if (rtexture->uncompressed == NULL) {
-		rtexture->uncompressed = radeon_ws_bo(rscreen->rw, rtexture->size, 4096, 0);
-		if (rtexture->uncompressed == NULL) {
-			return -ENOMEM;
-		}
-	}
-
-	/* render a rectangle covering whole buffer to uncompress depth */
-	r = r600_blit_uncompress_depth(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-
-	rtexture->dirty = 0;
-	return 0;
-}
-
-
-
-int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->scissor[level].cpm4) {
-		rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
-	}
-	return 0;
-}
-
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->cb[cb][level].cpm4) {
-		rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
-	}
-	return 0;
-}
-
-int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->db[level].cpm4) {
-		rctx->vtbl->texture_state_db(rscreen, rtexture, level);
-	}
-	return 0;
-}
-
-int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->viewport[level].cpm4) {
-		rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
-	}
-	return 0;
-}
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 07bfc0593e..a3cb5b8600 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -607,8 +607,15 @@
 #define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
 #define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
 #define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define   S_028D0C_DEPTH_CLEAR_ENABLE(x)               (((x) & 0x1) << 0)
+#define   S_028D0C_STENCIL_CLEAR_ENABLE(x)             (((x) & 0x1) << 1)
+#define   S_028D0C_DEPTH_COPY_ENABLE(x)                (((x) & 0x1) << 2)
+#define   S_028D0C_STENCIL_COPY_ENABLE(x)              (((x) & 0x1) << 3)
+#define   S_028D0C_RESUMMARIZE_ENABLE(x)               (((x) & 0x1) << 4)
 #define   S_028D0C_STENCIL_COMPRESS_DISABLE(x)         (((x) & 0x1) << 5)
 #define   S_028D0C_DEPTH_COMPRESS_DISABLE(x)           (((x) & 0x1) << 6)
+#define   S_028D0C_COPY_CENTROID(x)                    (((x) & 0x1) << 7)
+#define   S_028D0C_COPY_SAMPLE(x)                      (((x) & 0x1) << 8)
 #define   S_028D0C_R700_PERFECT_ZPASS_COUNTS(x)        (((x) & 0x1) << 15)
 #define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
 #define   V_028D10_FORCE_OFF                         0
@@ -660,6 +667,9 @@
 #define   S_02880C_Z_EXPORT_ENABLE(x)                  (((x) & 0x1) << 0)
 #define   G_02880C_Z_EXPORT_ENABLE(x)                  (((x) >> 0) & 0x1)
 #define   C_02880C_Z_EXPORT_ENABLE                     0xFFFFFFFE
+#define   S_02880C_STENCIL_REF_EXPORT_ENABLE(x)        (((x) & 0x1) << 1)
+#define   G_02880C_STENCIL_REF_EXPORT_ENABLE(x)        (((x) >> 1) & 0x1)
+#define   C_02880C_STENCIL_REF_EXPORT_ENABLE           0xFFFFFFFD
 #define   S_02880C_Z_ORDER(x)                          (((x) & 0x3) << 4)
 #define   G_02880C_Z_ORDER(x)                          (((x) >> 4) & 0x3)
 #define   C_02880C_Z_ORDER                             0xFFFFFCFF
@@ -894,6 +904,10 @@
 #define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
 #define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
 #define   C_038000_TILE_MODE                           0xFFFFFF87
+#define     V_038000_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_038000_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_038000_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_038000_ARRAY_2D_TILED_THIN1              0x00000004
 #define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
 #define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
 #define   C_038000_TILE_TYPE                           0xFFFFFF7F
@@ -1018,43 +1032,13 @@
 #define   S_038008_DATA_FORMAT(x)                      (((x) & 0x3F) << 20)
 #define   G_038008_DATA_FORMAT(x)                      (((x) >> 20) & 0x3F)
 #define   C_038008_DATA_FORMAT                         0xFC0FFFFF
-#define     V_038008_COLOR_INVALID                     0x00000000
-#define     V_038008_COLOR_8                           0x00000001
-#define     V_038008_COLOR_4_4                         0x00000002
-#define     V_038008_COLOR_3_3_2                       0x00000003
-#define     V_038008_COLOR_16                          0x00000005
-#define     V_038008_COLOR_16_FLOAT                    0x00000006
-#define     V_038008_COLOR_8_8                         0x00000007
-#define     V_038008_COLOR_5_6_5                       0x00000008
-#define     V_038008_COLOR_6_5_5                       0x00000009
-#define     V_038008_COLOR_1_5_5_5                     0x0000000A
-#define     V_038008_COLOR_4_4_4_4                     0x0000000B
-#define     V_038008_COLOR_5_5_5_1                     0x0000000C
-#define     V_038008_COLOR_32                          0x0000000D
-#define     V_038008_COLOR_32_FLOAT                    0x0000000E
-#define     V_038008_COLOR_16_16                       0x0000000F
-#define     V_038008_COLOR_16_16_FLOAT                 0x00000010
-#define     V_038008_COLOR_8_24                        0x00000011
-#define     V_038008_COLOR_8_24_FLOAT                  0x00000012
-#define     V_038008_COLOR_24_8                        0x00000013
-#define     V_038008_COLOR_24_8_FLOAT                  0x00000014
-#define     V_038008_COLOR_10_11_11                    0x00000015
-#define     V_038008_COLOR_10_11_11_FLOAT              0x00000016
-#define     V_038008_COLOR_11_11_10                    0x00000017
-#define     V_038008_COLOR_11_11_10_FLOAT              0x00000018
-#define     V_038008_COLOR_2_10_10_10                  0x00000019
-#define     V_038008_COLOR_8_8_8_8                     0x0000001A
-#define     V_038008_COLOR_10_10_10_2                  0x0000001B
-#define     V_038008_COLOR_X24_8_32_FLOAT              0x0000001C
-#define     V_038008_COLOR_32_32                       0x0000001D
-#define     V_038008_COLOR_32_32_FLOAT                 0x0000001E
-#define     V_038008_COLOR_16_16_16_16                 0x0000001F
-#define     V_038008_COLOR_16_16_16_16_FLOAT           0x00000020
-#define     V_038008_COLOR_32_32_32_32                 0x00000022
-#define     V_038008_COLOR_32_32_32_32_FLOAT           0x00000023
+
 #define   S_038008_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 26)
 #define   G_038008_NUM_FORMAT_ALL(x)                   (((x) >> 26) & 0x3)
 #define   C_038008_NUM_FORMAT_ALL                      0xF3FFFFFF
+#define     V_038008_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_038008_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_038008_SQ_NUM_FORMAT_SCALED              0x00000002
 #define   S_038008_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 28)
 #define   G_038008_FORMAT_COMP_ALL(x)                  (((x) >> 28) & 0x1)
 #define   C_038008_FORMAT_COMP_ALL                     0xEFFFFFFF
@@ -2112,6 +2096,9 @@
 #define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
 #define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
 #define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define   S_028C00_LAST_PIXEL(x)                       (((x) & 0x1) << 10)
+#define   G_028C00_LAST_PIXEL(x)                       (((x) >> 10) & 0x1)
+#define   C_028C00_LAST_PIXEL                          0xFFFFFBFF
 #define R_028C04_PA_SC_AA_CONFIG                     0x028C04
 #define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
 #define R_028C48_PA_SC_AA_MASK                       0x028C48
@@ -2125,7 +2112,16 @@
 #define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
 #define R_028A00_PA_SU_POINT_SIZE                    0x028A00
 #define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define   S_028A04_MIN_SIZE(x)                         (((x) & 0xFFFF) << 0)
+#define   G_028A04_MIN_SIZE(x)                         (((x) >> 0) & 0xFFFF)
+#define   C_028A04_MIN_SIZE                            0xFFFF0000
+#define   S_028A04_MAX_SIZE(x)                         (((x) & 0xFFFF) << 16)
+#define   G_028A04_MAX_SIZE(x)                         (((x) >> 16) & 0xFFFF)
+#define   C_028A04_MAX_SIZE                            0x0000FFFF
 #define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define   S_028A08_WIDTH(x)                            (((x) & 0xFFFF) << 0)
+#define   G_028A08_WIDTH(x)                            (((x) >> 0) & 0xFFFF)
+#define   C_028A08_WIDTH                               0xFFFF0000
 #define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
 #define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
 #define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
@@ -2134,6 +2130,27 @@
 #define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
 #define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
 #define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define   S_028818_VPORT_X_SCALE_ENA(x)                (((x) & 0x1) << 0)
+#define   G_028818_VPORT_X_SCALE_ENA(x)                (((x) >> 0 & 0x1)
+#define   C_028818_VPORT_X_SCALE_ENA                   0xFFFFFFFE
+#define   S_028818_VPORT_X_OFFSET_ENA(x)               (((x) & 0x1) << 1)
+#define   G_028818_VPORT_X_OFFSET_ENA(x)               (((x) >> 1 & 0x1)
+#define   C_028818_VPORT_X_OFFSET_ENA                  0xFFFFFFFD
+#define   S_028818_VPORT_Y_SCALE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_028818_VPORT_Y_SCALE_ENA(x)                (((x) >> 2 & 0x1)
+#define   C_028818_VPORT_Y_SCALE_ENA                   0xFFFFFFFB
+#define   S_028818_VPORT_Y_OFFSET_ENA(x)               (((x) & 0x1) << 3)
+#define   G_028818_VPORT_Y_OFFSET_ENA(x)               (((x) >> 3 & 0x1)
+#define   C_028818_VPORT_Y_OFFSET_ENA                  0xFFFFFFF7
+#define   S_028818_VPORT_Z_SCALE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_028818_VPORT_Z_SCALE_ENA(x)                (((x) >> 4 & 0x1)
+#define   C_028818_VPORT_Z_SCALE_ENA                   0xFFFFFFEF
+#define   S_028818_VPORT_Z_OFFSET_ENA(x)               (((x) & 0x1) << 5)
+#define   G_028818_VPORT_Z_OFFSET_ENA(x)               (((x) >> 5 & 0x1)
+#define   C_028818_VPORT_Z_OFFSET_ENA                  0xFFFFFFDF
+#define   S_028818_VTX_W0_FMT(x)                       (((x) & 0x1) << 10)
+#define   G_028818_VTX_W0_FMT(x)                       (((x) >> 10) & 0x1)
+#define   C_028818_VTX_W0_FMT                          0xFFFFFBFF
 #define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
 #define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
 #define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C
@@ -2199,6 +2216,12 @@
 #define R_0286C0_SPI_PS_INPUT_CNTL_31                0x0286C0
 #define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
 #define R_028854_SQ_PGM_EXPORTS_PS                   0x028854
+#define   S_028854_EXPORT_COLORS(x)                    (((x) & 0xF) << 1)
+#define   G_028854_EXPORT_COLORS(x)                    (((x) >> 1) & 0xF)
+#define   C_028854_EXPORT_COLORS                       0xFFFFFFE1
+#define   S_028854_EXPORT_Z(x)                         (((x) & 0x1) << 0)
+#define   G_028854_EXPORT_Z(x)                         (((x) >> 0) & 0x1)
+#define   C_028854_EXPORT_Z                            0xFFFFFFFE
 #define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
 #define R_028A7C_VGT_DMA_INDEX_TYPE                  0x028A7C
 #define R_028A88_VGT_DMA_NUM_INSTANCES               0x028A88
@@ -3435,6 +3458,16 @@
 #define R_038014_RESOURCE0_WORD5                     0x038014
 #define R_038018_RESOURCE0_WORD6                     0x038018
 
+#define R_028140_ALU_CONST_BUFFER_SIZE_PS_0          0x00028140
+#define R_028180_ALU_CONST_BUFFER_SIZE_VS_0          0x00028180
+#define R_028940_ALU_CONST_CACHE_PS_0                0x00028940
+#define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
+
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC                 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC               0x03CFF4
+
+#define R_03E200_SQ_LOOP_CONST_0                     0x3E200
+
 #define SQ_TEX_INST_LD 0x03
 #define SQ_TEX_INST_GET_GRADIENTS_H 0x7
 #define SQ_TEX_INST_GET_GRADIENTS_V 0x8
diff --git a/src/gallium/drivers/r600/r700_asm.c b/src/gallium/drivers/r600/r700_asm.c
index a78cf0ce95..892dee86ba 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -20,12 +20,11 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_context.h"
-#include "r600_asm.h"
+#include <stdio.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
+#include "r600_asm.h"
 #include "r700_sq.h"
-#include <stdio.h>
 
 
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
@@ -37,7 +36,7 @@ int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 		S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
 		S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
 		S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
-		S_SQ_ALU_WORD0_SRC0_REL(alu->src[1].rel) |
+		S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
 		S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
 		S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
 		S_SQ_ALU_WORD0_LAST(alu->last);
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
deleted file mode 100644
index 5f9f21db1b..0000000000
--- a/src/gallium/drivers/r600/radeon.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef RADEON_H
-#define RADEON_H
-
-#define RADEON_CTX_MAX_PM4	(64 * 1024 / 4)
-
-#include <stdint.h>
-
-#include <pipe/p_compiler.h>
-
-typedef uint64_t		u64;
-typedef uint32_t		u32;
-typedef uint16_t		u16;
-typedef uint8_t			u8;
-
-struct radeon;
-
-enum radeon_family {
-	CHIP_UNKNOWN,
-	CHIP_R100,
-	CHIP_RV100,
-	CHIP_RS100,
-	CHIP_RV200,
-	CHIP_RS200,
-	CHIP_R200,
-	CHIP_RV250,
-	CHIP_RS300,
-	CHIP_RV280,
-	CHIP_R300,
-	CHIP_R350,
-	CHIP_RV350,
-	CHIP_RV380,
-	CHIP_R420,
-	CHIP_R423,
-	CHIP_RV410,
-	CHIP_RS400,
-	CHIP_RS480,
-	CHIP_RS600,
-	CHIP_RS690,
-	CHIP_RS740,
-	CHIP_RV515,
-	CHIP_R520,
-	CHIP_RV530,
-	CHIP_RV560,
-	CHIP_RV570,
-	CHIP_R580,
-	CHIP_R600,
-	CHIP_RV610,
-	CHIP_RV630,
-	CHIP_RV670,
-	CHIP_RV620,
-	CHIP_RV635,
-	CHIP_RS780,
-	CHIP_RS880,
-	CHIP_RV770,
-	CHIP_RV730,
-	CHIP_RV710,
-	CHIP_RV740,
-	CHIP_CEDAR,
-	CHIP_REDWOOD,
-	CHIP_JUNIPER,
-	CHIP_CYPRESS,
-	CHIP_HEMLOCK,
-	CHIP_LAST,
-};
-
-enum {
-	R600_SHADER_PS = 1,
-	R600_SHADER_VS,
-	R600_SHADER_GS,
-	R600_SHADER_FS,
-	R600_SHADER_MAX = R600_SHADER_FS,
-};
-
-enum radeon_family radeon_get_family(struct radeon *rw);
-void radeon_set_mem_constant(struct radeon *radeon, boolean state);
-
-/* lowlevel WS bo */
-struct radeon_ws_bo;
-struct radeon_ws_bo *radeon_ws_bo(struct radeon *radeon,
-				  unsigned size, unsigned alignment, unsigned usage);
-struct radeon_ws_bo *radeon_ws_bo_handle(struct radeon *radeon,
-					 unsigned handle);
-void *radeon_ws_bo_map(struct radeon *radeon, struct radeon_ws_bo *bo, unsigned usage, void *ctx);
-void radeon_ws_bo_unmap(struct radeon *radeon, struct radeon_ws_bo *bo);
-void radeon_ws_bo_reference(struct radeon *radeon, struct radeon_ws_bo **dst,
-			    struct radeon_ws_bo *src);
-int radeon_ws_bo_wait(struct radeon *radeon, struct radeon_ws_bo *bo);
-
-struct radeon_stype_info;
-/*
- * states functions
- */
-struct radeon_state {
-	struct radeon			*radeon;
-	unsigned			refcount;
-	struct radeon_stype_info	*stype;
-	unsigned			state_id;
-	unsigned			id;
-	unsigned			shader_index;
-	unsigned			nstates;
-	u32				states[64];
-	unsigned			npm4;
-	unsigned			cpm4;
-	u32				pm4_crc;
-	u32				pm4[128];
-	unsigned			nbo;
-	struct radeon_ws_bo		*bo[4];
-	unsigned			nreloc;
-	unsigned			reloc_pm4_id[8];
-	unsigned			reloc_bo_id[8];
-	u32				placement[8];
-	unsigned			bo_dirty[4];
-};
-
-int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
-void radeon_state_fini(struct radeon_state *state);
-int radeon_state_pm4(struct radeon_state *state);
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
-
-/*
- * draw functions
- */
-struct radeon_draw {
-	struct radeon			*radeon;
-	struct radeon_state		**state;
-};
-
-int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
-void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
-void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
-
-/*
- * radeon context functions
- */
-#pragma pack(1)
-struct radeon_cs_reloc {
-	uint32_t	handle;
-	uint32_t	read_domain;
-	uint32_t	write_domain;
-	uint32_t	flags;
-};
-#pragma pack()
-
-struct radeon_ctx;
-
-struct radeon_ctx *radeon_ctx_init(struct radeon *radeon);
-void radeon_ctx_fini(struct radeon_ctx *ctx);
-void radeon_ctx_clear(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-
-/*
- * R600/R700
- */
-
-enum r600_stype {
-	R600_STATE_CONFIG,
-	R600_STATE_CB_CNTL,
-	R600_STATE_RASTERIZER,
-	R600_STATE_VIEWPORT,
-	R600_STATE_SCISSOR,
-	R600_STATE_BLEND,
-	R600_STATE_DSA,
-	R600_STATE_SHADER,          /* has PS,VS,GS,FS variants */
-	R600_STATE_CONSTANT,        /* has PS,VS,GS,FS variants */
-	R600_STATE_CBUF,        /* has PS,VS,GS,FS variants */
-	R600_STATE_RESOURCE,        /* has PS,VS,GS,FS variants */
-	R600_STATE_SAMPLER,         /* has PS,VS,GS,FS variants */
-	R600_STATE_SAMPLER_BORDER,  /* has PS,VS,GS,FS variants */
-	R600_STATE_CB0,
-	R600_STATE_CB1,
-	R600_STATE_CB2,
-	R600_STATE_CB3,
-	R600_STATE_CB4,
-	R600_STATE_CB5,
-	R600_STATE_CB6,
-	R600_STATE_CB7,
-	R600_STATE_DB,
-	R600_STATE_QUERY_BEGIN,
-	R600_STATE_QUERY_END,
-	R600_STATE_UCP,
-	R600_STATE_VGT,
-	R600_STATE_DRAW,
-	R600_STATE_CB_FLUSH,
-	R600_STATE_DB_FLUSH,
-	R600_STATE_MAX,
-};
-
-#include "r600_states_inc.h"
-#include "eg_states_inc.h"
-
-/* R600 QUERY BEGIN/END */
-#define R600_QUERY__OFFSET			0
-#define R600_QUERY_SIZE				1
-#define R600_QUERY_PM4				128
-
-void r600_flush_ctx(void *data);
-#endif