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| author | Eric Anholt <eric@anholt.net> | 2008-07-02 10:21:44 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2008-07-02 10:21:44 -0700 |
| commit | 4b3ed4d2d16811a624857519e95303017f4160b5 (patch) | |
| tree | fabe8a116da19f6d4fd636f38f9dafdfcee24465 /src/mesa/drivers/dri/i965/brw_misc_state.c | |
| parent | 19f585a3cf65887e249d630fe43e83e7e7618dfa (diff) | |
intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now
displays correctly.
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c')
0 files changed, 0 insertions, 0 deletions