Merge branch 'master' into asm-shader-rework-1

Conflicts:
	src/mesa/shader/arbprogparse.c

52 files changed, 1730 insertions, 992 deletions

diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile
index 2f225f7cb5..5bdc1afbf0 100644
--- a/src/mesa/drivers/dri/r600/Makefile
+++ b/src/mesa/drivers/dri/r600/Makefile
@@ -68,54 +68,10 @@ DRIVER_DEFINES = -DCOMPILE_R600 -DR200_MERGED=0 \
 #	-DRADEON_BO_TRACK \
 	-Wall
 
-SYMLINKS = \
-	server/radeon_dri.c \
-	server/radeon_dri.h \
-	server/radeon.h \
-	server/radeon_macros.h \
-	server/radeon_reg.h \
-	server/radeon_egl.c
-
-COMMON_SYMLINKS = \
-	radeon_chipset.h \
-	radeon_screen.c \
-	radeon_screen.h \
-	radeon_span.h \
-	radeon_span.c \
-	radeon_bo_legacy.c \
-	radeon_cs_legacy.c \
-	radeon_bo_legacy.h \
-	radeon_cs_legacy.h \
-	radeon_bocs_wrapper.h \
-	radeon_lock.c \
-	radeon_lock.h \
-	radeon_common.c \
-	radeon_common.h \
-	radeon_common_context.c \
-	radeon_common_context.h \
-	radeon_cmdbuf.h \
-	radeon_dma.c \
-	radeon_dma.h \
-	radeon_mipmap_tree.c \
-	radeon_mipmap_tree.h \
-	radeon_texture.c \
-	radeon_texture.h \
-	radeon_fbo.c \
-	$(CS_SOURCES)
-
 DRI_LIB_DEPS += $(RADEON_LDFLAGS)
 
 ##### TARGETS #####
 
 include ../Makefile.template
 
-server:
-	mkdir -p server
-
-$(SYMLINKS): server
-	@[ -e $@ ] || ln -sf ../../radeon/$@ server/
-
-$(COMMON_SYMLINKS):
-	@[ -e $@ ] || ln -sf ../radeon/$@ ./
-
-symlinks: $(SYMLINKS) $(COMMON_SYMLINKS)
+symlinks:
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.c b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
index 74fec02584..dc2fb0144a 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.c
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.c
@@ -78,8 +78,7 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
                         struct radeon_bo *bo,
                         uint32_t read_domain,
                         uint32_t write_domain,
-                        uint32_t flags,
-                        offset_modifiers* poffset_mod)
+                        uint32_t flags)
 {
     struct r600_cs_reloc_legacy *relocs;
     int i;
@@ -135,10 +134,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
             cs->section_ndw += 2;
             cs->section_cdw += 2;
 
-            relocs[i].offset_mod.shift     = poffset_mod->shift;
-            relocs[i].offset_mod.shiftbits = poffset_mod->shiftbits;
-            relocs[i].offset_mod.mask      = poffset_mod->mask;
-
             return 0;
         }
     }
@@ -160,9 +155,6 @@ int r600_cs_write_reloc(struct radeon_cs *cs,
     {
         return -ENOMEM;
     }
-    relocs[cs->crelocs].offset_mod.shift     = poffset_mod->shift;
-    relocs[cs->crelocs].offset_mod.shiftbits = poffset_mod->shiftbits;
-    relocs[cs->crelocs].offset_mod.mask      = poffset_mod->mask;
 
     relocs[cs->crelocs].indices[0] = cs->cdw - 1;
     relocs[cs->crelocs].reloc_indices[0] = cs->section_cdw;
@@ -255,65 +247,44 @@ static int r600_cs_process_relocs(struct radeon_cs *cs,
     csm = (struct r600_cs_manager_legacy*)cs->csm;
     relocs = (struct r600_cs_reloc_legacy *)cs->relocs;
 restart:
-    for (i = 0; i < cs->crelocs; i++) 
-    {
-        for (j = 0; j < relocs[i].cindices; j++) 
-        {
+    for (i = 0; i < cs->crelocs; i++) {
             uint32_t soffset, eoffset, asicoffset;
 
             r = radeon_bo_legacy_validate(relocs[i].base.bo,
-                                           &soffset, &eoffset);
-	        if (r == -EAGAIN)
-            {
-	             goto restart;
+					  &soffset, &eoffset);
+	    if (r == -EAGAIN) {
+		    goto restart;
             }
-            if (r) 
-            {
-                fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
-                        relocs[i].base.bo, soffset, eoffset);
-                return r;
+            if (r) {
+		    fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
+			    relocs[i].base.bo, soffset, eoffset);
+		    return r;
             }
             asicoffset = soffset;
-            if (asicoffset >= eoffset) 
-            {
-	      /*                radeon_bo_debug(relocs[i].base.bo, 12); */
-                fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
-                        relocs[i].base.bo, soffset, eoffset);
-                fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
-                        relocs[i].base.bo,
-                        cs->packets[relocs[i].indices[j]],
-                        eoffset);
-                exit(0);
-                return -EINVAL;
-            }
-            /* apply offset operator */
-            switch (relocs[i].offset_mod.shift)
-            {
-            case NO_SHIFT:
-                asicoffset = asicoffset & relocs[i].offset_mod.mask;
-                break;
-            case LEFT_SHIFT:
-                asicoffset = (asicoffset << relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask;
-                break;
-            case RIGHT_SHIFT:
-                asicoffset = (asicoffset >> relocs[i].offset_mod.shiftbits) & relocs[i].offset_mod.mask;
-                break;
-            default:
-                break;
-            };              
-
-            /* pkt3 nop header in ib chunk */
-            cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000;
-
-            /* reloc index in ib chunk */
-            cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw;
-            
-            /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
-            reloc_chunk[offset_dw] = asicoffset;
-            reloc_chunk[offset_dw + 3] = 0;
-
-            offset_dw += 4;
-        }
+
+	    for (j = 0; j < relocs[i].cindices; j++) {
+		    if (asicoffset >= eoffset) {
+			    /*                radeon_bo_debug(relocs[i].base.bo, 12); */
+			    fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
+				    relocs[i].base.bo, soffset, eoffset);
+			    fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
+				    relocs[i].base.bo,
+				    cs->packets[relocs[i].indices[j]],
+				    eoffset);
+			    exit(0);
+			    return -EINVAL;
+		    }
+		    /* pkt3 nop header in ib chunk */
+		    cs->packets[relocs[i].reloc_indices[j]] = 0xC0001000;
+		    /* reloc index in ib chunk */
+		    cs->packets[relocs[i].reloc_indices[j] + 1] = offset_dw;
+	    }
+
+	    /* asic offset in reloc chunk */ /* see alex drm r600_nomm_relocate */
+	    reloc_chunk[offset_dw] = asicoffset;
+	    reloc_chunk[offset_dw + 3] = 0;
+
+	    offset_dw += 4;
     }
 
     *length_dw_reloc_chunk = offset_dw;
@@ -351,10 +322,7 @@ static int r600_cs_emit(struct radeon_cs *cs)
     struct r600_cs_manager_legacy *csm = (struct r600_cs_manager_legacy*)cs->csm;
     struct drm_radeon_cs       cs_cmd;
     struct drm_radeon_cs_chunk cs_chunk[2];
-    drm_radeon_cmd_buffer_t cmd; 
-    /* drm_r300_cmd_header_t age; */
     uint32_t length_dw_reloc_chunk;
-    uint64_t ull;
     uint64_t chunk_ptrs[2];
     uint32_t reloc_chunk[128]; 
     int r;
@@ -363,43 +331,13 @@ static int r600_cs_emit(struct radeon_cs *cs)
     /* TODO : put chip level things here if need. */
     /* csm->ctx->vtbl.emit_cs_header(cs, csm->ctx); */
 
-    BATCH_LOCALS(csm->ctx);
-    drm_radeon_getparam_t gp;
-    uint32_t              current_scratchx_age;
-
-    gp.param = RADEON_PARAM_LAST_CLEAR;
-    gp.value = (int *)&current_scratchx_age;
-    r = drmCommandWriteRead(cs->csm->fd, 
-                            DRM_RADEON_GETPARAM,
-                            &gp, 
-                            sizeof(gp));
-    if (r) 
-    {
-        fprintf(stderr, "%s: drmRadeonGetParam: %d\n", __FUNCTION__, r);
-        exit(1);
-    }
-
-    csm->pending_age = 0;
     csm->pending_count = 1;
 
-    current_scratchx_age++;
-    csm->pending_age = current_scratchx_age;
-
-    BEGIN_BATCH_NO_AUTOSTATE(3);
-    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-    R600_OUT_BATCH((SCRATCH_REG2 - R600_SET_CONFIG_REG_OFFSET) >> 2);
-    R600_OUT_BATCH(current_scratchx_age);
-    END_BATCH();
-    COMMIT_BATCH();
-
-    //TODO ioctl to get back cs id assigned in drm
-    //csm->pending_age = cs_id_back;
-    
     r = r600_cs_process_relocs(cs, &(reloc_chunk[0]), &length_dw_reloc_chunk);
     if (r) {
         return 0;
     }
-      
+
     /* raw ib chunk */
     cs_chunk[0].chunk_id   = RADEON_CHUNK_ID_IB;
     cs_chunk[0].length_dw  = cs->cdw;
@@ -429,6 +367,8 @@ static int r600_cs_emit(struct radeon_cs *cs)
         return r;
     }
 
+    csm->pending_age = cs_cmd.cs_id;
+
     r600_cs_set_age(cs);
 
     cs->csm->read_used = 0;
@@ -514,8 +454,12 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
 void r600InitCmdBuf(context_t *r600) /* from rcommonInitCmdBuf */
 {
     radeonContextPtr rmesa = &r600->radeon;
-	
     GLuint size;
+    rmesa->hw.max_state_size = 4000; /* rough estimate */
+
+    rmesa->hw.all_dirty = GL_TRUE;
+    rmesa->hw.is_dirty = GL_TRUE;
+
 	/* Initialize command buffer */
 	size = 256 * driQueryOptioni(&rmesa->optionCache,
 				     "command_buffer_size");
diff --git a/src/mesa/drivers/dri/r600/r600_cmdbuf.h b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
index bd1ed7fdff..5df0cf1ab6 100644
--- a/src/mesa/drivers/dri/r600/r600_cmdbuf.h
+++ b/src/mesa/drivers/dri/r600/r600_cmdbuf.h
@@ -132,15 +132,13 @@ struct r600_cs_reloc_legacy {
     uint32_t                cindices;
     uint32_t                *indices;
     uint32_t                *reloc_indices;
-    struct offset_modifiers offset_mod;
 };
 
 extern int r600_cs_write_reloc(struct radeon_cs *cs,
                         struct radeon_bo *bo,
                         uint32_t read_domain,
                         uint32_t write_domain,
-                        uint32_t flags,
-                        offset_modifiers* poffset_mod);
+                        uint32_t flags);
 
 static inline void r600_cs_write_dword(struct radeon_cs *cs, uint32_t dword)
 {
@@ -171,7 +169,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
 /**
  * Write a relocated dword to the command buffer.
  */
-#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags, offset_mod) 	\
+#define R600_OUT_BATCH_RELOC(data, bo, offset, rd, wd, flags) 	\
 	do { 							\
         if (0 && offset) {					\
             fprintf(stderr, "(%s:%s:%d) offset : %d\n",		\
@@ -179,7 +177,7 @@ struct radeon_cs_manager * r600_radeon_cs_manager_legacy_ctor(struct radeon_cont
         }							\
         r600_cs_write_dword(b_l_rmesa->cmdbuf.cs, offset);	\
         r600_cs_write_reloc(b_l_rmesa->cmdbuf.cs, 		\
-                              bo, rd, wd, flags, offset_mod);		\
+                              bo, rd, wd, flags);		\
 	} while(0)
 
 /* R600/R700 */
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index 78bad8726b..7009374b0c 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -57,7 +57,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #include "drivers/common/driverfuncs.h"
 
 #include "r600_context.h"
-#include "radeon_context.h"
+#include "radeon_common_context.h"
 #include "radeon_span.h"
 #include "r600_cmdbuf.h"
 #include "r600_emit.h"
@@ -218,7 +218,6 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 	struct dd_function_table functions;
 	context_t *r600;
 	GLcontext *ctx;
-	int tcl_mode;
 
 	assert(glVisual);
 	assert(driContextPriv);
@@ -377,23 +376,12 @@ GLboolean r600CreateContext(const __GLcontextModes * glVisual,
 
 	TNL_CONTEXT(ctx)->Driver.RunPipeline = r600RunPipeline;
 
-	tcl_mode = driQueryOptioni(&r600->radeon.optionCache, "tcl_mode");
 	if (driQueryOptionb(&r600->radeon.optionCache, "no_rast")) {
 		fprintf(stderr, "disabling 3D acceleration\n");
 #if R200_MERGED
 		FALLBACK(&r600->radeon, RADEON_FALLBACK_DISABLE, 1);
 #endif
 	}
-	if (tcl_mode == DRI_CONF_TCL_SW ||
-	    !(r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
-		if (r600->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
-			r600->radeon.radeonScreen->chip_flags &=
-			    ~RADEON_CHIPSET_TCL;
-			fprintf(stderr, "Disabling HW TCL support\n");
-		}
-		TCL_FALLBACK(r600->radeon.glCtx,
-			     RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
-	}
 
 	return GL_TRUE;
 }
@@ -407,6 +395,8 @@ r600DestroyContext (__DRIcontextPrivate * driContextPriv)
 
     if (context)
 	    FREE(context->hw.pStateList);
+
+    radeonDestroyContext(driContextPriv);
 }
 
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h
index bcb33e1386..30ddce682c 100644
--- a/src/mesa/drivers/dri/r600/r600_context.h
+++ b/src/mesa/drivers/dri/r600/r600_context.h
@@ -128,13 +128,6 @@ enum
     RIGHT_SHIFT = 2,
 };
 
-typedef struct offset_modifiers
-{
-    GLuint shift;
-    GLuint shiftbits;
-    GLuint mask;
-} offset_modifiers;
-
 /**
  * \brief R600 context structure.
  */
@@ -165,6 +158,17 @@ extern GLboolean r700InitChipObject(context_t *context);
 extern GLboolean r700SendContextStates(context_t *context);
 extern GLboolean r700SendViewportState(context_t *context, int id);
 extern GLboolean r700SendRenderTargetState(context_t *context, int id);
+extern GLboolean r700SendTextureState(context_t *context);
+extern GLboolean r700SendDepthTargetState(context_t *context);
+extern GLboolean r700SendUCPState(context_t *context);
+extern GLboolean r700SendFSState(context_t *context);
+extern void r700EmitState(GLcontext * ctx);
+
+extern GLboolean r700SyncSurf(context_t *context,
+			      struct radeon_bo *pbo,
+			      uint32_t read_domain,
+			      uint32_t write_domain,
+			      uint32_t sync_type);
 
 extern int       r700SetupStreams(GLcontext * ctx);
 extern void      r700SetupVTXConstants(GLcontext  * ctx, 
diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c
index 685f7fe473..b695ed9583 100644
--- a/src/mesa/drivers/dri/r600/r600_emit.c
+++ b/src/mesa/drivers/dri/r600/r600_emit.c
@@ -63,26 +63,15 @@ GLboolean r600EmitShader(GLcontext * ctx,
     struct radeon_bo * pbo;
     uint32_t *out;
 
-shader_again_alloc:	
-#ifdef RADEON_DEBUG_BO
-	pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
-					     0, 
-                         sizeinDWORD * 4, 
-                         256, 
-                         RADEON_GEM_DOMAIN_GTT,
-					     0,
-                         szShaderUsage);
-#else
+shader_again_alloc:
     pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
-					     0, 
-                         sizeinDWORD * 4, 
-                         256, 
+			 0,
+                         sizeinDWORD * 4,
+                         256,
                          RADEON_GEM_DOMAIN_GTT,
-					     0);
-#endif /* RADEON_DEBUG_BO */
+			 0);
 
-	if (!pbo) 
-    {
+	if (!pbo) {
 		rcommonFlushCmdBuf(radeonctx, __FUNCTION__);
 		goto shader_again_alloc;
 	}
diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c
index 43d9f641af..6d531bf0f9 100644
--- a/src/mesa/drivers/dri/r600/r600_tex.c
+++ b/src/mesa/drivers/dri/r600/r600_tex.c
@@ -62,10 +62,10 @@ static unsigned int translate_wrap_mode(GLenum wrapmode)
 	case GL_CLAMP: return SQ_TEX_CLAMP_HALF_BORDER;
 	case GL_CLAMP_TO_EDGE: return SQ_TEX_CLAMP_LAST_TEXEL;
 	case GL_CLAMP_TO_BORDER: return SQ_TEX_CLAMP_BORDER;
-	case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
-	case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR;
-	case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
-	case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case GL_MIRRORED_REPEAT: return SQ_TEX_MIRROR;
+	case GL_MIRROR_CLAMP_EXT: return SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case GL_MIRROR_CLAMP_TO_EDGE_EXT: return SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case GL_MIRROR_CLAMP_TO_BORDER_EXT: return SQ_TEX_MIRROR_ONCE_BORDER;
 	default:
 		_mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
 		return 0;
@@ -127,10 +127,18 @@ static void r600SetTexDefaultState(radeonTexObjPtr t)
         SETfield(t->SQ_TEX_RESOURCE4, SQ_ENDIAN_NONE,
                  SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_shift, SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP_mask);
         SETfield(t->SQ_TEX_RESOURCE4, 1, REQUEST_SIZE_shift, REQUEST_SIZE_mask);
-        t->SQ_TEX_RESOURCE4 |= SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift
-		              |SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift
-		              |SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift
-		              |SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift;
+        SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+	SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+	SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+	SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift,
+		 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
         SETfield(t->SQ_TEX_RESOURCE4, 0, BASE_LEVEL_shift, BASE_LEVEL_mask); /* mip-maps */
 
         t->SQ_TEX_RESOURCE5 = 0;
@@ -141,17 +149,18 @@ static void r600SetTexDefaultState(radeonTexObjPtr t)
 
         /* Initialize sampler registers */
         t->SQ_TEX_SAMPLER0                           = 0;
-        t->SQ_TEX_SAMPLER0 |=
-                         SQ_TEX_WRAP << SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift
-                        |SQ_TEX_WRAP << CLAMP_Y_shift
-                        |SQ_TEX_WRAP << CLAMP_Z_shift
-                        |SQ_TEX_XY_FILTER_POINT << XY_MAG_FILTER_shift
-                        |SQ_TEX_XY_FILTER_POINT << XY_MIN_FILTER_shift
-                        |SQ_TEX_Z_FILTER_NONE << Z_FILTER_shift
-                        |SQ_TEX_Z_FILTER_NONE << MIP_FILTER_shift
-                        |SQ_TEX_BORDER_COLOR_TRANS_BLACK << BORDER_COLOR_TYPE_shift;
-
-        t->SQ_TEX_SAMPLER1 = 0x7FF << MAX_LOD_shift;
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift,
+		 SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Y_shift, CLAMP_Y_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_WRAP, CLAMP_Z_shift, CLAMP_Z_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MAG_FILTER_shift, XY_MAG_FILTER_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_XY_FILTER_POINT, XY_MIN_FILTER_shift, XY_MIN_FILTER_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, Z_FILTER_shift, Z_FILTER_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_Z_FILTER_NONE, MIP_FILTER_shift, MIP_FILTER_mask);
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_TRANS_BLACK, BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
+
+        t->SQ_TEX_SAMPLER1                           = 0;
+        SETfield(t->SQ_TEX_SAMPLER1, 0x3ff, MAX_LOD_shift, MAX_LOD_mask);
 
         t->SQ_TEX_SAMPLER2                          = 0;
         SETbit(t->SQ_TEX_SAMPLER2, SQ_TEX_SAMPLER_WORD2_0__TYPE_bit);
@@ -260,14 +269,12 @@ static void r600SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloa
 
 static void r600SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
 {
-#if 0
-	GLubyte c[4];
-	CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
-	CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
-	CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
-	CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
-	t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
-#endif
+	t->TD_PS_SAMPLER0_BORDER_ALPHA = *((uint32_t*)&(color[3]));
+	t->TD_PS_SAMPLER0_BORDER_RED = *((uint32_t*)&(color[2]));
+	t->TD_PS_SAMPLER0_BORDER_GREEN = *((uint32_t*)&(color[1]));
+	t->TD_PS_SAMPLER0_BORDER_BLUE = *((uint32_t*)&(color[0]));
+        SETfield(t->SQ_TEX_SAMPLER0, SQ_TEX_BORDER_COLOR_REGISTER,
+		 BORDER_COLOR_TYPE_shift, BORDER_COLOR_TYPE_mask);
 }
 
 /**
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 2466aa9595..ee9b64ee43 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -75,10 +75,10 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo
 {
 	radeonTexObj *t = radeon_tex_obj(tObj);
 
-	t->SQ_TEX_RESOURCE4 &= ~( SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask
-				  |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask
-				  |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask
-				  |SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask );
+	CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+	CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+	CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+	CLEARfield(t->SQ_TEX_RESOURCE4, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 
 	switch (mesa_format) /* This is mesa format. */
 	{
@@ -86,163 +86,211 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGBA8888_REV:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB8888:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB8888_REV:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB888:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB565:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB565_REV:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB4444:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB4444_REV:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB1555:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ARGB1555_REV:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_AL88:
 	case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB332:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_3_3_2,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_A8: /* ZERO, ZERO, ZERO, X */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_L8: /* X, X, X, ONE */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_I8: /* X, X, X, X */
 	case MESA_FORMAT_CI8:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 		/* YUV422 TODO conversion */  /* X, Y, Z, ONE, G8R8_G8B8 */
 		/*
@@ -272,121 +320,157 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGBA_FLOAT16:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB_FLOAT32: /* X, Y, Z, ONE */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_RGB_FLOAT16:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ALPHA_FLOAT32: /* ZERO, ZERO, ZERO, X */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_ALPHA_FLOAT16: /* ZERO, ZERO, ZERO, X */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_LUMINANCE_FLOAT32: /* X, X, X, ONE */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_LUMINANCE_FLOAT16: /* X, X, X, ONE */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_32_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_16_FLOAT,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		break;
 	case MESA_FORMAT_Z16:
 	case MESA_FORMAT_Z24_S8:
@@ -407,25 +491,34 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo
 		};
 		switch (tObj->DepthMode) {
 		case GL_LUMINANCE:  /* X, X, X, ONE */
-			t->SQ_TEX_RESOURCE4 |=
-				(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-				|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 			break;
 		case GL_INTENSITY:  /* X, X, X, X */
-			t->SQ_TEX_RESOURCE4 |=
-				(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 			break;
 		case GL_ALPHA:     /* ZERO, ZERO, ZERO, X */
-			t->SQ_TEX_RESOURCE4 |=
-				(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-				|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-				|(SQ_SEL_0 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_0,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 			break;
 		default:
 			return GL_FALSE;
@@ -441,7 +534,6 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, GLuint mesa_fo
 
 void r600SetDepthTexMode(struct gl_texture_object *tObj)
 {
-	const GLuint *format;
 	radeonTexObjPtr t;
 
 	if (!tObj)
@@ -464,7 +556,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 	radeonTexObj *t = radeon_tex_obj(texObj);
 	const struct gl_texture_image *firstImage;
 	int firstlevel = t->mt ? t->mt->firstLevel : 0;
-	GLuint uTexelPitch;
+	GLuint uTexelPitch, row_align;
 
 	firstImage = t->base.Image[0][firstlevel];
 
@@ -476,9 +568,6 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 		}
 	}
 
-	if (t->image_override && t->bo)
-		return;
-
 	switch (texObj->Target) {
         case GL_TEXTURE_1D:
 		SETfield(t->SQ_TEX_RESOURCE0, SQ_TEX_DIM_1D, DIM_shift, DIM_mask);
@@ -503,15 +592,26 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex
 		return;
 	}
 
-	uTexelPitch = (firstImage->Width + R700_TEXEL_PITCH_ALIGNMENT_MASK)
+	row_align = rmesa->radeon.texture_row_align - 1;
+	uTexelPitch = ((firstImage->Width * t->mt->bpp + row_align) & ~row_align) / t->mt->bpp;
+	uTexelPitch = (uTexelPitch + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
+	/* min pitch is 8 */
+	if (uTexelPitch < 8)
+		uTexelPitch = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (uTexelPitch/8)-1, PITCH_shift, PITCH_mask);
 	SETfield(t->SQ_TEX_RESOURCE0, firstImage->Width - 1,
 		 TEX_WIDTH_shift, TEX_WIDTH_mask);
 	SETfield(t->SQ_TEX_RESOURCE1, firstImage->Height - 1,
 		 TEX_HEIGHT_shift, TEX_HEIGHT_mask);
 
+	if ((t->mt->lastLevel - t->mt->firstLevel) > 0) {
+		t->SQ_TEX_RESOURCE3 = t->mt->levels[0].size / 256;
+		SETfield(t->SQ_TEX_RESOURCE4, t->mt->firstLevel, BASE_LEVEL_shift, BASE_LEVEL_mask);
+		SETfield(t->SQ_TEX_RESOURCE5, t->mt->lastLevel, LAST_LEVEL_shift, LAST_LEVEL_mask);
+	}
 }
 
 /**
@@ -598,7 +698,7 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 	struct gl_texture_object *tObj =
 	    _mesa_lookup_texture(rmesa->radeon.glCtx, texname);
 	radeonTexObjPtr t = radeon_tex_obj(tObj);
-	uint32_t pitch_val;
+	uint32_t pitch_val, size;
 
 	if (!tObj)
 		return;
@@ -608,7 +708,12 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 	if (!offset)
 		return;
 
-	t->bo = NULL;
+	size = pitch;//h * w * (depth / 8);
+	if (t->bo) {
+		radeon_bo_unref(t->bo);
+		t->bo = NULL;
+	}
+	t->bo = radeon_legacy_bo_alloc_fake(rmesa->radeon.radeonScreen->bom, size, offset);
 	t->override_offset = offset;
 	pitch_val = pitch;
 	switch (depth) {
@@ -616,11 +721,14 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		pitch_val /= 4;
 		break;
 	case 24:
@@ -628,28 +736,39 @@ void r600SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		pitch_val /= 4;
 		break;
 	case 16:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		pitch_val /= 2;
 		break;
 	}
 
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
+
+	/* min pitch is 8 */
+	if (pitch_val < 8)
+		pitch_val = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
 }
 
@@ -739,20 +858,26 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 			SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 				 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-			t->SQ_TEX_RESOURCE4 |=
-				(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-				|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-				|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-				|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		} else {
 			SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 				 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-			t->SQ_TEX_RESOURCE4 |=
-				(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-				|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-				|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-				|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		}
 		pitch_val /= 4;
 		break;
@@ -762,22 +887,28 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_W << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		pitch_val /= 4;
 		break;
 	case 2:
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
-		t->SQ_TEX_RESOURCE4 |=
-			(SQ_SEL_Z << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift)
-			|(SQ_SEL_Y << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift)
-			|(SQ_SEL_X << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift)
-			|(SQ_SEL_1 << SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+		SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+			 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		pitch_val /= 2;
 		break;
 	}
@@ -785,6 +916,10 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
+	/* min pitch is 8 */
+	if (pitch_val < 8)
+		pitch_val = 8;
+
 	SETfield(t->SQ_TEX_RESOURCE0, (pitch_val/8)-1, PITCH_shift, PITCH_mask);
 	SETfield(t->SQ_TEX_RESOURCE0, rb->base.Width - 1,
 		 TEX_WIDTH_shift, TEX_WIDTH_mask);
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 1d41c5cf78..eaacd06113 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1205,7 +1205,7 @@ GLboolean tex_src(r700_AssemblerBase *pAsm)
     return GL_TRUE;
 }
 
-GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm)
+GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized)
 {
     PVSSRC *   texture_coordinate_source;
     PVSSRC *   texture_unit_source;
@@ -1227,10 +1227,18 @@ GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm)
     tex_instruction_ptr->m_Word0.f.resource_id      = texture_unit_source->reg;
 
     tex_instruction_ptr->m_Word1.f.lod_bias     = 0x0;
-    tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED;
-    tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED;
-    tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED;
-    tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED;
+    if (normalized) {
+	    tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_NORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_NORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_NORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_NORMALIZED;
+    } else {
+	    /* XXX: UNNORMALIZED tex coords have limited wrap modes */
+	    tex_instruction_ptr->m_Word1.f.coord_type_x = SQ_TEX_UNNORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_y = SQ_TEX_UNNORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_z = SQ_TEX_UNNORMALIZED;
+	    tex_instruction_ptr->m_Word1.f.coord_type_w = SQ_TEX_UNNORMALIZED;
+    }
 
     tex_instruction_ptr->m_Word2.f.offset_x   = 0x0;
     tex_instruction_ptr->m_Word2.f.offset_y   = 0x0;
@@ -2196,11 +2204,19 @@ GLboolean next_ins(r700_AssemblerBase *pAsm)
 
     if( GL_TRUE == IsTex(pILInst->Opcode) )
     {
-        if( GL_FALSE == assemble_tex_instruction(pAsm) ) 
-        {
-            r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction");
-            return GL_FALSE;
-        }
+	    if (pILInst->TexSrcTarget == TEXTURE_RECT_INDEX) {
+		    if( GL_FALSE == assemble_tex_instruction(pAsm, GL_FALSE) ) 
+		    {
+			    r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction");
+			    return GL_FALSE;
+		    }
+	    } else {
+		    if( GL_FALSE == assemble_tex_instruction(pAsm, GL_TRUE) ) 
+		    {
+			    r700_error(ERROR_ASM_TEXINSTRUCTION, "Error assembling TEX instruction");
+			    return GL_FALSE;
+		    }
+	    }
     }
     else 
     {   //ALU      
@@ -3823,6 +3839,9 @@ GLboolean Process_Export(r700_AssemblerBase* pAsm,
     if (export_count == 1) 
     {
         ucWriteMask = pAsm->pucOutMask[starting_register_number - pAsm->starting_export_register_number];
+	/* exports Z as a float into Red channel */
+	if (GL_TRUE == is_depth_export)
+	    ucWriteMask = 0x1;
 
         if( (ucWriteMask & 0x1) != 0)
         {
@@ -4014,6 +4033,22 @@ GLboolean Process_Vertex_Exports(r700_AssemblerBase *pR700AsmCode,
         export_starting_index++;
 	}
 
+        unBit = 1 << VERT_RESULT_FOGC;
+        if(OutputsWritten & unBit)
+        {
+        if( GL_FALSE == Process_Export(pR700AsmCode,
+                                       SQ_EXPORT_PARAM,
+                                       export_starting_index,
+                                       1,
+                                       pR700AsmCode->ucVP_OutputMap[VERT_RESULT_FOGC],
+                                       GL_FALSE) )
+        {
+            return GL_FALSE;
+        }
+
+        export_starting_index++;
+        }
+
 	for(i=0; i<8; i++)
 	{
 		unBit = 1 << (VERT_RESULT_TEX0 + i);
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h
index e9b21b802e..f9c4d849c6 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.h
+++ b/src/mesa/drivers/dri/r600/r700_assembler.h
@@ -424,7 +424,7 @@ GLboolean assemble_src(r700_AssemblerBase *pAsm,
 GLboolean assemble_dst(r700_AssemblerBase *pAsm);
 GLboolean tex_dst(r700_AssemblerBase *pAsm);
 GLboolean tex_src(r700_AssemblerBase *pAsm);
-GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm);
+GLboolean assemble_tex_instruction(r700_AssemblerBase *pAsm, GLboolean normalized);
 void initialize(r700_AssemblerBase *pAsm);
 GLboolean assemble_alu_src(R700ALUInstruction*  alu_instruction_ptr,
                            int                  source_index,
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 087d17312e..0fb355a0b6 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -38,6 +38,8 @@
 #include "r700_vertprog.h"
 #include "r700_ioctl.h"
 
+#include "radeon_mipmap_tree.h"
+
 #define LINK_STATES(reg)                                            \
 do                                                                  \
 {                                                                   \
@@ -136,9 +138,23 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(CB_CLRCMP_MSK);
     LINK_STATES(CB_BLEND_CONTROL);
 
+    //DB
+    LINK_STATES(DB_HTILE_DATA_BASE);
+    LINK_STATES(DB_STENCIL_CLEAR);
+    LINK_STATES(DB_DEPTH_CLEAR);
+    LINK_STATES(DB_STENCILREFMASK);
+    LINK_STATES(DB_STENCILREFMASK_BF);
+    LINK_STATES(DB_DEPTH_CONTROL);
+    LINK_STATES(DB_SHADER_CONTROL);
+    LINK_STATES(DB_RENDER_CONTROL);
+    LINK_STATES(DB_RENDER_OVERRIDE);
+    LINK_STATES(DB_HTILE_SURFACE);
+    LINK_STATES(DB_ALPHA_TO_MASK);
+
     // SX
     LINK_STATES(SX_MISC);
     LINK_STATES(SX_ALPHA_TEST_CONTROL);
+    LINK_STATES(SX_ALPHA_REF);
 
     // VGT
     LINK_STATES(VGT_MAX_VTX_INDX);
@@ -159,7 +175,6 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
     LINK_STATES(VGT_GS_MODE);
     LINK_STATES(VGT_PRIMITIVEID_EN);
-    LINK_STATES(VGT_DMA_NUM_INSTANCES);
     LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN);
     LINK_STATES(VGT_INSTANCE_STEP_RATE_0);
     LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
@@ -213,39 +228,6 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(SPI_VS_OUT_ID_8);
     LINK_STATES(SPI_VS_OUT_ID_9);
 
-    LINK_STATES(SPI_PS_INPUT_CNTL_0);
-    LINK_STATES(SPI_PS_INPUT_CNTL_1);
-    LINK_STATES(SPI_PS_INPUT_CNTL_2);
-    LINK_STATES(SPI_PS_INPUT_CNTL_3);
-    LINK_STATES(SPI_PS_INPUT_CNTL_4);
-    LINK_STATES(SPI_PS_INPUT_CNTL_5);
-    LINK_STATES(SPI_PS_INPUT_CNTL_6);
-    LINK_STATES(SPI_PS_INPUT_CNTL_7);
-    LINK_STATES(SPI_PS_INPUT_CNTL_8);
-    LINK_STATES(SPI_PS_INPUT_CNTL_9);
-    LINK_STATES(SPI_PS_INPUT_CNTL_10);
-    LINK_STATES(SPI_PS_INPUT_CNTL_11);
-    LINK_STATES(SPI_PS_INPUT_CNTL_12);
-    LINK_STATES(SPI_PS_INPUT_CNTL_13);
-    LINK_STATES(SPI_PS_INPUT_CNTL_14);
-    LINK_STATES(SPI_PS_INPUT_CNTL_15);
-    LINK_STATES(SPI_PS_INPUT_CNTL_16);
-    LINK_STATES(SPI_PS_INPUT_CNTL_17);
-    LINK_STATES(SPI_PS_INPUT_CNTL_18);
-    LINK_STATES(SPI_PS_INPUT_CNTL_19);
-    LINK_STATES(SPI_PS_INPUT_CNTL_20);
-    LINK_STATES(SPI_PS_INPUT_CNTL_21);
-    LINK_STATES(SPI_PS_INPUT_CNTL_22);
-    LINK_STATES(SPI_PS_INPUT_CNTL_23);
-    LINK_STATES(SPI_PS_INPUT_CNTL_24);
-    LINK_STATES(SPI_PS_INPUT_CNTL_25);
-    LINK_STATES(SPI_PS_INPUT_CNTL_26);
-    LINK_STATES(SPI_PS_INPUT_CNTL_27);
-    LINK_STATES(SPI_PS_INPUT_CNTL_28);
-    LINK_STATES(SPI_PS_INPUT_CNTL_29);
-    LINK_STATES(SPI_PS_INPUT_CNTL_30);
-    LINK_STATES(SPI_PS_INPUT_CNTL_31);
-
     LINK_STATES(SPI_VS_OUT_CONFIG);
     LINK_STATES(SPI_THREAD_GROUPING);
     LINK_STATES(SPI_PS_IN_CONTROL_0);
@@ -274,6 +256,67 @@ GLboolean r700InitChipObject(context_t *context)
     return GL_TRUE;
 }
 
+GLboolean r700SendTextureState(context_t *context)
+{
+    unsigned int i;
+    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+    struct radeon_bo *bo = NULL;
+    BATCH_LOCALS(&context->radeon);
+
+    for (i=0; i<R700_TEXTURE_NUMBERUNITS; i++) {
+	    radeonTexObj *t = r700->textures[i];
+	    if (t) {
+		    if (!t->image_override)
+			    bo = t->mt->bo;
+		    else
+			    bo = t->bo;
+		    if (bo) {
+
+			    r700SyncSurf(context, bo,
+					 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
+					 0, TC_ACTION_ENA_bit);
+
+			    BEGIN_BATCH_NO_AUTOSTATE(9);
+			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
+			    R600_OUT_BATCH(i * 7);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
+			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
+						 bo,
+						 0,
+						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
+						 bo,
+						 r700->textures[i]->SQ_TEX_RESOURCE3,
+						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
+			    END_BATCH();
+
+			    BEGIN_BATCH_NO_AUTOSTATE(5);
+			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
+			    R600_OUT_BATCH(i * 3);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
+			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
+			    END_BATCH();
+
+			    BEGIN_BATCH_NO_AUTOSTATE(2 + 4);
+			    R600_OUT_BATCH_REGSEQ((TD_PS_SAMPLER0_BORDER_RED + (i * 16)), 4);
+			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_RED);
+			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_GREEN);
+			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_BLUE);
+			    R600_OUT_BATCH(r700->textures[i]->TD_PS_SAMPLER0_BORDER_ALPHA);
+			    END_BATCH();
+
+			    COMMIT_BATCH();
+		    }
+	    }
+    }
+    return GL_TRUE;
+}
+
 void r700SetupVTXConstants(GLcontext  * ctx,
 			   unsigned int nStreamID,
 			   void *       pAos,
@@ -282,10 +325,7 @@ void r700SetupVTXConstants(GLcontext  * ctx,
 			   unsigned int count)     /* number of vectors in stream */
 {
     context_t *context = R700_CONTEXT(ctx);
-    uint32_t *dest;
     struct radeon_aos * paos = (struct radeon_aos *)pAos;
-    offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
-
     BATCH_LOCALS(&context->radeon);
 
     unsigned int uSQ_VTX_CONSTANT_WORD0_0;
@@ -294,6 +334,9 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     unsigned int uSQ_VTX_CONSTANT_WORD3_0 = 0;
     unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0;
 
+    if (!paos->bo)
+	    return;
+
     if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
 	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
@@ -305,15 +348,19 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
     uSQ_VTX_CONSTANT_WORD1_0 = count * (size * 4) - 1;
 
-    uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */
-	    |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift
-	    |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */
-	    |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift
-	    |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit;
-
-    uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift;
+    SETfield(uSQ_VTX_CONSTANT_WORD2_0, 0, BASE_ADDRESS_HI_shift, BASE_ADDRESS_HI_mask); /* TODO */
+    SETfield(uSQ_VTX_CONSTANT_WORD2_0, stride, SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift,
+	     SQ_VTX_CONSTANT_WORD2_0__STRIDE_mask);
+    SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(GL_FLOAT, size, NULL),
+	     SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
+	     SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
+    SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_SCALED,
+	     SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift, SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_mask);
+    SETbit(uSQ_VTX_CONSTANT_WORD2_0, SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit);
 
-    uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift;
+    SETfield(uSQ_VTX_CONSTANT_WORD3_0, 1, MEM_REQUEST_SIZE_shift, MEM_REQUEST_SIZE_mask);
+    SETfield(uSQ_VTX_CONSTANT_WORD6_0, SQ_TEX_VTX_VALID_BUFFER,
+	     SQ_TEX_RESOURCE_WORD6_0__TYPE_shift, SQ_TEX_RESOURCE_WORD6_0__TYPE_mask);
 
     BEGIN_BATCH_NO_AUTOSTATE(9);
 
@@ -323,7 +370,7 @@ void r700SetupVTXConstants(GLcontext  * ctx,
     R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0,
                          paos->bo,
                          uSQ_VTX_CONSTANT_WORD0_0,
-                         RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+                         RADEON_GEM_DOMAIN_GTT, 0, 0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0);
     R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0);
@@ -339,7 +386,6 @@ void r700SetupVTXConstants(GLcontext  * ctx,
 int r700SetupStreams(GLcontext * ctx)
 {
     context_t         *context = R700_CONTEXT(ctx);
-
     BATCH_LOCALS(&context->radeon);
 
     struct r700_vertex_program *vpc
@@ -353,7 +399,7 @@ int r700SetupStreams(GLcontext * ctx)
 
     BEGIN_BATCH_NO_AUTOSTATE(6);
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-	R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+    R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
     R600_OUT_BATCH(0);
 
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
@@ -431,17 +477,37 @@ GLboolean r700SendContextStates(context_t *context)
         };
         END_BATCH();
     };
+
+    /* todo:
+     * - split this into a separate function?
+     * - only emit the ones we use
+     */
+    BEGIN_BATCH_NO_AUTOSTATE(2 + R700_MAX_SHADER_EXPORTS);
+    R600_OUT_BATCH_REGSEQ(SPI_PS_INPUT_CNTL_0, R700_MAX_SHADER_EXPORTS);
+    for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
+	    R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
+    END_BATCH();
+
+    if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
+	    for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
+		    if (r700->render_target[ui].enabled) {
+			    BEGIN_BATCH_NO_AUTOSTATE(3);
+			    R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
+						  r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
+			    END_BATCH();
+		    }
+	    }
+    }
+
     COMMIT_BATCH();
 
     return GL_TRUE;
 }
 
-
-GLboolean r700SendDepthTargetState(context_t *context, int id)
+GLboolean r700SendDepthTargetState(context_t *context)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	struct radeon_renderbuffer *rrb;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	rrb = radeon_get_depthbuffer(&context->radeon);
@@ -450,42 +516,25 @@ GLboolean r700SendDepthTargetState(context_t *context, int id)
 		return GL_FALSE;
 	}
 
-	offset_mod.shift     = NO_SHIFT;
-	offset_mod.shiftbits = 0;
-	offset_mod.mask      = 0xFFFFFFFF;
-
-        BEGIN_BATCH_NO_AUTOSTATE(9);
+        BEGIN_BATCH_NO_AUTOSTATE(8);
 	R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
 	R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
 	R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
-	R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 3);
+	R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
 	R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 			     rrb->bo,
 			     r700->DB_DEPTH_BASE.u32All,
-			     0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+			     0, RADEON_GEM_DOMAIN_VRAM, 0);
 	R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
-	R600_OUT_BATCH(r700->DB_HTILE_DATA_BASE.u32All);
         END_BATCH();
 
-        BEGIN_BATCH_NO_AUTOSTATE(24);
-	R600_OUT_BATCH_REGSEQ(DB_STENCIL_CLEAR, 2);
-	R600_OUT_BATCH(r700->DB_STENCIL_CLEAR.u32All);
-	R600_OUT_BATCH(r700->DB_DEPTH_CLEAR.u32All);
-
-	R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK.u32All);
-	R600_OUT_BATCH(r700->DB_STENCILREFMASK_BF.u32All);
-
-	R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, r700->DB_DEPTH_CONTROL.u32All);
-	R600_OUT_BATCH_REGVAL(DB_SHADER_CONTROL, r700->DB_SHADER_CONTROL.u32All);
-
-	R600_OUT_BATCH_REGSEQ(DB_RENDER_CONTROL, 2);
-	R600_OUT_BATCH(r700->DB_RENDER_CONTROL.u32All);
-	R600_OUT_BATCH(r700->DB_RENDER_OVERRIDE.u32All);
-
-	R600_OUT_BATCH_REGVAL(DB_HTILE_SURFACE, r700->DB_HTILE_SURFACE.u32All);
-	R600_OUT_BATCH_REGVAL(DB_ALPHA_TO_MASK, r700->DB_ALPHA_TO_MASK.u32All);
-        END_BATCH();
+	if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
+	    (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
+		BEGIN_BATCH_NO_AUTOSTATE(2);
+		R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
+		R600_OUT_BATCH(1 << 0);
+		END_BATCH();
+	}
 
 	COMMIT_BATCH();
 
@@ -499,7 +548,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
 	struct radeon_renderbuffer *rrb;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	rrb = radeon_get_colorbuffer(&context->radeon);
@@ -514,16 +562,12 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
 	if (!r700->render_target[id].enabled)
 		return GL_FALSE;
 
-	offset_mod.shift     = NO_SHIFT;
-	offset_mod.shiftbits = 0;
-	offset_mod.mask      = 0xFFFFFFFF;
-
         BEGIN_BATCH_NO_AUTOSTATE(3);
 	R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1);
 	R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
 			     rrb->bo,
 			     r700->render_target[id].CB_COLOR0_BASE.u32All,
-			     0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod);
+			     0, RADEON_GEM_DOMAIN_VRAM, 0);
         END_BATCH();
 
 	if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
@@ -543,12 +587,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
 	R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
         END_BATCH();
 
-	if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
-		BEGIN_BATCH_NO_AUTOSTATE(3);
-		R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All);
-		END_BATCH();
-	}
-
 	COMMIT_BATCH();
 
 	r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
@@ -560,16 +598,13 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
 GLboolean r700SendPSState(context_t *context)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
-	struct radeon_renderbuffer *rrb;
 	struct radeon_bo * pbo;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context));
 
-	offset_mod.shift     = NO_SHIFT;
-	offset_mod.shiftbits = 0;
-	offset_mod.mask      = 0xFFFFFFFF;
+	if (!pbo)
+		return GL_FALSE;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -578,7 +613,7 @@ GLboolean r700SendPSState(context_t *context)
 	R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All,
 			     pbo,
 			     r700->ps.SQ_PGM_START_PS.u32All,
-			     RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+			     RADEON_GEM_DOMAIN_GTT, 0, 0);
 	END_BATCH();
 
         BEGIN_BATCH_NO_AUTOSTATE(9);
@@ -595,16 +630,13 @@ GLboolean r700SendPSState(context_t *context)
 GLboolean r700SendVSState(context_t *context)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
-	struct radeon_renderbuffer *rrb;
 	struct radeon_bo * pbo;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context));
 
-	offset_mod.shift     = NO_SHIFT;
-	offset_mod.shiftbits = 0;
-	offset_mod.mask      = 0xFFFFFFFF;
+	if (!pbo)
+		return GL_FALSE;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -613,7 +645,7 @@ GLboolean r700SendVSState(context_t *context)
 	R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All,
 			     pbo,
 			     r700->vs.SQ_PGM_START_VS.u32All,
-			     RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+			     RADEON_GEM_DOMAIN_GTT, 0, 0);
 	END_BATCH();
 
         BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -629,9 +661,7 @@ GLboolean r700SendVSState(context_t *context)
 GLboolean r700SendFSState(context_t *context)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
-	struct radeon_renderbuffer *rrb;
 	struct radeon_bo * pbo;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	/* XXX fixme
@@ -645,9 +675,8 @@ GLboolean r700SendFSState(context_t *context)
 	r700->fs.SQ_PGM_CF_OFFSET_FS.u32All = 0;
 	/* XXX */
 
-	offset_mod.shift     = NO_SHIFT;
-	offset_mod.shiftbits = 0;
-	offset_mod.mask      = 0xFFFFFFFF;
+	if (!pbo)
+		return GL_FALSE;
 
 	r700SyncSurf(context, pbo, RADEON_GEM_DOMAIN_GTT, 0, SH_ACTION_ENA_bit);
 
@@ -656,7 +685,7 @@ GLboolean r700SendFSState(context_t *context)
 	R600_OUT_BATCH_RELOC(r700->fs.SQ_PGM_START_FS.u32All,
 			     pbo,
 			     r700->fs.SQ_PGM_START_FS.u32All,
-			     RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod);
+			     RADEON_GEM_DOMAIN_GTT, 0, 0);
 	END_BATCH();
 
         BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -672,8 +701,6 @@ GLboolean r700SendFSState(context_t *context)
 GLboolean r700SendViewportState(context_t *context, int id)
 {
 	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
-	struct radeon_renderbuffer *rrb;
-	offset_modifiers offset_mod;
 	BATCH_LOCALS(&context->radeon);
 
 	if (id > R700_MAX_VIEWPORTS)
@@ -722,3 +749,25 @@ GLboolean r700SendSQConfig(context_t *context)
 	return GL_TRUE;
 }
 
+GLboolean r700SendUCPState(context_t *context)
+{
+	R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+	BATCH_LOCALS(&context->radeon);
+	int i;
+
+	for (i = 0; i < R700_MAX_UCP; i++) {
+		if (r700->ucp[i].enabled) {
+			BEGIN_BATCH_NO_AUTOSTATE(6);
+			R600_OUT_BATCH_REGSEQ(PA_CL_UCP_0_X + (16 * i), 4);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_X.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Y.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_Z.u32All);
+			R600_OUT_BATCH(r700->ucp[i].PA_CL_UCP_0_W.u32All);
+			END_BATCH();
+			COMMIT_BATCH();
+		}
+	}
+
+	return GL_TRUE;
+}
+
diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index 04af4bc3b9..4e89c75f2f 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -372,6 +372,7 @@ typedef struct _R700_CHIP_CONTEXT
 	// SX
 	union UINT_FLOAT                SX_MISC                   ;  /* 0xA0D4 */
 	union UINT_FLOAT     	        SX_ALPHA_TEST_CONTROL     ;  /* 0xA104 */
+	union UINT_FLOAT     	        SX_ALPHA_REF              ;  /* 0xA10E */
 
 	// VGT
 	union UINT_FLOAT          	VGT_MAX_VTX_INDX          ;  /* 0xA100 */
@@ -392,7 +393,6 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT      	        VGT_GROUP_VECT_1_FMT_CNTL ;  /* 0xA28F */
 	union UINT_FLOAT               	VGT_GS_MODE               ;  /* 0xA290 */
 	union UINT_FLOAT        	VGT_PRIMITIVEID_EN        ;  /* 0xA2A1 */
-	union UINT_FLOAT     	        VGT_DMA_NUM_INSTANCES     ;  /* 0xA2A2 */
 	union UINT_FLOAT	        VGT_MULTI_PRIM_IB_RESET_EN;  /* 0xA2A5 */
 	union UINT_FLOAT  	        VGT_INSTANCE_STEP_RATE_0  ;  /* 0xA2A8 */
 	union UINT_FLOAT  	        VGT_INSTANCE_STEP_RATE_1  ;  /* 0xA2A9 */
@@ -422,7 +422,7 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT              	SPI_FOG_FUNC_SCALE        ;  /* 0xA1B8 */
 	union UINT_FLOAT              	SPI_FOG_FUNC_BIAS         ;  /* 0xA1B9 */
 
-    union UINT_FLOAT         	SQ_VTX_SEMANTIC_0         ;  /* 0xA0E0 */
+	union UINT_FLOAT         	SQ_VTX_SEMANTIC_0         ;  /* 0xA0E0 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_1         ;  /* 0xA0E1 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_2         ;  /* 0xA0E2 */
 	union UINT_FLOAT         	SQ_VTX_SEMANTIC_3         ;  /* 0xA0E3 */
@@ -455,38 +455,7 @@ typedef struct _R700_CHIP_CONTEXT
 	union UINT_FLOAT        	SQ_VTX_SEMANTIC_30        ;  /* 0xA0FE */
 	union UINT_FLOAT        	SQ_VTX_SEMANTIC_31        ;  /* 0xA0FF */
 
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_0       ;  /* 0xA191 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_1       ;  /* 0xA192 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_2       ;  /* 0xA193 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_3       ;  /* 0xA194 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_4       ;  /* 0xA195 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_5       ;  /* 0xA196 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_6       ;  /* 0xA197 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_7       ;  /* 0xA198 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_8       ;  /* 0xA199 */
-	union UINT_FLOAT       	SPI_PS_INPUT_CNTL_9       ;  /* 0xA19A */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_10      ;  /* 0xA19B */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_11      ;  /* 0xA19C */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_12      ;  /* 0xA19D */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_13      ;  /* 0xA19E */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_14      ;  /* 0xA19F */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_15      ;  /* 0xA1A0 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_16      ;  /* 0xA1A1 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_17      ;  /* 0xA1A2 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_18      ;  /* 0xA1A3 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_19      ;  /* 0xA1A4 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_20      ;  /* 0xA1A5 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_21      ;  /* 0xA1A6 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_22      ;  /* 0xA1A7 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_23      ;  /* 0xA1A8 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_24      ;  /* 0xA1A9 */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_25      ;  /* 0xA1AA */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_26      ;  /* 0xA1AB */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_27      ;  /* 0xA1AC */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_28      ;  /* 0xA1AD */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_29      ;  /* 0xA1AE */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_30      ;  /* 0xA1AF */
-	union UINT_FLOAT      	SPI_PS_INPUT_CNTL_31      ;  /* 0xA1B0 */
+	union UINT_FLOAT       	SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
 
 	// shaders
 	PS_STATE_STRUCT                 ps;
diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c
index e84be38622..05d4af331e 100644
--- a/src/mesa/drivers/dri/r600/r700_clear.c
+++ b/src/mesa/drivers/dri/r600/r700_clear.c
@@ -31,6 +31,7 @@
 #include "main/imports.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
+#include "swrast/swrast.h"
 
 #include "radeon_lock.h"
 #include "r600_context.h"
diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c
index 44de2aebee..6249bde6f1 100644
--- a/src/mesa/drivers/dri/r600/r700_fragprog.c
+++ b/src/mesa/drivers/dri/r600/r700_fragprog.c
@@ -55,6 +55,12 @@ void Map_Fragment_Program(r700_AssemblerBase         *pAsm,
 //Input mapping : mesa_fp->Base.InputsRead set the flag, set in 
 	//The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
 	//MUST match order in Map_Vertex_Output
+	unBit = 1 << FRAG_ATTRIB_WPOS;
+	if(mesa_fp->Base.InputsRead & unBit)
+	{
+		pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
+	}
+
 	unBit = 1 << FRAG_ATTRIB_COL0;
 	if(mesa_fp->Base.InputsRead & unBit)
 	{
@@ -67,6 +73,12 @@ void Map_Fragment_Program(r700_AssemblerBase         *pAsm,
 		pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
 	}
 
+        unBit = 1 << FRAG_ATTRIB_FOGC;
+        if(mesa_fp->Base.InputsRead & unBit)
+        {
+                pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
+        }
+
 	for(i=0; i<8; i++)
 	{
 		unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
@@ -106,6 +118,7 @@ void Map_Fragment_Program(r700_AssemblerBase         *pAsm,
 		pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
 		pAsm->number_of_exports++;
 		pAsm->number_of_colorandz_exports++;
+		pAsm->pR700Shader->depthIsExported = 1;
 	}
 
     pAsm->pucOutMask = (unsigned char*) MALLOC(pAsm->number_of_exports);    
@@ -255,20 +268,19 @@ void * r700GetActiveFpShaderBo(GLcontext * ctx)
 
 GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 {
-    context_t *context = R700_CONTEXT(ctx);   
-    BATCH_LOCALS(&context->radeon);
-    
+    context_t *context = R700_CONTEXT(ctx);
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
+    BATCH_LOCALS(&context->radeon);
     struct r700_fragment_program *fp = (struct r700_fragment_program *)
 	                                   (ctx->FragmentProgram._Current);
-
+    r700_AssemblerBase         *pAsm = &(fp->r700AsmCode);
+    struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
     struct gl_program_parameter_list *paramList;
     unsigned int unNumParamData;
-    unsigned int ui;
-
+    unsigned int ui, i;
     unsigned int unNumOfReg;
-    
+    unsigned int unBit;
+
     if(GL_FALSE == fp->loaded)
     {
         if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
@@ -277,11 +289,11 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 	    }
 
         /* Load fp to gpu */
-        r600EmitShader(ctx, 
-                       &(fp->shaderbo), 
+        r600EmitShader(ctx,
+                       &(fp->shaderbo),
                        (GLvoid *)(fp->r700Shader.pProgram),
                        fp->r700Shader.uShaderBinaryDWORDSize,
-                       "FS");    			                
+                       "FS");
 
         fp->loaded = GL_TRUE;
     }
@@ -299,7 +311,17 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
 
     ui = (r700->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
 
-    ui = ui ? ui : unNumOfReg;
+    /* PS uses fragment.position */
+    if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
+    {
+        ui += 1;
+        SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
+        SETfield(r700->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
+        SETbit(r700->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
+        SETbit(r700->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
+    }
+
+    ui = (unNumOfReg < ui) ? ui : unNumOfReg;
 
     SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); 
     
@@ -333,7 +355,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
     }
 
     /* sent out shader constants. */
-
     paramList = fp->mesa_program.Base.Parameters;
 
     if(NULL != paramList)
@@ -343,7 +364,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
         unNumParamData = paramList->NumParameters * 4;
 
         BEGIN_BATCH_NO_AUTOSTATE(2 + unNumParamData);
-        
+
         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
 
         /* assembler map const from very beginning. */
@@ -362,8 +383,72 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
         COMMIT_BATCH();
     }
 
-    return GL_TRUE;
-}
+    // emit ps input map
+    unBit = 1 << FRAG_ATTRIB_WPOS;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+            ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
+            SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+            SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+                     SEMANTIC_shift, SEMANTIC_mask);
+            if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+                    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+            else
+                    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
+
+    unBit = 1 << FRAG_ATTRIB_COL0;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+	    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
+	    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+	    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+		     SEMANTIC_shift, SEMANTIC_mask);
+	    if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    else
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
+
+    unBit = 1 << FRAG_ATTRIB_COL1;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+	    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
+	    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+	    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+		     SEMANTIC_shift, SEMANTIC_mask);
+	    if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    else
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
 
+    unBit = 1 << FRAG_ATTRIB_FOGC;
+    if(mesa_fp->Base.InputsRead & unBit)
+    {
+            ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
+            SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+            SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+                     SEMANTIC_shift, SEMANTIC_mask);
+            if (r700->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
+                    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+            else
+                    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+    }
+
+    for(i=0; i<8; i++)
+    {
+	    unBit = 1 << (FRAG_ATTRIB_TEX0 + i);
+	    if(mesa_fp->Base.InputsRead & unBit)
+	    {
+		    ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
+		    SETbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
+		    SETfield(r700->SPI_PS_INPUT_CNTL[ui].u32All, ui,
+			     SEMANTIC_shift, SEMANTIC_mask);
+		    CLEARbit(r700->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
+	    }
+    }
 
+    return GL_TRUE;
+}
 
diff --git a/src/mesa/drivers/dri/r600/r700_ioctl.c b/src/mesa/drivers/dri/r600/r700_ioctl.c
index c479532001..23cc128d6d 100644
--- a/src/mesa/drivers/dri/r600/r700_ioctl.c
+++ b/src/mesa/drivers/dri/r600/r700_ioctl.c
@@ -43,7 +43,6 @@
 static void r700Flush(GLcontext *ctx)
 {
 	radeonContextPtr radeon = RADEON_CONTEXT(ctx);
-    context_t *     context = R700_CONTEXT(ctx);
 
 	if (RADEON_DEBUG & DEBUG_IOCTL)
 		fprintf(stderr, "%s %d\n", __FUNCTION__, radeon->cmdbuf.cs->cdw);
@@ -59,7 +58,7 @@ static void r700Flush(GLcontext *ctx)
 	if (radeon->dma.flush)
 		radeon->dma.flush( ctx );
 
-	r700SendContextStates(context);
+	r700EmitState(ctx);
 
 	if (radeon->cmdbuf.cs->cdw)
 		rcommonFlushCmdBuf(radeon, __FUNCTION__);
diff --git a/src/mesa/drivers/dri/r600/r700_oglprog.c b/src/mesa/drivers/dri/r600/r700_oglprog.c
index 36de143b1a..c49b90c1cc 100644
--- a/src/mesa/drivers/dri/r600/r700_oglprog.c
+++ b/src/mesa/drivers/dri/r600/r700_oglprog.c
@@ -33,6 +33,7 @@
 #include "tnl/tnl.h"
 
 #include "r600_context.h"
+#include "r600_emit.h"
 
 #include "r700_oglprog.h"
 #include "r700_fragprog.h"
@@ -87,7 +88,6 @@ static void r700DeleteProgram(GLcontext * ctx, struct gl_program *prog)
 {
     struct r700_vertex_program   * vp;
     struct r700_fragment_program * fp;
-    context_t *context = R700_CONTEXT(ctx);
 
     switch (prog->Target) 
     {
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index f1e467a317..6985bd4ffa 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -44,7 +44,6 @@
 #include "tnl/t_vertex.h"
 #include "tnl/t_pipeline.h"
 
-#include "radeon_mipmap_tree.h"
 #include "r600_context.h"
 #include "r600_cmdbuf.h"
 
@@ -58,7 +57,7 @@ void r700WaitForIdle(context_t *context);
 void r700WaitForIdleClean(context_t *context);
 void r700Start3D(context_t *context);
 GLboolean r700SendTextureState(context_t *context);
-unsigned int r700PrimitiveType(int prim);
+static unsigned int r700PrimitiveType(int prim);
 void r600UpdateTextureState(GLcontext * ctx);
 GLboolean r700SyncSurf(context_t *context,
 		       struct radeon_bo *pbo,
@@ -138,59 +137,15 @@ static GLboolean r700SetupShaders(GLcontext * ctx)
     exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
     r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
 
-    return GL_TRUE;
-}
+    r600UpdateTextureState(ctx);
 
-GLboolean r700SendTextureState(context_t *context)
-{
-    unsigned int i;
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    offset_modifiers offset_mod = {NO_SHIFT, 0, 0xFFFFFFFF};
-    struct radeon_bo *bo = NULL;
-    BATCH_LOCALS(&context->radeon);
+    r700SendFSState(context); // FIXME just a place holder for now
+    r700SendPSState(context);
+    r700SendVSState(context);
+
+    r700SendTextureState(context);
+    r700SetupStreams(ctx);
 
-    for (i=0; i<R700_TEXTURE_NUMBERUNITS; i++) {
-	    radeonTexObj *t = r700->textures[i];
-	    if (t) {
-		    if (!t->image_override)
-			    bo = t->mt->bo;
-		    else
-			    bo = t->bo;
-		    if (bo) {
-
-			    r700SyncSurf(context, bo,
-					 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM,
-					 0, TC_ACTION_ENA_bit);
-
-			    BEGIN_BATCH_NO_AUTOSTATE(9);
-			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
-			    R600_OUT_BATCH(i * 7);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE0);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE1);
-			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE2,
-						 bo,
-						 0,
-						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod);
-			    R600_OUT_BATCH_RELOC(r700->textures[i]->SQ_TEX_RESOURCE3,
-						 bo,
-						 0,
-						 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0, &offset_mod);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE4);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE5);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_RESOURCE6);
-			    END_BATCH();
-
-			    BEGIN_BATCH_NO_AUTOSTATE(5);
-			    R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_SAMPLER, 3));
-			    R600_OUT_BATCH(i * 3);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER0);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER1);
-			    R600_OUT_BATCH(r700->textures[i]->SQ_TEX_SAMPLER2);
-			    END_BATCH();
-			    COMMIT_BATCH();
-		    }
-	    }
-    }
     return GL_TRUE;
 }
 
@@ -202,17 +157,15 @@ GLboolean r700SyncSurf(context_t *context,
 {
     BATCH_LOCALS(&context->radeon);
     uint32_t cp_coher_size;
-    offset_modifiers offset_mod;
+
+    if (!pbo)
+	    return GL_FALSE;
 
     if (pbo->size == 0xffffffff)
 	    cp_coher_size = 0xffffffff;
     else
 	    cp_coher_size = ((pbo->size + 255) >> 8);
 
-    offset_mod.shift     = NO_SHIFT;
-    offset_mod.shiftbits = 0;
-    offset_mod.mask      = 0xFFFFFFFF;
-
     BEGIN_BATCH_NO_AUTOSTATE(5);
     R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
     R600_OUT_BATCH(sync_type);
@@ -220,7 +173,7 @@ GLboolean r700SyncSurf(context_t *context,
     R600_OUT_BATCH_RELOC(0,
 			 pbo,
 			 0,
-			 read_domain, write_domain, 0, &offset_mod); // ???
+			 read_domain, write_domain, 0); // ???
     R600_OUT_BATCH(10);
 
     END_BATCH();
@@ -229,7 +182,7 @@ GLboolean r700SyncSurf(context_t *context,
     return GL_TRUE;
 }
 
-unsigned int r700PrimitiveType(int prim)
+static unsigned int r700PrimitiveType(int prim)
 {
     switch (prim & PRIM_MODE_MASK)
     {
@@ -270,119 +223,163 @@ unsigned int r700PrimitiveType(int prim)
     }
 }
 
-static GLboolean r700RunRender(GLcontext * ctx,
-			                   struct tnl_pipeline_stage *stage)
+static int r700NumVerts(int num_verts, int prim)
 {
-    context_t *context = R700_CONTEXT(ctx);
-    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-    int lastIndex = 0;
-#if 1
-    BATCH_LOCALS(&context->radeon);
-
-    unsigned int i, j;
-    TNLcontext *tnl = TNL_CONTEXT(ctx);
-    struct vertex_buffer *vb = &tnl->vb;
-
-    struct r700_fragment_program *fp = (struct r700_fragment_program *)
-	                                   (ctx->FragmentProgram._Current);
-    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
-    {
-        fp->r700AsmCode.bR6xx = 1;
-    }
-
-    r700Start3D(context); /* TODO : this is too much. */
+	int verts_off = 0;
+
+	switch (prim & PRIM_MODE_MASK) {
+	case GL_POINTS:
+		verts_off = 0;
+		break;
+	case GL_LINES:
+		verts_off = num_verts % 2;
+		break;
+	case GL_LINE_STRIP:
+		if (num_verts < 2)
+			verts_off = num_verts;
+		break;
+	case GL_LINE_LOOP:
+		if (num_verts < 2)
+			verts_off = num_verts;
+		break;
+	case GL_TRIANGLES:
+		verts_off = num_verts % 3;
+		break;
+	case GL_TRIANGLE_STRIP:
+		if (num_verts < 3)
+			verts_off = num_verts;
+		break;
+	case GL_TRIANGLE_FAN:
+		if (num_verts < 3)
+			verts_off = num_verts;
+		break;
+	case GL_QUADS:
+		verts_off = num_verts % 4;
+		break;
+	case GL_QUAD_STRIP:
+		if (num_verts < 4)
+			verts_off = num_verts;
+		else
+			verts_off = num_verts % 2;
+		break;
+	case GL_POLYGON:
+		if (num_verts < 3)
+			verts_off = num_verts;
+		break;
+	default:
+		assert(0);
+		return -1;
+		break;
+	}
+
+	return num_verts - verts_off;
+}
 
-    r700SendSQConfig(context);
+static void r700RunRenderPrimitive(GLcontext * ctx, int start, int end, int prim)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	BATCH_LOCALS(&context->radeon);
+	int type, i, total_emit;
+	int num_indices;
+	uint32_t vgt_draw_initiator = 0;
+	uint32_t vgt_index_type     = 0;
+	uint32_t vgt_primitive_type = 0;
+	uint32_t vgt_num_indices    = 0;
+
+	type = r700PrimitiveType(prim);
+	num_indices = r700NumVerts(end - start, prim);
+
+	if (type < 0 || num_indices <= 0)
+		return;
+
+        total_emit =   3 /* VGT_PRIMITIVE_TYPE */
+		     + 2 /* VGT_INDEX_TYPE */
+		     + 2 /* NUM_INSTANCES */
+                     + num_indices + 3; /* DRAW_INDEX_IMMD */
+
+        BEGIN_BATCH_NO_AUTOSTATE(total_emit);
+	// prim
+        SETfield(vgt_primitive_type, type,
+		 VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
+        R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
+        R600_OUT_BATCH(vgt_primitive_type);
 
-    r700UpdateShaders(ctx);
+	// index type
+        SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
+        R600_OUT_BATCH(vgt_index_type);
 
-    r700SetScissor(context);
-    r700SetRenderTarget(context, 0);
-    r700SetDepthTarget(context);
+	// num instances
+	R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
+        R600_OUT_BATCH(1);
 
-    if(r700SetupStreams(ctx))
-    {
-        return GL_TRUE;
-    }
+	// draw packet
+        vgt_num_indices = num_indices;
+        SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
+	SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
 
-    r600UpdateTextureState(ctx);
-    r700SendTextureState(context);
+        R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
+        R600_OUT_BATCH(vgt_num_indices);
+        R600_OUT_BATCH(vgt_draw_initiator);
 
-    if(GL_FALSE == fp->translated)
-    {
-        if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
-        {
-            return GL_TRUE;
+        for (i = start; i < (start + num_indices); i++) {
+            R600_OUT_BATCH(i);
         }
-    }
+        END_BATCH();
+        COMMIT_BATCH();
 
-    r700SetupShaders(ctx);
+}
 
-    r700SendFSState(context); // FIXME just a place holder for now
-    r700SendPSState(context);
-    r700SendVSState(context);
+void r700EmitState(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	radeonContextPtr radeon = &context->radeon;
 
-    r700SendContextStates(context);
-    r700SendViewportState(context, 0);
-    r700SendRenderTargetState(context, 0);
-    r700SendDepthTargetState(context);
+	if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty)
+		return;
 
-    /* richard test code */
-    for (i = 0; i < vb->PrimitiveCount; i++) 
-    {
-        GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
-        GLuint start = vb->Primitive[i].start;
-        GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
-        GLuint numIndices = vb->Primitive[i].count;
-        GLuint numEntires;
-
-        unsigned int VGT_DRAW_INITIATOR = 0;
-        unsigned int VGT_INDEX_TYPE     = 0;
-        unsigned int VGT_PRIMITIVE_TYPE = 0;
-        unsigned int VGT_NUM_INDICES    = 0;
-        
-        numEntires = 2 /* VGT_INDEX_TYPE */
-                     + 3 /* VGT_PRIMITIVE_TYPE */
-                     + numIndices + 3; /* DRAW_INDEX_IMMD */                  
-                     
-        BEGIN_BATCH_NO_AUTOSTATE(numEntires);  
-
-        VGT_INDEX_TYPE |= DI_INDEX_SIZE_32_BIT << INDEX_TYPE_shift;
+	rcommonEnsureCmdBufSpace(&context->radeon,
+				 context->radeon.hw.max_state_size, __FUNCTION__);
 
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
-        R600_OUT_BATCH(VGT_INDEX_TYPE);
+	r700SendSQConfig(context);
 
-        VGT_NUM_INDICES = numIndices;
+	r700SendUCPState(context);
+	r700SendContextStates(context);
+	r700SendViewportState(context, 0);
+	r700SendRenderTargetState(context, 0);
+	r700SendDepthTargetState(context);
 
-        VGT_PRIMITIVE_TYPE |= r700PrimitiveType(prim) << VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift;
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
-        R600_OUT_BATCH(mmVGT_PRIMITIVE_TYPE - ASIC_CONFIG_BASE_INDEX);
-        R600_OUT_BATCH(VGT_PRIMITIVE_TYPE);
+}
 
-        VGT_DRAW_INITIATOR |= DI_SRC_SEL_IMMEDIATE << SOURCE_SELECT_shift;
-        VGT_DRAW_INITIATOR |= DI_MAJOR_MODE_0 << MAJOR_MODE_shift;
+static GLboolean r700RunRender(GLcontext * ctx,
+			                   struct tnl_pipeline_stage *stage)
+{
+    context_t *context = R700_CONTEXT(ctx);
+    unsigned int i;
+    TNLcontext *tnl = TNL_CONTEXT(ctx);
+    struct vertex_buffer *vb = &tnl->vb;
 
-        R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (numIndices + 1)));
-        R600_OUT_BATCH(VGT_NUM_INDICES);
-        R600_OUT_BATCH(VGT_DRAW_INITIATOR);
+    r700Start3D(context);
 
-        for (j = lastIndex; j < lastIndex + numIndices; j++)
-        {
-            R600_OUT_BATCH(j);
-        }
-        lastIndex += numIndices;
+    r700UpdateShaders(ctx);
+    r700SetScissor(context);
+    r700SetupShaders(ctx);
 
-        END_BATCH();
-        COMMIT_BATCH();
+    r700EmitState(ctx);
+
+    /* richard test code */
+    for (i = 0; i < vb->PrimitiveCount; i++) {
+        GLuint prim = _tnl_translate_prim(&vb->Primitive[i]);
+        GLuint start = vb->Primitive[i].start;
+        GLuint end = vb->Primitive[i].start + vb->Primitive[i].count;
+	r700RunRenderPrimitive(ctx, start, end, prim);
     }
 
     /* Flush render op cached for last several quads. */
     r700WaitForIdleClean(context);
 
-    radeonReleaseArrays(ctx, 0);
-
-#endif //0
-    rcommonFlushCmdBuf( &context->radeon, __FUNCTION__ );
+    radeonReleaseArrays(ctx, ~0);
 
     return GL_FALSE;
 }
@@ -410,10 +407,6 @@ static GLboolean r700RunTCLRender(GLcontext * ctx,  /*----------------------*/
         return GL_TRUE;
     }
 
-    context_t *context = R700_CONTEXT(ctx);
-
-    r700UpdateShaders(ctx);
-
     bRet = r700RunRender(ctx, stage);
 
     return bRet;
diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index eda224def3..835b5e18c2 100644
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -30,6 +30,7 @@
 #include "main/imports.h"
 #include "main/enums.h"
 #include "main/macros.h"
+#include "main/context.h"
 #include "main/dd.h"
 #include "main/simple_list.h"
 
@@ -55,6 +56,13 @@
 #include "r700_vertprog.h"
 
 
+static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
+static void r700UpdatePolygonMode(GLcontext * ctx);
+static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
+static void r700SetStencilState(GLcontext * ctx, GLboolean state);
+static void r700SetRenderTarget(context_t *context, int id);
+static void r700SetDepthTarget(context_t *context);
+
 void r700SetDefaultStates(context_t *context) //--------------------
 {
     
@@ -66,12 +74,28 @@ void r700UpdateShaders (GLcontext * ctx)  //----------------------------------
 
     GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
     GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
-
-    struct r700_vertex_program *vp;
-	int i;
+    int i;
+
+    if (ctx->FragmentProgram._Current) {
+	    struct r700_fragment_program *fp = (struct r700_fragment_program *)
+		    (ctx->FragmentProgram._Current);
+	    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+	    {
+		    fp->r700AsmCode.bR6xx = 1;
+	    }
+
+	    if(GL_FALSE == fp->translated)
+	    {
+		    if( GL_FALSE == r700TranslateFragmentShader(fp, &(fp->mesa_program)) )
+		    {
+			    //return GL_TRUE;
+		    }
+	    }
+    }
 
     if (context->radeon.NewGLState) 
     {
+	struct r700_vertex_program *vp;
         context->radeon.NewGLState = 0;
 
         for (i = _TNL_FIRST_MAT; i <= _TNL_LAST_MAT; i++) 
@@ -113,10 +137,21 @@ void r700UpdateShaders (GLcontext * ctx)  //----------------------------------
  */
 void r700UpdateViewportOffset(GLcontext * ctx) //------------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
+	GLfloat xoffset = (GLfloat) dPriv->x;
+	GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h;
+	const GLfloat *v = ctx->Viewport._WindowMap.m;
+	int id = 0;
 
-	//radeonUpdateScissor(ctx);
+	GLfloat tx = v[MAT_TX] + xoffset;
+	GLfloat ty = (-v[MAT_TY]) + yoffset;
 
-    return;
+	r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx;
+	r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty;
+
+	radeonUpdateScissor(ctx);
 }
 
 /**
@@ -125,29 +160,16 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
  */
 void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
 {
-#if 0 /* to be enabled */
-    context_t *context = R700_CONTEXT(ctx);
+	context_t *context = R700_CONTEXT(ctx);
 
-    switch (ctx->DrawBuffer->_ColorDrawBufferIndexes[0]) 
-    {
-	case BUFFER_FRONT_LEFT:
-	    context->target.rt = context->screen->frontBuffer;
-	    break;
-	case BUFFER_BACK_LEFT:
-	    context->target.rt = context->screen->backBuffer;
-	    break;
-	default:
-	    memset (&context->target.rt, sizeof(context->target.rt), 0);
-	}
-#endif /* to be enabled */
+	r700SetRenderTarget(context, 0);
+	r700SetDepthTarget(context);
 }
 
 static void r700FetchStateParameter(GLcontext * ctx,
 			                        const gl_state_index state[STATE_LENGTH],
 			                        GLfloat * value)
 {
-	context_t *context = R700_CONTEXT(ctx);
-
     /* TODO */
 }
 
@@ -257,40 +279,40 @@ static void r700SetDepthState(GLcontext * ctx)
 
         switch (ctx->Depth.Func)
         {
-        case GL_NEVER:            
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER, 
+        case GL_NEVER:
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NEVER,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_LESS:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS, 
-                     ZFUNC_shift, ZFUNC_mask);            
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LESS,
+                     ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_EQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL, 
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_EQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_LEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_LEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_GREATER:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,  
-                     ZFUNC_shift, ZFUNC_mask);           
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GREATER,
+                     ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_NOTEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_NOTEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_GEQUAL:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_GEQUAL,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         case GL_ALWAYS:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         default:
-            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,  
+            SETfield(r700->DB_DEPTH_CONTROL.u32All, FRAG_ALWAYS,
                      ZFUNC_shift, ZFUNC_mask);
             break;
         }
@@ -302,24 +324,336 @@ static void r700SetDepthState(GLcontext * ctx)
     }
 }
 
+static void r700SetAlphaState(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	uint32_t alpha_func = REF_ALWAYS;
+	GLboolean really_enabled = ctx->Color.AlphaEnabled;
+
+	switch (ctx->Color.AlphaFunc) {
+	case GL_NEVER:
+		alpha_func = REF_NEVER;
+		break;
+	case GL_LESS:
+		alpha_func = REF_LESS;
+		break;
+	case GL_EQUAL:
+		alpha_func = REF_EQUAL;
+		break;
+	case GL_LEQUAL:
+		alpha_func = REF_LEQUAL;
+		break;
+	case GL_GREATER:
+		alpha_func = REF_GREATER;
+		break;
+	case GL_NOTEQUAL:
+		alpha_func = REF_NOTEQUAL;
+		break;
+	case GL_GEQUAL:
+		alpha_func = REF_GEQUAL;
+		break;
+	case GL_ALWAYS:
+		/*alpha_func = REF_ALWAYS; */
+		really_enabled = GL_FALSE;
+		break;
+	}
+
+	if (really_enabled) {
+		SETfield(r700->SX_ALPHA_TEST_CONTROL.u32All, alpha_func,
+			 ALPHA_FUNC_shift, ALPHA_FUNC_mask);
+		SETbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
+		r700->SX_ALPHA_REF.f32All = ctx->Color.AlphaRef;
+	} else {
+		CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
+	}
+
+}
+
 static void r700AlphaFunc(GLcontext * ctx, GLenum func, GLfloat ref) //---------------
 {
+	(void)func;
+	(void)ref;
+	r700SetAlphaState(ctx);
 }
 
 
 static void r700BlendColor(GLcontext * ctx, const GLfloat cf[4]) //----------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	r700->CB_BLEND_RED.f32All = cf[0];
+	r700->CB_BLEND_GREEN.f32All = cf[1];
+	r700->CB_BLEND_BLUE.f32All = cf[2];
+	r700->CB_BLEND_ALPHA.f32All = cf[3];
+}
+
+static int blend_factor(GLenum factor, GLboolean is_src)
+{
+	switch (factor) {
+	case GL_ZERO:
+		return BLEND_ZERO;
+		break;
+	case GL_ONE:
+		return BLEND_ONE;
+		break;
+	case GL_DST_COLOR:
+		return BLEND_DST_COLOR;
+		break;
+	case GL_ONE_MINUS_DST_COLOR:
+		return BLEND_ONE_MINUS_DST_COLOR;
+		break;
+	case GL_SRC_COLOR:
+		return BLEND_SRC_COLOR;
+		break;
+	case GL_ONE_MINUS_SRC_COLOR:
+		return BLEND_ONE_MINUS_SRC_COLOR;
+		break;
+	case GL_SRC_ALPHA:
+		return BLEND_SRC_ALPHA;
+		break;
+	case GL_ONE_MINUS_SRC_ALPHA:
+		return BLEND_ONE_MINUS_SRC_ALPHA;
+		break;
+	case GL_DST_ALPHA:
+		return BLEND_DST_ALPHA;
+		break;
+	case GL_ONE_MINUS_DST_ALPHA:
+		return BLEND_ONE_MINUS_DST_ALPHA;
+		break;
+	case GL_SRC_ALPHA_SATURATE:
+		return (is_src) ? BLEND_SRC_ALPHA_SATURATE : BLEND_ZERO;
+		break;
+	case GL_CONSTANT_COLOR:
+		return BLEND_CONSTANT_COLOR;
+		break;
+	case GL_ONE_MINUS_CONSTANT_COLOR:
+		return BLEND_ONE_MINUS_CONSTANT_COLOR;
+		break;
+	case GL_CONSTANT_ALPHA:
+		return BLEND_CONSTANT_ALPHA;
+		break;
+	case GL_ONE_MINUS_CONSTANT_ALPHA:
+		return BLEND_ONE_MINUS_CONSTANT_ALPHA;
+		break;
+	default:
+		fprintf(stderr, "unknown blend factor %x\n", factor);
+		return (is_src) ? BLEND_ONE : BLEND_ZERO;
+		break;
+	}
+}
+
+static void r700SetBlendState(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	int id = 0;
+	uint32_t blend_reg = 0, eqn, eqnA;
+
+	if (RGBA_LOGICOP_ENABLED(ctx) || !ctx->Color.BlendEnabled) {
+		SETfield(blend_reg,
+			 BLEND_ONE, COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ZERO, COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		SETfield(blend_reg,
+			 COMB_DST_PLUS_SRC, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE, ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ZERO, ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		SETfield(blend_reg,
+			 COMB_DST_PLUS_SRC, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
+		if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
+			r700->CB_BLEND_CONTROL.u32All = blend_reg;
+		else
+			r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
+		return;
+	}
+
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
+		 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
+		 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+
+	switch (ctx->Color.BlendEquationRGB) {
+	case GL_FUNC_ADD:
+		eqn = COMB_DST_PLUS_SRC;
+		break;
+	case GL_FUNC_SUBTRACT:
+		eqn = COMB_SRC_MINUS_DST;
+		break;
+	case GL_FUNC_REVERSE_SUBTRACT:
+		eqn = COMB_DST_MINUS_SRC;
+		break;
+	case GL_MIN:
+		eqn = COMB_MIN_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		break;
+	case GL_MAX:
+		eqn = COMB_MAX_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_SRCBLEND_shift, COLOR_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 COLOR_DESTBLEND_shift, COLOR_DESTBLEND_mask);
+		break;
+
+	default:
+		fprintf(stderr,
+			"[%s:%u] Invalid RGB blend equation (0x%04x).\n",
+			__FUNCTION__, __LINE__, ctx->Color.BlendEquationRGB);
+		return;
+	}
+	SETfield(blend_reg,
+		 eqn, COLOR_COMB_FCN_shift, COLOR_COMB_FCN_mask);
+
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendSrcRGB, GL_TRUE),
+		 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+	SETfield(blend_reg,
+		 blend_factor(ctx->Color.BlendDstRGB, GL_FALSE),
+		 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+
+	switch (ctx->Color.BlendEquationA) {
+	case GL_FUNC_ADD:
+		eqnA = COMB_DST_PLUS_SRC;
+		break;
+	case GL_FUNC_SUBTRACT:
+		eqnA = COMB_SRC_MINUS_DST;
+		break;
+	case GL_FUNC_REVERSE_SUBTRACT:
+		eqnA = COMB_DST_MINUS_SRC;
+		break;
+	case GL_MIN:
+		eqnA = COMB_MIN_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		break;
+	case GL_MAX:
+		eqnA = COMB_MAX_DST_SRC;
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_SRCBLEND_shift, ALPHA_SRCBLEND_mask);
+		SETfield(blend_reg,
+			 BLEND_ONE,
+			 ALPHA_DESTBLEND_shift, ALPHA_DESTBLEND_mask);
+		break;
+	default:
+		fprintf(stderr,
+			"[%s:%u] Invalid A blend equation (0x%04x).\n",
+			__FUNCTION__, __LINE__, ctx->Color.BlendEquationA);
+		return;
+	}
+
+	SETfield(blend_reg,
+		 eqnA, ALPHA_COMB_FCN_shift, ALPHA_COMB_FCN_mask);
+
+	SETbit(blend_reg, SEPARATE_ALPHA_BLEND_bit);
+
+	if (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_R600)
+		r700->CB_BLEND_CONTROL.u32All = blend_reg;
+	else {
+		r700->render_target[id].CB_BLEND0_CONTROL.u32All = blend_reg;
+		SETbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
+	}
+	SETfield(r700->CB_COLOR_CONTROL.u32All, (1 << id),
+		 TARGET_BLEND_ENABLE_shift, TARGET_BLEND_ENABLE_mask);
+
 }
 
 static void r700BlendEquationSeparate(GLcontext * ctx,
 				                      GLenum modeRGB, GLenum modeA) //-----------------
 {
+	r700SetBlendState(ctx);
 }
 
 static void r700BlendFuncSeparate(GLcontext * ctx,
 				  GLenum sfactorRGB, GLenum dfactorRGB,
 				  GLenum sfactorA, GLenum dfactorA) //------------------------
 {
+	r700SetBlendState(ctx);
+}
+
+/**
+ * Translate LogicOp enums into hardware representation.
+ */
+static GLuint translate_logicop(GLenum logicop)
+{
+	switch (logicop) {
+	case GL_CLEAR:
+		return 0x00;
+	case GL_SET:
+		return 0xff;
+	case GL_COPY:
+		return 0xcc;
+	case GL_COPY_INVERTED:
+		return 0x33;
+	case GL_NOOP:
+		return 0xaa;
+	case GL_INVERT:
+		return 0x55;
+	case GL_AND:
+		return 0x88;
+	case GL_NAND:
+		return 0x77;
+	case GL_OR:
+		return 0xee;
+	case GL_NOR:
+		return 0x11;
+	case GL_XOR:
+		return 0x66;
+	case GL_EQUIV:
+		return 0xaa;
+	case GL_AND_REVERSE:
+		return 0x44;
+	case GL_AND_INVERTED:
+		return 0x22;
+	case GL_OR_REVERSE:
+		return 0xdd;
+	case GL_OR_INVERTED:
+		return 0xbb;
+	default:
+		fprintf(stderr, "unknown blend logic operation %x\n", logicop);
+		return 0xcc;
+	}
+}
+
+/**
+ * Used internally to update the r300->hw hardware state to match the
+ * current OpenGL state.
+ */
+static void r700SetLogicOpState(GLcontext *ctx)
+{
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&R700_CONTEXT(ctx)->hw);
+
+	if (RGBA_LOGICOP_ENABLED(ctx))
+		SETfield(r700->CB_COLOR_CONTROL.u32All,
+			 translate_logicop(ctx->Color.LogicOp), ROP3_shift, ROP3_mask);
+	else
+		SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
+}
+
+/**
+ * Called by Mesa when an application program changes the LogicOp state
+ * via glLogicOp.
+ */
+static void r700LogicOpcode(GLcontext *ctx, GLenum logicop)
+{
+	if (RGBA_LOGICOP_ENABLED(ctx))
+		r700SetLogicOpState(ctx);
 }
 
 static void r700UpdateCulling(GLcontext * ctx)
@@ -330,11 +664,11 @@ static void r700UpdateCulling(GLcontext * ctx)
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
     CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
 
-    if (ctx->Polygon.CullFlag) 
+    if (ctx->Polygon.CullFlag)
     {
-        switch (ctx->Polygon.CullFaceMode) 
+        switch (ctx->Polygon.CullFaceMode)
         {
-        case GL_FRONT:            
+        case GL_FRONT:
             SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_FRONT_bit);
             CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, CULL_BACK_bit);
             break;
@@ -353,13 +687,13 @@ static void r700UpdateCulling(GLcontext * ctx)
         }
     }
 
-    switch (ctx->Polygon.FrontFace) 
+    switch (ctx->Polygon.FrontFace)
     {
         case GL_CW:
             SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
             break;
         case GL_CCW:
-            CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); 
+            CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit);
             break;
         default:
             CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, FACE_bit); /* default: ccw */
@@ -394,13 +728,13 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		/* empty */
 		break;
 	case GL_ALPHA_TEST:
-		//r700SetAlphaState(ctx);
+		r700SetAlphaState(ctx);
 		break;
 	case GL_COLOR_LOGIC_OP:
-		//r700SetLogicOpState(ctx);
+		r700SetLogicOpState(ctx);
 		/* fall-through, because logic op overrides blending */
 	case GL_BLEND:
-		//r700SetBlendState(ctx);
+		r700SetBlendState(ctx);
 		break;
 	case GL_CLIP_PLANE0:
 	case GL_CLIP_PLANE1:
@@ -408,13 +742,13 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 	case GL_CLIP_PLANE3:
 	case GL_CLIP_PLANE4:
 	case GL_CLIP_PLANE5:
-		//r700SetClipPlaneState(ctx, cap, state);
+		r700SetClipPlaneState(ctx, cap, state);
 		break;
 	case GL_DEPTH_TEST:
 		r700SetDepthState(ctx);
 		break;
 	case GL_STENCIL_TEST:
-		//r700SetStencilState(ctx, state);
+		r700SetStencilState(ctx, state);
 		break;
 	case GL_CULL_FACE:
 		r700UpdateCulling(ctx);
@@ -422,7 +756,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 	case GL_POLYGON_OFFSET_POINT:
 	case GL_POLYGON_OFFSET_LINE:
 	case GL_POLYGON_OFFSET_FILL:
-		//r700SetPolygonOffsetState(ctx, state);
+		r700SetPolygonOffsetState(ctx, state);
 		break;
 	case GL_SCISSOR_TEST:
 		radeon_firevertices(&context->radeon);
@@ -431,7 +765,7 @@ static void r700Enable(GLcontext * ctx, GLenum cap, GLboolean state) //---------
 		break;
 	case GL_LINE_STIPPLE:
 		r700UpdateLineStipple(ctx);
-		break;	
+		break;
 	default:
 		break;
 	}
@@ -499,6 +833,7 @@ static void r700Fogfv(GLcontext * ctx, GLenum pname, const GLfloat * param) //--
 static void r700FrontFace(GLcontext * ctx, GLenum mode) //------------------
 {
     r700UpdateCulling(ctx);
+    r700UpdatePolygonMode(ctx);
 }
 
 static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
@@ -519,28 +854,201 @@ static void r700ShadeModel(GLcontext * ctx, GLenum mode) //--------------------
 	}
 }
 
+/* =============================================================
+ * Point state
+ */
+static void r700PointSize(GLcontext * ctx, GLfloat size)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	/* We need to clamp to user defined range here, because
+	 * the HW clamping happens only for per vertex point size. */
+	size = CLAMP(size, ctx->Point.MinSize, ctx->Point.MaxSize);
+
+	/* same size limits for AA, non-AA points */
+	size = CLAMP(size, ctx->Const.MinPointSize, ctx->Const.MaxPointSize);
+
+	/* format is 12.4 fixed point */
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+		 PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
+	SETfield(r700->PA_SU_POINT_SIZE.u32All, (int)(size * 16),
+		 PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
+
+}
+
 static void r700PointParameter(GLcontext * ctx, GLenum pname, const GLfloat * param) //---------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	/* format is 12.4 fixed point */
+	switch (pname) {
+	case GL_POINT_SIZE_MIN:
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MinSize * 16.0),
+			 MIN_SIZE_shift, MIN_SIZE_mask);
+		break;
+	case GL_POINT_SIZE_MAX:
+		SETfield(r700->PA_SU_POINT_MINMAX.u32All, (int)(ctx->Point.MaxSize * 16.0),
+			 MAX_SIZE_shift, MAX_SIZE_mask);
+		break;
+	case GL_POINT_DISTANCE_ATTENUATION:
+		break;
+	case GL_POINT_FADE_THRESHOLD_SIZE:
+		break;
+	default:
+		break;
+	}
+}
+
+static int translate_stencil_func(int func)
+{
+	switch (func) {
+	case GL_NEVER:
+		return REF_NEVER;
+	case GL_LESS:
+		return REF_LESS;
+	case GL_EQUAL:
+		return REF_EQUAL;
+	case GL_LEQUAL:
+		return REF_LEQUAL;
+	case GL_GREATER:
+		return REF_GREATER;
+	case GL_NOTEQUAL:
+		return REF_NOTEQUAL;
+	case GL_GEQUAL:
+		return REF_GEQUAL;
+	case GL_ALWAYS:
+		return REF_ALWAYS;
+	}
+	return 0;
+}
+
+static int translate_stencil_op(int op)
+{
+	switch (op) {
+	case GL_KEEP:
+		return STENCIL_KEEP;
+	case GL_ZERO:
+		return STENCIL_ZERO;
+	case GL_REPLACE:
+		return STENCIL_REPLACE;
+	case GL_INCR:
+		return STENCIL_INCR_CLAMP;
+	case GL_DECR:
+		return STENCIL_DECR_CLAMP;
+	case GL_INCR_WRAP_EXT:
+		return STENCIL_INCR_WRAP;
+	case GL_DECR_WRAP_EXT:
+		return STENCIL_DECR_WRAP;
+	case GL_INVERT:
+		return STENCIL_INVERT;
+	default:
+		WARN_ONCE("Do not know how to translate stencil op");
+		return STENCIL_KEEP;
+	}
+	return 0;
+}
+
+static void r700SetStencilState(GLcontext * ctx, GLboolean state)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLboolean hw_stencil = GL_FALSE;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	if (ctx->DrawBuffer) {
+		struct radeon_renderbuffer *rrbStencil
+			= radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL);
+		hw_stencil = (rrbStencil && rrbStencil->bo);
+	}
+
+	if (hw_stencil) {
+		if (state)
+			SETbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
+		else
+			CLEARbit(r700->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit);
+	}
 }
 
 static void r700StencilFuncSeparate(GLcontext * ctx, GLenum face,
 				    GLenum func, GLint ref, GLuint mask) //---------------------
 {
-}
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
 
+	//front
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.Ref[0],
+		 STENCILREF_shift, STENCILREF_mask);
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.ValueMask[0],
+		 STENCILMASK_shift, STENCILMASK_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[0]),
+		 STENCILFUNC_shift, STENCILFUNC_mask);
+
+	//back
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.Ref[back],
+		 STENCILREF_BF_shift, STENCILREF_BF_mask);
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.ValueMask[back],
+		 STENCILMASK_BF_shift, STENCILMASK_BF_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_func(ctx->Stencil.Function[back]),
+		 STENCILFUNC_BF_shift, STENCILFUNC_BF_mask);
+
+}
 
 static void r700StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask) //--------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	// front
+	SETfield(r700->DB_STENCILREFMASK.u32All, ctx->Stencil.WriteMask[0],
+		 STENCILWRITEMASK_shift, STENCILWRITEMASK_mask);
+
+	// back
+	SETfield(r700->DB_STENCILREFMASK_BF.u32All, ctx->Stencil.WriteMask[back],
+		 STENCILWRITEMASK_BF_shift, STENCILWRITEMASK_BF_mask);
+
 }
 
 static void r700StencilOpSeparate(GLcontext * ctx, GLenum face,
 				  GLenum fail, GLenum zfail, GLenum zpass) //--------------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	const unsigned back = ctx->Stencil._BackFace;
+
+	//fixme
+	//r300CatchStencilFallback(ctx);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[0]),
+		 STENCILFAIL_shift, STENCILFAIL_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[0]),
+		 STENCILZFAIL_shift, STENCILZFAIL_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[0]),
+		 STENCILZPASS_shift, STENCILZPASS_mask);
+
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.FailFunc[back]),
+		 STENCILFAIL_BF_shift, STENCILFAIL_BF_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZFailFunc[back]),
+		 STENCILZFAIL_BF_shift, STENCILZFAIL_BF_mask);
+	SETfield(r700->DB_DEPTH_CONTROL.u32All, translate_stencil_op(ctx->Stencil.ZPassFunc[back]),
+		 STENCILZPASS_BF_shift, STENCILZPASS_BF_mask);
 }
 
 static void r700UpdateWindow(GLcontext * ctx, int id) //--------------------
 {
-
 	context_t *context = R700_CONTEXT(ctx);
 	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 	__DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon);
@@ -599,10 +1107,6 @@ static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) /
 	r700UpdateWindow(ctx, 0);
 }
 
-static void r700PointSize(GLcontext * ctx, GLfloat size) //-------------------
-{
-}
-
 static void r700LineWidth(GLcontext * ctx, GLfloat widthf) //---------------
 {
     context_t *context = R700_CONTEXT(ctx);
@@ -624,21 +1128,146 @@ static void r700LineStipple(GLcontext *ctx, GLint factor, GLushort pattern)
     SETfield(r700->PA_SC_LINE_STIPPLE.u32All, 1, AUTO_RESET_CNTL_shift, AUTO_RESET_CNTL_mask);
 }
 
+static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	if (state) {
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
+		SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
+	} else {
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_FRONT_ENABLE_bit);
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_BACK_ENABLE_bit);
+		CLEARbit(r700->PA_SU_SC_MODE_CNTL.u32All, POLY_OFFSET_PARA_ENABLE_bit);
+	}
+}
+
 static void r700PolygonOffset(GLcontext * ctx, GLfloat factor, GLfloat units) //--------------
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLfloat constant = units;
+
+	switch (ctx->Visual.depthBits) {
+	case 16:
+		constant *= 4.0;
+		break;
+	case 24:
+		constant *= 2.0;
+		break;
+	}
+
+	factor *= 12.0;
+
+	r700->PA_SU_POLY_OFFSET_FRONT_SCALE.f32All = factor;
+	r700->PA_SU_POLY_OFFSET_FRONT_OFFSET.f32All = constant;
+	r700->PA_SU_POLY_OFFSET_BACK_SCALE.f32All = factor;
+	r700->PA_SU_POLY_OFFSET_BACK_OFFSET.f32All = constant;
 }
 
+static void r700UpdatePolygonMode(GLcontext * ctx)
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+
+	SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DISABLE_POLY_MODE, POLY_MODE_shift, POLY_MODE_mask);
+
+	/* Only do something if a polygon mode is wanted, default is GL_FILL */
+	if (ctx->Polygon.FrontMode != GL_FILL ||
+	    ctx->Polygon.BackMode != GL_FILL) {
+		GLenum f, b;
+
+		/* Handle GL_CW (clock wise and GL_CCW (counter clock wise)
+		 * correctly by selecting the correct front and back face
+		 */
+		if (ctx->Polygon.FrontFace == GL_CCW) {
+			f = ctx->Polygon.FrontMode;
+			b = ctx->Polygon.BackMode;
+		} else {
+			f = ctx->Polygon.BackMode;
+			b = ctx->Polygon.FrontMode;
+		}
+
+		/* Enable polygon mode */
+		SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DUAL_MODE, POLY_MODE_shift, POLY_MODE_mask);
+
+		switch (f) {
+		case GL_LINE:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		case GL_POINT:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		case GL_FILL:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
+				 POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
+			break;
+		}
+
+		switch (b) {
+		case GL_LINE:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_LINES,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		case GL_POINT:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_POINTS,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		case GL_FILL:
+			SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
+				 POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
+			break;
+		}
+	}
+}
 
 static void r700PolygonMode(GLcontext * ctx, GLenum face, GLenum mode) //------------------
 {
+	(void)face;
+	(void)mode;
+
+	r700UpdatePolygonMode(ctx);
 }
- 
+
 static void r700RenderMode(GLcontext * ctx, GLenum mode) //---------------------
 {
 }
 
-static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq ) //-----------------
+static void r700ClipPlane( GLcontext *ctx, GLenum plane, const GLfloat *eq )
+{
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLint p;
+	GLint *ip;
+
+	p = (GLint) plane - (GLint) GL_CLIP_PLANE0;
+	ip = (GLint *)ctx->Transform._ClipUserPlane[p];
+
+	r700->ucp[p].PA_CL_UCP_0_X.u32All = ip[0];
+	r700->ucp[p].PA_CL_UCP_0_Y.u32All = ip[1];
+	r700->ucp[p].PA_CL_UCP_0_Z.u32All = ip[2];
+	r700->ucp[p].PA_CL_UCP_0_W.u32All = ip[3];
+}
+
+static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state)
 {
+	context_t *context = R700_CONTEXT(ctx);
+	R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+	GLuint p;
+
+	p = cap - GL_CLIP_PLANE0;
+	if (state) {
+		r700->PA_CL_CLIP_CNTL.u32All |= (UCP_ENA_0_bit << p);
+		r700->ucp[p].enabled = GL_TRUE;
+		r700ClipPlane(ctx, cap, NULL);
+	} else {
+		r700->PA_CL_CLIP_CNTL.u32All &= ~(UCP_ENA_0_bit << p);
+		r700->ucp[p].enabled = GL_FALSE;
+	}
 }
 
 void r700SetScissor(context_t *context) //---------------
@@ -719,22 +1348,22 @@ void r700SetScissor(context_t *context) //---------------
 	r700->viewport[id].enabled = GL_TRUE;
 }
 
-void r700SetRenderTarget(context_t *context, int id)
+static void r700SetRenderTarget(context_t *context, int id)
 {
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
     struct radeon_renderbuffer *rrb;
     unsigned int nPitchInPixel;
 
+    rrb = radeon_get_colorbuffer(&context->radeon);
+    if (!rrb || !rrb->bo) {
+	    fprintf(stderr, "no rrb\n");
+	    return;
+    }
+
     /* screen/window/view */
     SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
 
-    rrb = radeon_get_colorbuffer(&context->radeon);
-	if (!rrb || !rrb->bo) {
-		fprintf(stderr, "no rrb\n");
-		return;
-	}
-
     /* color buffer */
     r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
 
@@ -764,45 +1393,25 @@ void r700SetRenderTarget(context_t *context, int id)
     SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
     SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
 
-    CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */
-    CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */
-
     r700->render_target[id].enabled = GL_TRUE;
 }
 
-void r700SetDepthTarget(context_t *context)
+static void r700SetDepthTarget(context_t *context)
 {
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
     struct radeon_renderbuffer *rrb;
     unsigned int nPitchInPixel;
 
+    rrb = radeon_get_depthbuffer(&context->radeon);
+    if (!rrb)
+	    return;
+
     /* depth buf */
     r700->DB_DEPTH_SIZE.u32All = 0;
     r700->DB_DEPTH_BASE.u32All = 0;
     r700->DB_DEPTH_INFO.u32All = 0;
-
-    r700->DB_DEPTH_CLEAR.u32All     = 0x3F800000;
-    r700->DB_DEPTH_VIEW.u32All      = 0;
-    r700->DB_RENDER_CONTROL.u32All  = 0;
-    SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
-    SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
-    r700->DB_RENDER_OVERRIDE.u32All = 0;
-    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
-	    SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
-    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
-
-    r700->DB_ALPHA_TO_MASK.u32All = 0;
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
-    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
-
-    rrb = radeon_get_depthbuffer(&context->radeon);
-	if (!rrb)
-		return;
+    r700->DB_DEPTH_VIEW.u32All = 0;
 
     nPitchInPixel = rrb->pitch/rrb->cpp;
 
@@ -1033,9 +1642,10 @@ static void r700InitSQConfig(GLcontext * ctx)
 void r700InitState(GLcontext * ctx) //-------------------
 {
     context_t *context = R700_CONTEXT(ctx);
-
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+    radeon_firevertices(&context->radeon);
+
     r700->TA_CNTL_AUX.u32All = 0;
     SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
     r700->VC_ENHANCE.u32All = 0;
@@ -1064,37 +1674,14 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->VGT_MIN_VTX_INDX.u32All      = 0;
     r700->VGT_INDX_OFFSET.u32All    = 0;
 
-    /* Specify the number of instances */
-    r700->VGT_DMA_NUM_INSTANCES.u32All = 1;
-
-    /* not alpha blend */
-    CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
-    CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
-
     /* default shader connections. */
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
     r700->SPI_VS_OUT_ID_1.u32All  = 0x07060504;
 
-    r700->SPI_PS_INPUT_CNTL_0.u32All  = 0x00000800;
-    r700->SPI_PS_INPUT_CNTL_1.u32All  = 0x00000801;
-    r700->SPI_PS_INPUT_CNTL_2.u32All  = 0x00000802;
-
     r700->SPI_THREAD_GROUPING.u32All = 0;
     if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
 	    SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
 
-    SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
-    CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
-
-    r700->DB_SHADER_CONTROL.u32All = 0;
-    SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
-
-    /* Set up the culling control register */
-    SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
-             POLYMODE_FRONT_PTYPE_shift, POLYMODE_FRONT_PTYPE_mask);
-    SETfield(r700->PA_SU_SC_MODE_CNTL.u32All, X_DRAW_TRIANGLES,
-             POLYMODE_BACK_PTYPE_shift, POLYMODE_BACK_PTYPE_mask);
-
     /* screen */
     r700->PA_SC_SCREEN_SCISSOR_TL.u32All = 0x0;
 
@@ -1138,21 +1725,8 @@ void r700InitState(GLcontext * ctx) //-------------------
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_SCALE_ENA_bit);
     SETbit(r700->PA_CL_VTE_CNTL.u32All, VPORT_Z_OFFSET_ENA_bit);
 
-    /* Set up point sizes and min/max values */
-    SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
-             PA_SU_POINT_SIZE__HEIGHT_shift, PA_SU_POINT_SIZE__HEIGHT_mask);
-    SETfield(r700->PA_SU_POINT_SIZE.u32All, 0x8,
-             PA_SU_POINT_SIZE__WIDTH_shift, PA_SU_POINT_SIZE__WIDTH_mask);
-    CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
-    SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
-
-    /* Set up line control */
-    SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
-             PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
-
-    r700->PA_SC_LINE_CNTL.u32All = 0;
-    CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
-    SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
+    /* GL uses last vtx for flat shading components */
+    SETbit(r700->PA_SU_SC_MODE_CNTL.u32All, PROVOKING_VTX_LAST_bit);
 
     /* Set up vertex control */
     r700->PA_SU_VTX_CNTL.u32All = 0;
@@ -1167,7 +1741,84 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All  = 0x3F800000;
     r700->PA_CL_GB_HORZ_DISC_ADJ.u32All  = 0x3F800000;
 
+    /* Enable all samples for multi-sample anti-aliasing */
+    r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
+    /* Turn off AA */
+    r700->PA_SC_AA_CONFIG.u32All = 0;
+
+    r700->SX_MISC.u32All = 0;
+
+    r700InitSQConfig(ctx);
+
+    r700ColorMask(ctx,
+		  ctx->Color.ColorMask[RCOMP],
+		  ctx->Color.ColorMask[GCOMP],
+		  ctx->Color.ColorMask[BCOMP],
+		  ctx->Color.ColorMask[ACOMP]);
+
+    r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
+    r700DepthMask(ctx, ctx->Depth.Mask);
+    r700DepthFunc(ctx, ctx->Depth.Func);
+    SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
+
+    r700->DB_DEPTH_CLEAR.u32All     = 0x3F800000;
+
+    r700->DB_RENDER_CONTROL.u32All  = 0;
+    SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
+    SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
+    r700->DB_RENDER_OVERRIDE.u32All = 0;
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+	    SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
+    SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
+
+    r700->DB_ALPHA_TO_MASK.u32All = 0;
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
+
+    /* stencil */
+    r700Enable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled);
+    r700StencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]);
+    r700StencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0],
+			    ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]);
+    r700StencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0],
+			  ctx->Stencil.ZFailFunc[0],
+			  ctx->Stencil.ZPassFunc[0]);
+
+    r700UpdateCulling(ctx);
+
+    r700SetBlendState(ctx);
+    r700SetLogicOpState(ctx);
+
+    r700AlphaFunc(ctx, ctx->Color.AlphaFunc, ctx->Color.AlphaRef);
+    r700Enable(ctx, GL_ALPHA_TEST, ctx->Color.AlphaEnabled);
+
+    r700PointSize(ctx, 1.0);
+
+    CLEARfield(r700->PA_SU_POINT_MINMAX.u32All, MIN_SIZE_mask);
+    SETfield(r700->PA_SU_POINT_MINMAX.u32All, 0x8000, MAX_SIZE_shift, MAX_SIZE_mask);
+
+    r700LineWidth(ctx, 1.0);
+
+    r700->PA_SC_LINE_CNTL.u32All = 0;
+    CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
+    SETbit(r700->PA_SC_LINE_CNTL.u32All, LAST_PIXEL_bit);
+
+    r700ShadeModel(ctx, ctx->Light.ShadeModel);
+    r700PolygonMode(ctx, GL_FRONT, ctx->Polygon.FrontMode);
+    r700PolygonMode(ctx, GL_BACK, ctx->Polygon.BackMode);
+    r700PolygonOffset(ctx, ctx->Polygon.OffsetFactor,
+		      ctx->Polygon.OffsetUnits);
+    r700Enable(ctx, GL_POLYGON_OFFSET_POINT, ctx->Polygon.OffsetPoint);
+    r700Enable(ctx, GL_POLYGON_OFFSET_LINE, ctx->Polygon.OffsetLine);
+    r700Enable(ctx, GL_POLYGON_OFFSET_FILL, ctx->Polygon.OffsetFill);
+
     /* CB */
+    r700BlendColor(ctx, ctx->Color.BlendColor);
+
     r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
     r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
     r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
@@ -1176,13 +1827,6 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
     r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
 
-    r700->CB_BLEND_RED.u32All = 0;
-    r700->CB_BLEND_GREEN.u32All = 0;
-    r700->CB_BLEND_BLUE.u32All = 0;
-    r700->CB_BLEND_ALPHA.u32All = 0;
-
-    r700->CB_BLEND_CONTROL.u32All = 0;
-
     /* Disable color compares */
     SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
              CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
@@ -1200,17 +1844,8 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Set up color compare mask */
     r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
 
-    /* default color mask */
-    SETfield(r700->CB_SHADER_MASK.u32All, 0xF, OUTPUT0_ENABLE_shift, OUTPUT0_ENABLE_mask);
-
-    /* Enable all samples for multi-sample anti-aliasing */
-    r700->PA_SC_AA_MASK.u32All = 0xFFFFFFFF;
-    /* Turn off AA */
-    r700->PA_SC_AA_CONFIG.u32All = 0;
-
-    r700->SX_MISC.u32All = 0;
+    context->radeon.hw.all_dirty = GL_TRUE;
 
-    r700InitSQConfig(ctx);
 }
 
 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
@@ -1228,6 +1863,7 @@ void r700InitStateFuncs(struct dd_function_table *functions) //-----------------
 	functions->Fogfv = r700Fogfv;
 	functions->FrontFace = r700FrontFace;
 	functions->ShadeModel = r700ShadeModel;
+	functions->LogicOpcode = r700LogicOpcode;
 
 	/* ARB_point_parameters */
 	functions->PointParameterfv = r700PointParameter;
diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h
index 23246367db..30eb54e8b0 100644
--- a/src/mesa/drivers/dri/r600/r700_state.h
+++ b/src/mesa/drivers/dri/r600/r700_state.h
@@ -42,10 +42,8 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx);
 extern void r700InitState (GLcontext * ctx);
 extern void r700InitStateFuncs (struct dd_function_table *functions);
 
-extern void r700SetRenderTarget(context_t *context, int id);
 extern void r700SetDefaultStates(context_t * context);
 
-void r700SetScissor(context_t *context);
-void r700SetDepthTarget(context_t *context);
+extern void r700SetScissor(context_t *context);
 
 #endif	/* _R600_SCREEN_H */
diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c
index cbfeaf071b..31e71cdfa3 100644
--- a/src/mesa/drivers/dri/r600/r700_vertprog.c
+++ b/src/mesa/drivers/dri/r600/r700_vertprog.c
@@ -52,7 +52,7 @@ unsigned int Map_Vertex_Output(r700_AssemblerBase       *pAsm,
 	unsigned int unBit;
 	unsigned int unTotal = unStart;
 
-    //!!!!!!! THE ORDER MATCH FS INPUT 
+    //!!!!!!! THE ORDER MATCH FS INPUT
 
 	unBit = 1 << VERT_RESULT_HPOS;
 	if(mesa_vp->Base.OutputsWritten & unBit)
@@ -73,31 +73,31 @@ unsigned int Map_Vertex_Output(r700_AssemblerBase       *pAsm,
 	}
 
 	//TODO : dealing back face.
-	//unBit = 1 << VERT_RESULT_BFC0;
-	//if(mesa_vp->Base.OutputsWritten & unBit)
-	//{
-	//	pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++;
-	//}
-
-	//unBit = 1 << VERT_RESULT_BFC1;
-	//if(mesa_vp->Base.OutputsWritten & unBit)
-	//{
-	//	pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++;
-	//}
+	unBit = 1 << VERT_RESULT_BFC0;
+	if(mesa_vp->Base.OutputsWritten & unBit)
+	{
+		pAsm->ucVP_OutputMap[VERT_RESULT_BFC0] = unTotal++;
+	}
+
+	unBit = 1 << VERT_RESULT_BFC1;
+	if(mesa_vp->Base.OutputsWritten & unBit)
+	{
+		pAsm->ucVP_OutputMap[VERT_RESULT_BFC1] = unTotal++;
+	}
 
 	//TODO : dealing fog.
-	//unBit = 1 << VERT_RESULT_FOGC;
-	//if(mesa_vp->Base.OutputsWritten & unBit)
-	//{
-	//	pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
-	//}
+	unBit = 1 << VERT_RESULT_FOGC;
+	if(mesa_vp->Base.OutputsWritten & unBit)
+	{
+		pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
+	}
 
 	//TODO : dealing point size.
-	//unBit = 1 << VERT_RESULT_PSIZ;
-	//if(mesa_vp->Base.OutputsWritten & unBit)
-	//{
-	//	pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
-	//}
+	unBit = 1 << VERT_RESULT_PSIZ;
+	if(mesa_vp->Base.OutputsWritten & unBit)
+	{
+		pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
+	}
 
 	for(i=0; i<8; i++)
 	{
@@ -335,17 +335,13 @@ void * r700GetActiveVpShaderBo(GLcontext * ctx)
 GLboolean r700SetupVertexProgram(GLcontext * ctx)
 {
     context_t *context = R700_CONTEXT(ctx);
-
-    BATCH_LOCALS(&context->radeon);
-
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
-
+    BATCH_LOCALS(&context->radeon);
     struct r700_vertex_program *vp
              = (struct r700_vertex_program *)ctx->VertexProgram._Current;
 
     struct gl_program_parameter_list *paramList;
     unsigned int unNumParamData;
-
     unsigned int ui;
 
     if(GL_FALSE == vp->loaded)
@@ -359,7 +355,7 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
         r600EmitShader(ctx, 
                        &(vp->shaderbo), 
                        (GLvoid *)(vp->r700Shader.pProgram),
-                       vp->r700Shader.uShaderBinaryDWORDSize,

+                       vp->r700Shader.uShaderBinaryDWORDSize,
                        "VS"); 
 
         vp->loaded = GL_TRUE;
@@ -394,7 +390,6 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
     */
 
     /* sent out shader constants. */
-
     paramList = vp->mesa_program.Base.Parameters;
 
     if(NULL != paramList)
@@ -403,8 +398,8 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx)
 
         unNumParamData = paramList->NumParameters * 4;
 
-        BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2); 
-        
+        BEGIN_BATCH_NO_AUTOSTATE(unNumParamData + 2);
+
         R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_ALU_CONST, unNumParamData));
         /* assembler map const from very beginning. */
         R600_OUT_BATCH(SQ_ALU_CONSTANT_VS_OFFSET * 4);
diff --git a/src/mesa/drivers/dri/r600/radeon_bo_legacy.c b/src/mesa/drivers/dri/r600/radeon_bo_legacy.c
new file mode 120000
index 0000000000..79ad050e6b
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_bo_legacy.c
@@ -0,0 +1 @@
+../radeon/radeon_bo_legacy.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_bo_legacy.h b/src/mesa/drivers/dri/r600/radeon_bo_legacy.h
new file mode 120000
index 0000000000..83b0f7ffab
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_bo_legacy.h
@@ -0,0 +1 @@
+../radeon/radeon_bo_legacy.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_bocs_wrapper.h b/src/mesa/drivers/dri/r600/radeon_bocs_wrapper.h
new file mode 120000
index 0000000000..ca894b2443
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_bocs_wrapper.h
@@ -0,0 +1 @@
+../radeon/radeon_bocs_wrapper.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_chipset.h b/src/mesa/drivers/dri/r600/radeon_chipset.h
new file mode 120000
index 0000000000..eba99001ff
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_chipset.h
@@ -0,0 +1 @@
+../radeon/radeon_chipset.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_cmdbuf.h b/src/mesa/drivers/dri/r600/radeon_cmdbuf.h
new file mode 120000
index 0000000000..a799e1dc6d
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_cmdbuf.h
@@ -0,0 +1 @@
+../radeon/radeon_cmdbuf.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_common.c b/src/mesa/drivers/dri/r600/radeon_common.c
new file mode 120000
index 0000000000..67b19ba940
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_common.c
@@ -0,0 +1 @@
+../radeon/radeon_common.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_common.h b/src/mesa/drivers/dri/r600/radeon_common.h
new file mode 120000
index 0000000000..5bcb696a9f
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_common.h
@@ -0,0 +1 @@
+../radeon/radeon_common.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_common_context.c b/src/mesa/drivers/dri/r600/radeon_common_context.c
new file mode 120000
index 0000000000..86800f3819
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_common_context.c
@@ -0,0 +1 @@
+../radeon/radeon_common_context.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_common_context.h b/src/mesa/drivers/dri/r600/radeon_common_context.h
new file mode 120000
index 0000000000..4d66312550
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_common_context.h
@@ -0,0 +1 @@
+../radeon/radeon_common_context.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_context.h b/src/mesa/drivers/dri/r600/radeon_context.h
deleted file mode 100644
index 250570f6b8..0000000000
--- a/src/mesa/drivers/dri/r600/radeon_context.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**************************************************************************
-
-Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
-                     VA Linux Systems Inc., Fremont, California.
-Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
-
-The Weather Channel (TM) funded Tungsten Graphics to develop the
-initial release of the Radeon 8500 driver under the XFree86 license.
-This notice must be preserved.
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-**************************************************************************/
-
-/*
- * Authors:
- *   Gareth Hughes <gareth@valinux.com>
- *   Keith Whitwell <keith@tungstengraphics.com>
- *   Kevin E. Martin <martin@valinux.com>
- *   Nicolai Haehnle <prefect_@gmx.net>
- */
-
-#ifndef __RADEON_CONTEXT_H__
-#define __RADEON_CONTEXT_H__
-
-#include "main/mtypes.h"
-#include "main/colormac.h"
-#include "radeon_screen.h"
-#include "drm.h"
-#include "dri_util.h"
-
-#include "radeon_screen.h"
-
-#if R200_MERGED
-extern void radeonFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
-
-#define FALLBACK( radeon, bit, mode ) do {			\
-   if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n",	\
-		     __FUNCTION__, bit, mode );			\
-   radeonFallback( (radeon)->glCtx, bit, mode );		\
-} while (0)
-#else
-#define FALLBACK( radeon, bit, mode ) fprintf(stderr, "%s:%s\n", __LINE__, __FILE__);
-#endif
-
-/* TCL fallbacks */
-extern void radeonTclFallback(GLcontext * ctx, GLuint bit, GLboolean mode);
-
-#if R200_MERGED
-#define TCL_FALLBACK( ctx, bit, mode )	radeonTclFallback( ctx, bit, mode )
-#else
-#define TCL_FALLBACK( ctx, bit, mode )	;
-#endif
-
-
-#endif				/* __RADEON_CONTEXT_H__ */
diff --git a/src/mesa/drivers/dri/r600/radeon_cs_legacy.c b/src/mesa/drivers/dri/r600/radeon_cs_legacy.c
new file mode 120000
index 0000000000..006720f8a4
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_cs_legacy.c
@@ -0,0 +1 @@
+../radeon/radeon_cs_legacy.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_cs_legacy.h b/src/mesa/drivers/dri/r600/radeon_cs_legacy.h
new file mode 120000
index 0000000000..a5f95e0a3d
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_cs_legacy.h
@@ -0,0 +1 @@
+../radeon/radeon_cs_legacy.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_cs_space_drm.c b/src/mesa/drivers/dri/r600/radeon_cs_space_drm.c
new file mode 120000
index 0000000000..c248ea7d1a
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_cs_space_drm.c
@@ -0,0 +1 @@
+../radeon/radeon_cs_space_drm.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_dma.c b/src/mesa/drivers/dri/r600/radeon_dma.c
new file mode 120000
index 0000000000..43be000625
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_dma.c
@@ -0,0 +1 @@
+../radeon/radeon_dma.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_dma.h b/src/mesa/drivers/dri/r600/radeon_dma.h
new file mode 120000
index 0000000000..82e50634e3
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_dma.h
@@ -0,0 +1 @@
+../radeon/radeon_dma.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_fbo.c b/src/mesa/drivers/dri/r600/radeon_fbo.c
new file mode 120000
index 0000000000..0d738d8d78
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_fbo.c
@@ -0,0 +1 @@
+../radeon/radeon_fbo.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_lock.c b/src/mesa/drivers/dri/r600/radeon_lock.c
new file mode 120000
index 0000000000..af4108a8e3
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_lock.c
@@ -0,0 +1 @@
+../radeon/radeon_lock.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_lock.h b/src/mesa/drivers/dri/r600/radeon_lock.h
new file mode 120000
index 0000000000..64bdf94ee7
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_lock.h
@@ -0,0 +1 @@
+../radeon/radeon_lock.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_mipmap_tree.c b/src/mesa/drivers/dri/r600/radeon_mipmap_tree.c
new file mode 120000
index 0000000000..31c0cfbe94
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_mipmap_tree.c
@@ -0,0 +1 @@
+../radeon/radeon_mipmap_tree.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_mipmap_tree.h b/src/mesa/drivers/dri/r600/radeon_mipmap_tree.h
new file mode 120000
index 0000000000..254d50cf8c
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_mipmap_tree.h
@@ -0,0 +1 @@
+../radeon/radeon_mipmap_tree.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_screen.c b/src/mesa/drivers/dri/r600/radeon_screen.c
new file mode 120000
index 0000000000..86161118dd
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_screen.c
@@ -0,0 +1 @@
+../radeon/radeon_screen.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_screen.h b/src/mesa/drivers/dri/r600/radeon_screen.h
new file mode 120000
index 0000000000..23bb6bd459
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_screen.h
@@ -0,0 +1 @@
+../radeon/radeon_screen.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_span.c b/src/mesa/drivers/dri/r600/radeon_span.c
new file mode 120000
index 0000000000..232868c4c9
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_span.c
@@ -0,0 +1 @@
+../radeon/radeon_span.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_span.h b/src/mesa/drivers/dri/r600/radeon_span.h
new file mode 120000
index 0000000000..f9d634508c
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_span.h
@@ -0,0 +1 @@
+../radeon/radeon_span.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_texture.c b/src/mesa/drivers/dri/r600/radeon_texture.c
new file mode 120000
index 0000000000..a822710915
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_texture.c
@@ -0,0 +1 @@
+../radeon/radeon_texture.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/radeon_texture.h b/src/mesa/drivers/dri/r600/radeon_texture.h
new file mode 120000
index 0000000000..17fac3d5ea
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/radeon_texture.h
@@ -0,0 +1 @@
+../radeon/radeon_texture.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon.h b/src/mesa/drivers/dri/r600/server/radeon.h
new file mode 120000
index 0000000000..81274a54f1
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon.h
@@ -0,0 +1 @@
+../../radeon/server/radeon.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_dri.c b/src/mesa/drivers/dri/r600/server/radeon_dri.c
new file mode 120000
index 0000000000..d05847d650
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon_dri.c
@@ -0,0 +1 @@
+../../radeon/server/radeon_dri.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_dri.h b/src/mesa/drivers/dri/r600/server/radeon_dri.h
new file mode 120000
index 0000000000..27c591d3c9
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon_dri.h
@@ -0,0 +1 @@
+../../radeon/server/radeon_dri.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_egl.c b/src/mesa/drivers/dri/r600/server/radeon_egl.c
new file mode 120000
index 0000000000..d7735a7643
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon_egl.c
@@ -0,0 +1 @@
+../../radeon/server/radeon_egl.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_macros.h b/src/mesa/drivers/dri/r600/server/radeon_macros.h
new file mode 120000
index 0000000000..c56cd735b8
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon_macros.h
@@ -0,0 +1 @@
+../../radeon/server/radeon_macros.h
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/r600/server/radeon_reg.h b/src/mesa/drivers/dri/r600/server/radeon_reg.h
new file mode 120000
index 0000000000..e2349dcb68
--- /dev/null
+++ b/src/mesa/drivers/dri/r600/server/radeon_reg.h
@@ -0,0 +1 @@
+../../radeon/server/radeon_reg.h
\ No newline at end of file