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authorIan Romanick <idr@us.ibm.com>2005-11-08 22:40:26 +0000
committerIan Romanick <idr@us.ibm.com>2005-11-08 22:40:26 +0000
commit4884db6eb29d30a16e5bf72da08ea6095ecd3339 (patch)
treeb4087a2a68b008ff318a55d643d9ea0970e51ed0 /src/mesa/tnl/t_vb_arbprogram.h
parente1a5edf083efb065f97ec08592ae2c4ff6fc6662 (diff)
This patch adds the missing NV_vertex_program2 and NV_vertex_program3
instructions to the various internal tables. It does not add support for them to the parser nor does it add support for them to the program interpreter. It also corrects some errors in the comments in program_instruction.h. This patch breaks the instruction union in t_vb_arbprogram.h. The opcode field in that union was only 6 bits. When there were only 59+3 instructions that worked fine. However, this patch increases the base instruction count to 69. This requires 7 bits. The problem is that increasing the opcode width to 7 bits increases the size of instruction::rsw to 33 bits. I've increased the size of the union to 64-bit, but this is just a temporary hack (and probably breaks the build on some systems).
Diffstat (limited to 'src/mesa/tnl/t_vb_arbprogram.h')
-rw-r--r--src/mesa/tnl/t_vb_arbprogram.h16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/mesa/tnl/t_vb_arbprogram.h b/src/mesa/tnl/t_vb_arbprogram.h
index 93692c92cd..a3cf1d8ca1 100644
--- a/src/mesa/tnl/t_vb_arbprogram.h
+++ b/src/mesa/tnl/t_vb_arbprogram.h
@@ -71,7 +71,7 @@
#define REG_INVALID ~0
/* ARB_vp instructions are broken down into one or more of the
- * following micro-instructions, each representable in a 32 bit packed
+ * following micro-instructions, each representable in a 64 bit packed
* structure.
*/
struct reg {
@@ -82,17 +82,18 @@ struct reg {
union instruction {
struct {
- GLuint opcode:6;
+ GLuint opcode:7;
GLuint dst:5;
GLuint file0:2;
GLuint idx0:7;
GLuint file1:2;
GLuint idx1:7;
- GLuint pad:3;
+ GLuint pad:2;
+ GLuint pad2;
} alu;
struct {
- GLuint opcode:6;
+ GLuint opcode:7;
GLuint dst:5;
GLuint file0:2;
GLuint idx0:7;
@@ -101,15 +102,16 @@ union instruction {
} rsw;
struct {
- GLuint opcode:6;
+ GLuint opcode:7;
GLuint dst:5;
GLuint file:2;
GLuint idx:7;
GLuint mask:4;
- GLuint pad:1;
+ GLuint pad:7;
+ GLuint pad2;
} msk;
- GLuint dword;
+ long long dword;
};