diff options
Diffstat (limited to 'src/mesa/drivers/dri/r200/r200_cmdbuf.c')
| -rw-r--r-- | src/mesa/drivers/dri/r200/r200_cmdbuf.c | 47 |
1 files changed, 41 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c index 3a11a448ec..df9dd83344 100644 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c @@ -105,6 +105,35 @@ void r200SetUpAtomList( r200ContextPtr rmesa ) insert_at_tail( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); } +void r200EmitScissor(r200ContextPtr rmesa) +{ + BATCH_LOCALS(&rmesa->radeon); + if (!rmesa->radeon.radeonScreen->kernel_mm) { + return; + } + if (rmesa->radeon.state.scissor.enabled) { + BEGIN_BATCH(8); + OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0)); + OUT_BATCH(R200_SCISSOR_ENABLE | rmesa->hw.set.cmd[SET_RE_CNTL]); + OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0)); + OUT_BATCH(R200_SCISSOR_ENABLE_0); + OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_TL_0, 0)); + OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | + rmesa->radeon.state.scissor.rect.x1); + OUT_BATCH(CP_PACKET0(R200_RE_SCISSOR_BR_0, 0)); + OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2 - 1) << 16) | + (rmesa->radeon.state.scissor.rect.x2 - 1)); + END_BATCH(); + } else { + BEGIN_BATCH(4); + OUT_BATCH(CP_PACKET0(R200_RE_CNTL, 0)); + OUT_BATCH(rmesa->hw.set.cmd[SET_RE_CNTL] & ~R200_SCISSOR_ENABLE); + OUT_BATCH(CP_PACKET0(R200_RE_AUX_SCISSOR_CNTL, 0)); + OUT_BATCH(0); + END_BATCH(); + } +} + /* Fire a section of the retained (indexed_verts) buffer as a regular * primtive. */ @@ -121,6 +150,7 @@ void r200EmitVbufPrim( r200ContextPtr rmesa, if (R200_DEBUG & (DEBUG_IOCTL|DEBUG_PRIMS)) fprintf(stderr, "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, rmesa->store.cmd_used/4, primitive, vertex_nr); + r200EmitScissor(rmesa); BEGIN_BATCH(3); OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); @@ -134,9 +164,11 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) BATCH_LOCALS(&rmesa->radeon); if (vertex_count > 0) { + r200EmitScissor(rmesa); BEGIN_BATCH(8+2); - OUT_BATCH_PACKET3(R200_CP_CMD_3D_DRAW_INDX_2, 0); + OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); OUT_BATCH(R200_VF_PRIM_WALK_IND | + R200_VF_COLOR_ORDER_RGBA | ((vertex_count + 0) << 16) | type); @@ -147,12 +179,12 @@ static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) rmesa->radeon.tcl.elt_dma_bo, rmesa->radeon.tcl.elt_dma_offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - OUT_BATCH(vertex_count/2); + OUT_BATCH((vertex_count + 1)/2); } else { OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); - OUT_BATCH(vertex_count/2); + OUT_BATCH((vertex_count + 1)/2); radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, rmesa->radeon.tcl.elt_dma_bo, RADEON_GEM_DOMAIN_GTT, 0, 0); @@ -172,8 +204,6 @@ void r200FlushElts(GLcontext *ctx) assert( rmesa->radeon.dma.flush == r200FlushElts ); rmesa->radeon.dma.flush = NULL; - elt_used = (elt_used + 2) & ~2; - nr = elt_used / 2; radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); @@ -209,6 +239,11 @@ GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, rmesa->radeon.tcl.elt_dma_offset = 0; rmesa->tcl.elt_used = min_nr * 2; + radeon_validate_bo(&rmesa->radeon, rmesa->radeon.tcl.elt_dma_bo, + RADEON_GEM_DOMAIN_GTT, 0); + if (radeon_revalidate_bos(rmesa->radeon.glCtx) == GL_FALSE) + fprintf(stderr,"failure to revalidate BOs - badness\n"); + radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; @@ -238,7 +273,7 @@ void r200EmitVertexAOS( r200ContextPtr rmesa, __FUNCTION__, vertex_size, offset); - BEGIN_BATCH(5); + BEGIN_BATCH(7); OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); OUT_BATCH(1); OUT_BATCH(vertex_size | (vertex_size << 8)); |