| Age | Commit message (Collapse) | Author |
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Fewer float/int conversions involved.
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Plus, clearer shuffle masks in other funcs.
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The glsl/multitex demo runs now.
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Lots of restrictions for now (one 2D texture, no mipmaps, etc.) for now
but basic texture demos work.
TEX, TXD, TXP do the same thing for the time being.
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This set of code changes are for stencil code generation
support. Both one-sided and two-sided stenciling are supported.
In addition to the raw code generation changes, these changes had
to be made elsewhere in the system:
- Added new "register set" feature to the SPE assembly generation.
A "register set" is a way to allocate multiple registers and free
them all at the same time, delegating register allocation management
to the spe_function unit. It's quite useful in complex register
allocation schemes (like stenciling).
- Added and improved SPE macro calculations.
These are operations between registers and unsigned integer
immediates. In many cases, the calculation can be performed
with a single instruction; the macros will generate the
single instruction if possible, or generate a register load
and register-to-register operation if not. These macro
functions are: spe_load_uint() (which has new ways to
load a value in a single instruction), spe_and_uint(),
spe_xor_uint(), spe_compare_equal_uint(), and spe_compare_greater_uint().
- Added facing to fragment generation. While rendering, the rasterizer
needs to be able to determine front- and back-facing fragments, in order
to correctly apply two-sided stencil. That requires these changes:
- Added front_winding field to the cell_command_render block, so that
the state tracker could communicate to the rasterizer what it
considered to be the front-facing direction.
- Added fragment facing as an input to the fragment function.
- Calculated facing is passed during emit_quad().
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Will be used for instructions like SIN/COS/POW/TEX/etc. The PPU needs to
know the address of some functions in the SPU address space. Send that
info to the PPU/main memory rather than patch up shaders on the SPU side.
Not finished/tested yet...
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32-byte boundary
To make sure even/odd instructions hit the right pipes.
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cmd_state_fragment_ops() was inverted
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progs/demos: added new demo "fbo_firecube"
progs/glsl: added new demo "pointcoord"
src/gallium/drivers/cell/spu: added the g3d_spu executable, a Cell SPU
executable file, which seems to be occasionally built as part of the
cell driver
src/glu/sgi: added "exptmp", a byproduct of the "mklib" process that
sometimes gets deleted and sometimes not.
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- Added two new debug flags (to be used with the CELL_DEBUG environment
variable). The first, "CELL_DEBUG=fragops", activates SPE fragment
ops debug messages. The second, "CELL_DEBUG=fragopfallback", will
eventually be used to disable the use of generated SPE code for
fragment ops in favor of the default fallback reference routine.
(During development, though, the parity of this flag is reversed:
all users will get the reference code *unless* CELL_DEBUG=fragopfallback
is set. This will prevent hiccups in code generation from affecting
the other developers.)
- Formalized debug message usage and macros in spu/spu_main.c.
- Added lots of new code to ppu/cell_gen_fragment.c to extend the
number of supported source RGB factors from 4 to 15, and to
complete the list of supported blend equations.
More coming, to complete the source and destination RGB and alpha
factors, and to complete the rest of the fragment operations...
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Also, some var renaming and additional comments
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Also remove old code, etc.
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TGSI shaders are translated into SPE instructions which are then sent to
the SPEs for execution. Only a few opcodes work, no swizzling yet, no
support for constants/immediates, etc.
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Do code generation for alpha test, z test, stencil, blend, colormask
and framebuffer/tile read/write as a single code block.
Ian's previous blend/z/stencil test code is still there but mostly disabled
and will be removed soon.
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Options so far:
"checker" module tile clear color by SPU ID to see where the tiles are
"sync" to do synchronous DMA (only partially implemented)
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Note that SPU vertex transformation is disabled at this time.
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Also, rename p_tile.[ch] to u_tile.[ch]
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