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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
AgeCommit message (Expand)Author
2010-10-13Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg
2010-09-29Revert "i965: Always set tiling for depth buffer on sandybridge"Zhenyu Wang
2010-09-29i965: Always set tiling for depth buffer on sandybridgeZhenyu Wang
2010-08-31i965: fix depth test on sandybridgeZhenyu Wang
2010-08-22i965: Use intel->gen >= 6 instead of IS_GEN6.Eric Anholt
2010-06-12i965: Stream out CC unit state.Eric Anholt
2010-06-11i965: Use the state base address to avoid relocations.Eric Anholt
2010-06-11i965: Convert the binding table to streamed indirect state.Eric Anholt
2010-05-26i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.Eric Anholt
2010-05-26i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.Eric Anholt
2010-04-21intel: Clean up chipset name and gen num for IronlakeZhenyu Wang
2010-02-25i965: Add a couple SNB state packets I saw in other batchbuffer dumps.Eric Anholt
2010-02-25i965: Hook up remaining Sandybridge state packets besides WM.Eric Anholt
2010-02-25i965: Set the state base address on Sandybridge.Eric Anholt
2010-02-25i965: Set up sandybridge binding table pointers but don't enable it yet.Eric Anholt
2010-02-25i965: Set up sandybridge depthbuffer.Eric Anholt
2010-01-26i965: Remove DRI1 leftovers from stipple offset handling.Eric Anholt
2010-01-04intel: Drop more cliprect bookkeepingKristian Høgsberg
2010-01-04intel: Drop batchbuffer cliprect_mode trackingKristian Høgsberg
2010-01-04Remove leftover __DRI{screen,drawable,context}Private referencesKristian Høgsberg
2009-12-22intel: Replace IS_965 checks with context structure usage.Eric Anholt
2009-12-22intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt
2009-12-22intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt
2009-11-13i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt
2009-09-02i965: validate sf stateXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-23i965: Fix packed depth/stencil textures to be Y-tiled as well.Eric Anholt
2009-05-06i965: Disentangle VS constant surface state from WM surface state.Eric Anholt
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
2009-03-12i965: fix polygon stipple when rendering to FBORobert Ellison
2009-02-25i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt
2009-02-02i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
2008-10-28i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt
2008-10-28intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt
2008-10-24i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
2008-08-08965: cleanups to state emission from aperture checking and state ordering.Eric Anholt
2008-07-25Merge branch 'master' into drm-gemIan Romanick
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
2008-05-07GEM: Remove already-disabled PIPE_CONTROL command.Eric Anholt
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
2008-04-18i965: fixup depth buffer checkDave Airlie
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
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