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PRE_EMIT_STATE_BUFSZ accounts for the start 3d, idle, cd/db flush
not for state. The relocs for CB_COLOR0_FRAG & CB_COLOR0_TILE
are part of the render target state.
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This reverts commit 325614a882f5371da512536e07c443a172ffb87c.
Ok this was already fixed this commit actualy broke things
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To avoid kernel complaining and to set proper boundary on
vbo, substract the vbo offset to the vbo size.
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to make kernel cs checker happier, last attribs don't need full stride of
space. Calculate as count-1*stride + size of attrib
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normalized seems to work with this setting.
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fixes some fbo cases (mipmaps, cube textures ..)
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FRAG & TILE buffer are unused but still they need
to be associated with a valid relocation so that
userspace can't try to abuse them to overwritte
GART and then try to write anywhere in system
memory.
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R600_OUT_BATCH_RELOC doesn't really use offset so set it
in TEX_RESOURCE2
+ typo fix
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at least i think this is how it was meant to work
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Conflicts:
src/gallium/state_trackers/xorg/xorg_xv.c
src/mesa/drivers/dri/intel/intel_span.c
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Conflicts:
src/mesa/drivers/dri/r600/r700_assembler.c
src/mesa/main/version.h
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First time around render targets are not enabled yet (done in
r700SendRenderTargetState) so blend state is not emitted for any targets.
Affects first glClear in some mesa tests.
As a quick fix reorder state emit so that target is set first
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These are needed for HiZ which is not currently used and
the _BASE reg requires a reloc which is not currently supported
in the drm.
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These are needed for HiZ which is not currently used and
the _BASE reg requires a reloc which is not currently supported
in the drm.
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Based on initial patch from Stephan Schmid <stephan_2303@gmx.de>.
Basic idea is to dump the zpass count at the start and end of the query
and subtract to get the total number of visible fragments. HW writes
alternating qwords for up to 4 DBs. On the first pass, we start at
buffer address + 0; on the second pass, we start at buffer address + 8
(bytes). The resulting buffer at the end of the query looks like:
qw[0]: db0 start
qw[1]: db0 end
...
qw[6]: db3 start
qw[7]: db3 end
The MSB of each qword is the valid bit and the lower 63 bits are
the zpass count for that DB.
OQ on RV740 is disabled at the moment as it only seems to report
results for half of its DBs. This needs further investigation.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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noticed by taiu on IRC.
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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noticed by taiu on IRC.
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Setup the regs when we emit rather than during state setup.
In certain cases a proper CB target was never emitted.
This fixes bug 23658.
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There is only a few functions that have debugging enabled now.
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Gives a nice speed boost in most apps since
we only emit what state we need.
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Hopefully suokko's emit size impovements will
land soon.
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switches more state handling to common code. We need
should be more fine grained with the state atoms
eventually.
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Slowing migrating to atom based system like
the other radeon drivers.
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We probably want to go finer grained eventually, but
this is a good start.
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These regs don't use the SET_CONTEXT_REG packet,
so they weren't getting set correctly.
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make sure we allocate enough space for relocs
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