Merge remote branch 'origin/master' into nvc0-new

1 files changed, 23 insertions, 23 deletions

diff --git a/src/mesa/drivers/dri/nouveau/nv20_render.c b/src/mesa/drivers/dri/nouveau/nv20_render.c
index dbdb85da20..2bdc85cda4 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_render.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_render.c
@@ -26,7 +26,7 @@
 
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv20_driver.h"
 
 #define NUM_VERTEX_ATTRS 16
@@ -39,47 +39,47 @@ nv20_emit_material(struct gl_context *ctx, struct nouveau_array *a,
 static struct nouveau_attr_info nv20_vertex_attrs[VERT_ATTRIB_MAX] = {
 	[VERT_ATTRIB_POS] = {
 		.vbo_index = 0,
-		.imm_method = NV20TCL_VERTEX_POS_4F_X,
+		.imm_method = NV20_3D_VERTEX_POS_4F_X,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_NORMAL] = {
 		.vbo_index = 2,
-		.imm_method = NV20TCL_VERTEX_NOR_3F_X,
+		.imm_method = NV20_3D_VERTEX_NOR_3F_X,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_COLOR0] = {
 		.vbo_index = 3,
-		.imm_method = NV20TCL_VERTEX_COL_4F_X,
+		.imm_method = NV20_3D_VERTEX_COL_4F,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_COLOR1] = {
 		.vbo_index = 4,
-		.imm_method = NV20TCL_VERTEX_COL2_3F_X,
+		.imm_method = NV20_3D_VERTEX_COL2_3F,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_FOG] = {
 		.vbo_index = 5,
-		.imm_method = NV20TCL_VERTEX_FOG_1F,
+		.imm_method = NV20_3D_VERTEX_FOG_1F,
 		.imm_fields = 1,
 	},
 	[VERT_ATTRIB_TEX0] = {
 		.vbo_index = 9,
-		.imm_method = NV20TCL_VERTEX_TX0_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX0_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX1] = {
 		.vbo_index = 10,
-		.imm_method = NV20TCL_VERTEX_TX1_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX1_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX2] = {
 		.vbo_index = 11,
-		.imm_method = NV20TCL_VERTEX_TX2_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX2_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX3] = {
 		.vbo_index = 12,
-		.imm_method = NV20TCL_VERTEX_TX3_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX3_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_GENERIC0] = {
@@ -119,11 +119,11 @@ get_hw_format(int type)
 {
 	switch (type) {
 	case GL_FLOAT:
-		return NV20TCL_VTXFMT_TYPE_FLOAT;
+		return NV20_3D_VTXBUF_FMT_TYPE_FLOAT;
 	case GL_UNSIGNED_SHORT:
-		return NV20TCL_VTXFMT_TYPE_USHORT;
+		return NV20_3D_VTXBUF_FMT_TYPE_USHORT;
 	case GL_UNSIGNED_BYTE:
-		return NV20TCL_VTXFMT_TYPE_UBYTE;
+		return NV20_3D_VTXBUF_FMT_TYPE_UBYTE;
 	default:
 		assert(0);
 	}
@@ -147,10 +147,10 @@ nv20_render_set_format(struct gl_context *ctx)
 
 		} else {
 			/* Unused attribute. */
-			hw_format = NV10TCL_VTXFMT_TYPE_FLOAT;
+			hw_format = NV20_3D_VTXBUF_FMT_TYPE_FLOAT;
 		}
 
-		BEGIN_RING(chan, kelvin, NV20TCL_VTXFMT(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_VTXBUF_FMT(i), 1);
 		OUT_RING(chan, hw_format);
 	}
 }
@@ -167,9 +167,9 @@ nv20_render_bind_vertices(struct gl_context *ctx)
 		struct nouveau_array *a = &render->attrs[attr];
 
 		nouveau_bo_mark(bctx, kelvin,
-				NV20TCL_VTXBUF_ADDRESS(i),
+				NV20_3D_VTXBUF_OFFSET(i),
 				a->bo, a->offset, 0,
-				0, NV20TCL_VTXBUF_ADDRESS_DMA1,
+				0, NV20_3D_VTXBUF_OFFSET_DMA1,
 				NOUVEAU_BO_LOW | NOUVEAU_BO_OR |
 				NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 	}
@@ -180,33 +180,33 @@ nv20_render_bind_vertices(struct gl_context *ctx)
 	struct nouveau_grobj *kelvin = context_eng3d(ctx)
 
 #define BATCH_VALIDATE()						\
-	BEGIN_RING(chan, kelvin, NV20TCL_VTX_CACHE_INVALIDATE, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VTXBUF_VALIDATE, 1);	\
 	OUT_RING(chan, 0)
 
 #define BATCH_BEGIN(prim)					\
-	BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VERTEX_BEGIN_END, 1);	\
 	OUT_RING(chan, prim)
 #define BATCH_END()						\
-	BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VERTEX_BEGIN_END, 1);	\
 	OUT_RING(chan, 0)
 
 #define MAX_PACKET 0x400
 
 #define MAX_OUT_L 0x100
 #define BATCH_PACKET_L(n)						\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_VERTEX_BATCH, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_BATCH, n)
 #define BATCH_OUT_L(i, n)			\
 	OUT_RING(chan, ((n) - 1) << 24 | (i))
 
 #define MAX_OUT_I16 0x2
 #define BATCH_PACKET_I16(n)					\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_ELEMENT_U16, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_ELEMENT_U16, n)
 #define BATCH_OUT_I16(i0, i1)			\
 	OUT_RING(chan, (i1) << 16 | (i0))
 
 #define MAX_OUT_I32 0x1
 #define BATCH_PACKET_I32(n)					\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_ELEMENT_U32, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_ELEMENT_U32, n)
 #define BATCH_OUT_I32(i)			\
 	OUT_RING(chan, i)