Merge remote branch 'origin/master' into nvc0-new

author: Christoph Bumiller <e0425955@student.tuwien.ac.at> 2010-12-19 21:46:33 +0100
committer: Christoph Bumiller <e0425955@student.tuwien.ac.at> 2010-12-19 21:46:33 +0100
commit: 0f68236a2487dbeb0396b996debcda595b0b54a1 (patch)
tree: 938ae3b779349b6dba6f5a891550604f9a9ca895 /src/mesa/drivers/dri
parent: d047168d81cfeb39a98f3ae16416872facc6237c (diff)
parent: 237880463d5168cad8df0bae6018b5fd76617777 (diff)
146 files changed, 10275 insertions, 8319 deletions
diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template
index a00018cafa..4ecddbc048 100644
--- a/src/mesa/drivers/dri/Makefile.template
+++ b/src/mesa/drivers/dri/Makefile.template
@@ -86,11 +86,12 @@ subdirs:
 symlinks:
 
 
-depend: $(C_SOURCES) $(ASM_SOURCES) $(SYMLINKS)
+depend: $(C_SOURCES) $(CXX_SOURCES) $(ASM_SOURCES) $(SYMLINKS)
 	@ echo "running $(MKDEP)"
 	@ rm -f depend
 	@ touch depend
-	@ $(MKDEP) $(MKDEP_OPTIONS) $(DRIVER_DEFINES) $(INCLUDES) $(C_SOURCES) \
+	@ $(MKDEP) $(MKDEP_OPTIONS) $(DRIVER_DEFINES) $(INCLUDES) \
+		$(C_SOURCES) $(CXX_SOURCES) \
 		$(ASM_SOURCES) > /dev/null 2>/dev/null
 
 
diff --git a/src/mesa/drivers/dri/common/spantmp2.h b/src/mesa/drivers/dri/common/spantmp2.h
index abd79562f9..f436d1398c 100644
--- a/src/mesa/drivers/dri/common/spantmp2.h
+++ b/src/mesa/drivers/dri/common/spantmp2.h
@@ -48,6 +48,15 @@
 #define HW_WRITE_CLIPLOOP()	HW_CLIPLOOP()
 #endif
 
+#ifdef SPANTMP_MESA_FMT
+#define SPANTMP_PIXEL_FMT GL_NONE
+#define SPANTMP_PIXEL_TYPE GL_NONE
+#endif
+
+#ifndef SPANTMP_MESA_FMT
+#define SPANTMP_MESA_FMT MESA_FORMAT_COUNT
+#endif
+
 #if (SPANTMP_PIXEL_FMT == GL_RGB)  && (SPANTMP_PIXEL_TYPE == GL_UNSIGNED_SHORT_5_6_5)
 
 /**
@@ -445,6 +454,118 @@
 	rgba[3] = p;							\
      } while (0)
 
+#elif (SPANTMP_MESA_FMT == MESA_FORMAT_R8)
+
+#ifndef GET_VALUE
+#ifndef GET_PTR
+#define GET_PTR(_x, _y) (     buf + (_x) + (_y) * pitch)
+#endif
+
+#define GET_VALUE(_x, _y) *(volatile GLubyte *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLubyte *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
+# define INIT_MONO_PIXEL(p, color)                       \
+     p = color[0]
+
+# define WRITE_RGBA(_x, _y, r, g, b, a)                                 \
+   PUT_VALUE(_x, _y, r)
+
+#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
+
+#define READ_RGBA( rgba, _x, _y )				        \
+     do {								\
+        GLubyte p = GET_VALUE(_x, _y);					\
+	rgba[0] = p;							\
+	rgba[1] = 0;							\
+	rgba[2] = 0;							\
+	rgba[3] = 0;							\
+     } while (0)
+
+#elif (SPANTMP_MESA_FMT == MESA_FORMAT_RG88)
+
+#ifndef GET_VALUE
+#ifndef GET_PTR
+#define GET_PTR(_x, _y) (     buf + (_x) * 2 + (_y) * pitch)
+#endif
+
+#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
+# define INIT_MONO_PIXEL(p, color)                       \
+   PACK_COLOR_8888(color[0], color[1], 0, 0)
+
+# define WRITE_RGBA(_x, _y, r, g, b, a)                                 \
+   PUT_VALUE(_x, _y, r)
+
+#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
+
+#define READ_RGBA( rgba, _x, _y )				        \
+     do {								\
+        GLushort p = GET_VALUE(_x, _y);					\
+	rgba[0] = p & 0xff;						\
+	rgba[1] = (p >> 8) & 0xff;					\
+	rgba[2] = 0;							\
+	rgba[3] = 0;							\
+     } while (0)
+
+#elif (SPANTMP_MESA_FMT == MESA_FORMAT_R16)
+
+#ifndef GET_VALUE
+#ifndef GET_PTR
+#define GET_PTR(_x, _y) (     buf + (_x) * 2 + (_y) * pitch)
+#endif
+
+#define GET_VALUE(_x, _y) *(volatile GLushort *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLushort *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
+# define INIT_MONO_PIXEL(p, color)                       \
+     p = color[0]
+
+# define WRITE_RGBA(_x, _y, r, g, b, a)                                 \
+   PUT_VALUE(_x, _y, r)
+
+#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
+
+#define READ_RGBA( rgba, _x, _y )				        \
+     do {								\
+        GLushort p = GET_VALUE(_x, _y);					\
+	rgba[0] = p;							\
+	rgba[1] = 0;							\
+	rgba[2] = 0;							\
+	rgba[3] = 0;							\
+     } while (0)
+
+#elif (SPANTMP_MESA_FMT == MESA_FORMAT_RG1616)
+
+#ifndef GET_VALUE
+#ifndef GET_PTR
+#define GET_PTR(_x, _y) (     buf + (_x) * 4 + (_y) * pitch)
+#endif
+
+#define GET_VALUE(_x, _y) *(volatile GLuint *)(GET_PTR(_x, _y))
+#define PUT_VALUE(_x, _y, _v) *(volatile GLuint *)(GET_PTR(_x, _y)) = (_v)
+#endif /* GET_VALUE */
+
+# define INIT_MONO_PIXEL(p, color)                       \
+   ((color[1] << 16) | (color[0]))
+
+# define WRITE_RGBA(_x, _y, r, g, b, a)                                 \
+   PUT_VALUE(_x, _y, r)
+
+#define WRITE_PIXEL(_x, _y, p) PUT_VALUE(_x, _y, p)
+
+#define READ_RGBA( rgba, _x, _y )				        \
+     do {								\
+        GLuint p = GET_VALUE(_x, _y);					\
+	rgba[0] = p & 0xffff;						\
+	rgba[1] = (p >> 16) & 0xffff;					\
+	rgba[2] = 0;							\
+	rgba[3] = 0;							\
+     } while (0)
+
 #else
 #error SPANTMP_PIXEL_FMT must be set to a valid value!
 #endif
@@ -914,3 +1035,4 @@ static void TAG(InitPointers)(struct gl_renderbuffer *rb)
 #undef GET_PTR
 #undef SPANTMP_PIXEL_FMT
 #undef SPANTMP_PIXEL_TYPE
+#undef SPANTMP_MESA_FMT
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index f7fdb78d05..1621c9544a 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -364,7 +364,7 @@ i830_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit( intel, state, size )			\
-   intel_batchbuffer_data(intel->batch, state, size )
+   intel_batchbuffer_data(intel->batch, state, size, false)
 
 static GLuint
 get_dirty(struct i830_hw_state *state)
@@ -429,7 +429,8 @@ i830_emit_state(struct intel_context *intel)
     * batchbuffer fills up.
     */
    intel_batchbuffer_require_space(intel->batch,
-				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
+				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+				   false);
    count = 0;
  again:
    aper_count = 0;
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index f943f81dd0..f32f3cf602 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -176,6 +176,7 @@ i915CreateContext(int api,
    ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitCondCodes = GL_TRUE;
    ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoIfs = GL_TRUE;
    ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoNoise = GL_TRUE;
+   ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoPow = GL_TRUE;
 
    ctx->Const.MaxDrawBuffers = 1;
 
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index c00ee415b6..1c6e984517 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -569,10 +569,14 @@ upload_program(struct i915_fragment_program *p)
 	 if (inst->DstReg.CondMask == COND_TR) {
 	    tmp = i915_get_utemp(p);
 
+	    /* The KIL instruction discards the fragment if any component of
+	     * the source is < 0.  Emit an immediate operand of {-1}.xywz.
+	     */
 	    i915_emit_texld(p, get_live_regs(p, inst),
 			    tmp, A0_DEST_CHANNEL_ALL,
 			    0, /* use a dummy dest reg */
-			    swizzle(tmp, ONE, ONE, ONE, ONE), /* always */
+			    negate(swizzle(tmp, ONE, ONE, ONE, ONE),
+				   1, 1, 1, 1),
 			    T0_TEXKILL);
 	 } else {
 	    p->error = 1;
@@ -1158,11 +1162,6 @@ translate_program(struct i915_fragment_program *p)
    fixup_depth_write(p);
    i915_fini_program(p);
 
-   if (INTEL_DEBUG & DEBUG_WM) {
-      printf("i915:\n");
-      i915_disassemble_program(i915->state.Program, i915->state.ProgramSize);
-   }
-
    p->translated = 1;
 }
 
@@ -1423,6 +1422,11 @@ i915ValidateFragmentProgram(struct i915_context *i915)
 
    if (!p->on_hardware)
       i915_upload_program(i915, p);
+
+   if (INTEL_DEBUG & DEBUG_WM) {
+      printf("i915:\n");
+      i915_disassemble_program(i915->state.Program, i915->state.ProgramSize);
+   }
 }
 
 void
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 59dfe08563..8d9020f5ef 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -217,7 +217,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 
 
 #define emit(intel, state, size )		     \
-   intel_batchbuffer_data(intel->batch, state, size)
+   intel_batchbuffer_data(intel->batch, state, size, false)
 
 static GLuint
 get_dirty(struct i915_hw_state *state)
@@ -300,7 +300,8 @@ i915_emit_state(struct intel_context *intel)
     * batchbuffer fills up.
     */
    intel_batchbuffer_require_space(intel->batch,
-				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
+				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+				   false);
    count = 0;
  again:
    aper_count = 0;
diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index e3ca863fe5..7c3ac0c14e 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -81,7 +81,6 @@ DRIVER_SOURCES = \
 	brw_wm_emit.c \
 	brw_wm_fp.c \
 	brw_wm_iz.c \
-	brw_wm_glsl.c \
 	brw_wm_pass0.c \
 	brw_wm_pass1.c \
 	brw_wm_pass2.c \
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c
index a8369b07c3..d3a1233aac 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -232,3 +232,28 @@ const struct brw_tracked_state brw_cc_unit = {
    .prepare = prepare_cc_unit,
    .emit = upload_cc_unit,
 };
+
+static void upload_blend_constant_color(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->intel.ctx;
+   struct brw_blend_constant_color bcc;
+
+   memset(&bcc, 0, sizeof(bcc));
+   bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
+   bcc.header.length = sizeof(bcc)/4-2;
+   bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
+   bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
+   bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
+   bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
+
+   BRW_CACHED_BATCH_STRUCT(brw, &bcc);
+}
+
+const struct brw_tracked_state brw_blend_constant_color = {
+   .dirty = {
+      .mesa = _NEW_COLOR,
+      .brw = BRW_NEW_CONTEXT,
+      .cache = 0
+   },
+   .emit = upload_blend_constant_color
+};
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index cb0a8b96c9..28549f2574 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -122,9 +122,6 @@ GLboolean brwCreateContext( int api,
 	 (i == MESA_SHADER_FRAGMENT);
       ctx->ShaderCompilerOptions[i].EmitNoIndirectTemp =
 	 (i == MESA_SHADER_FRAGMENT);
-
-      if (intel->gen == 6)
-	 ctx->ShaderCompilerOptions[i].EmitNoIfs = (i == MESA_SHADER_VERTEX);
    }
 
    ctx->Const.VertexProgram.MaxNativeInstructions = (16 * 1024);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 335339515a..7069724466 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -171,7 +171,6 @@ struct brw_vertex_program {
 struct brw_fragment_program {
    struct gl_fragment_program program;
    GLuint id;  /**< serial no. to identify frag progs, never re-used */
-   GLboolean isGLSL;  /**< really, any IF/LOOP/CONT/BREAK instructions */
 
    /** for debugging, which texture units are referenced */
    GLbitfield tex_units_used;
@@ -211,6 +210,7 @@ struct brw_wm_prog_data {
    GLuint nr_params;       /**< number of float params/constants */
    GLuint nr_pull_params;
    GLboolean error;
+   int dispatch_width;
 
    /* Pointer to tracked values (only valid once
     * _mesa_load_state_parameters has been called at runtime).
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 7b823eb201..877b22fec1 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -242,21 +242,13 @@ static void prepare_constant_buffer(struct brw_context *brw)
       GLuint offset = brw->curbe.vs_start * 16;
       GLuint nr = brw->vs.prog_data->nr_params / 4;
 
-      if (vp->use_const_buffer) {
-	 /* Load the subset of push constants that will get used when
-	  * we also have a pull constant buffer.
-	  */
-	 for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
-	    if (brw->vs.constant_map[i] != -1) {
-	       assert(brw->vs.constant_map[i] <= nr);
-	       memcpy(buf + offset + brw->vs.constant_map[i] * 4,
-		      vp->program.Base.Parameters->ParameterValues[i],
-		      4 * sizeof(float));
-	    }
-	 }
-      } else {
-	 for (i = 0; i < nr; i++) {
-	    memcpy(buf + offset + i * 4,
+      /* Load the subset of push constants that will get used when
+       * we also have a pull constant buffer.
+       */
+      for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
+	 if (brw->vs.constant_map[i] != -1) {
+	    assert(brw->vs.constant_map[i] <= nr);
+	    memcpy(buf + offset + brw->vs.constant_map[i] * 4,
 		   vp->program.Base.Parameters->ParameterValues[i],
 		   4 * sizeof(float));
 	 }
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 239586a036..b48a30d6be 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -462,6 +462,13 @@
 #define BRW_COMPRESSION_2NDHALF       1
 #define BRW_COMPRESSION_COMPRESSED    2
 
+#define GEN6_COMPRESSION_1Q		0
+#define GEN6_COMPRESSION_2Q		1
+#define GEN6_COMPRESSION_3Q		2
+#define GEN6_COMPRESSION_4Q		3
+#define GEN6_COMPRESSION_1H		0
+#define GEN6_COMPRESSION_2H		2
+
 #define BRW_CONDITIONAL_NONE  0
 #define BRW_CONDITIONAL_Z     1
 #define BRW_CONDITIONAL_NZ    2
@@ -899,6 +906,8 @@
 # define GEN6_VS_VECTOR_MASK_ENABLE			(1 << 30)
 # define GEN6_VS_SAMPLER_COUNT_SHIFT			27
 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+# define GEN6_VS_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
+# define GEN6_VS_FLOATING_POINT_MODE_ALT		(1 << 16)
 /* DW4 */
 # define GEN6_VS_DISPATCH_START_GRF_SHIFT		20
 # define GEN6_VS_URB_READ_LENGTH_SHIFT			11
@@ -1022,6 +1031,13 @@
 # define ATTRIBUTE_0_CONST_SOURCE_SHIFT			9
 # define ATTRIBUTE_0_SWIZZLE_SHIFT			6
 # define ATTRIBUTE_0_SOURCE_SHIFT			0
+
+# define ATTRIBUTE_SWIZZLE_INPUTATTR                    0
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING             1
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_W                  2
+# define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W           3
+# define ATTRIBUTE_SWIZZLE_SHIFT                        6
+
 /* DW16: Point sprite texture coordinate enables */
 /* DW17: Constant interpolation enables */
 /* DW18: attr 0-7 wrap shortest enables */
@@ -1034,6 +1050,8 @@
 # define GEN6_WM_VECTOR_MASK_ENABLE			(1 << 30)
 # define GEN6_WM_SAMPLER_COUNT_SHIFT			27
 # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT	18
+# define GEN6_WM_FLOATING_POINT_MODE_IEEE_754		(0 << 16)
+# define GEN6_WM_FLOATING_POINT_MODE_ALT		(1 << 16)
 /* DW3: scratch space */
 /* DW4 */
 # define GEN6_WM_STATISTICS_ENABLE			(1 << 31)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 962c04128b..6b61f7af15 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -899,7 +899,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
 	err |= dest (file, inst);
     } else if (gen >= 6 && (inst->header.opcode == BRW_OPCODE_IF ||
 			    inst->header.opcode == BRW_OPCODE_ELSE ||
-			    inst->header.opcode == BRW_OPCODE_ENDIF)) {
+			    inst->header.opcode == BRW_OPCODE_ENDIF ||
+			    inst->header.opcode == BRW_OPCODE_WHILE)) {
        format (file, " %d", inst->bits1.branch_gen6.jump_count);
     }
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index a1f403ca4e..7eb16b71f4 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -159,7 +159,7 @@ static void brw_emit_prim(struct brw_context *brw,
    }
    if (prim_packet.verts_per_instance) {
       intel_batchbuffer_data( brw->intel.batch, &prim_packet,
-			      sizeof(prim_packet));
+			      sizeof(prim_packet), false);
    }
    if (intel->always_flush_cache) {
       intel_batchbuffer_emit_mi_flush(intel->batch);
@@ -351,7 +351,8 @@ static GLboolean brw_try_draw_prims( struct gl_context *ctx,
        * an upper bound of how much we might emit in a single
        * brw_try_draw_prims().
        */
-      intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4);
+      intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4,
+				      false);
 
       hw_prim = brw_set_prim(brw, &prim[i]);
 
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 2ff39e8e64..3b5c4c071e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -72,7 +72,37 @@ void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
 
 void brw_set_compression_control( struct brw_compile *p, GLboolean compression_control )
 {
-   p->current->header.compression_control = compression_control;
+   p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
+
+   if (p->brw->intel.gen >= 6) {
+      /* Since we don't use the 32-wide support in gen6, we translate
+       * the pre-gen6 compression control here.
+       */
+      switch (compression_control) {
+      case BRW_COMPRESSION_NONE:
+	 /* This is the "use the first set of bits of dmask/vmask/arf
+	  * according to execsize" option.
+	  */
+	 p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+	 break;
+      case BRW_COMPRESSION_2NDHALF:
+	 /* For 8-wide, this is "use the second set of 8 bits." */
+	 p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+	 break;
+      case BRW_COMPRESSION_COMPRESSED:
+	 /* For 16-wide instruction compression, use the first set of 16 bits
+	  * since we don't do 32-wide dispatch.
+	  */
+	 p->current->header.compression_control = GEN6_COMPRESSION_1H;
+	 break;
+      default:
+	 assert(!"not reached");
+	 p->current->header.compression_control = GEN6_COMPRESSION_1H;
+	 break;
+      }
+   } else {
+      p->current->header.compression_control = compression_control;
+   }
 }
 
 void brw_set_mask_control( struct brw_compile *p, GLuint value )
@@ -95,6 +125,7 @@ void brw_push_insn_state( struct brw_compile *p )
 {
    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
    memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
+   p->compressed_stack[p->current - p->stack] = p->compressed;
    p->current++;   
 }
 
@@ -102,6 +133,7 @@ void brw_pop_insn_state( struct brw_compile *p )
 {
    assert(p->current != p->stack);
    p->current--;
+   p->compressed = p->compressed_stack[p->current - p->stack];
 }
 
 
@@ -112,6 +144,7 @@ void brw_init_compile( struct brw_context *brw, struct brw_compile *p )
    p->brw = brw;
    p->nr_insn = 0;
    p->current = p->stack;
+   p->compressed = false;
    memset(p->current, 0, sizeof(p->current[0]));
 
    /* Some defaults?
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index b4538e6e8a..4dbdc52210 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -33,6 +33,7 @@
 #ifndef BRW_EU_H
 #define BRW_EU_H
 
+#include <stdbool.h>
 #include "brw_structs.h"
 #include "brw_defines.h"
 #include "program/prog_instruction.h"
@@ -106,10 +107,12 @@ struct brw_compile {
    /* Allow clients to push/pop instruction state:
     */
    struct brw_instruction stack[BRW_EU_MAX_INSN_STACK];
+   bool compressed_stack[BRW_EU_MAX_INSN_STACK];
    struct brw_instruction *current;
 
    GLuint flag_value;
    GLboolean single_program_flow;
+   bool compressed;
    struct brw_context *brw;
 
    struct brw_glsl_label *first_label;  /**< linked list of labels */
@@ -954,6 +957,8 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
 	       struct brw_instruction *patch_insn);
 
 struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count);
+struct brw_instruction *brw_CONT_gen6(struct brw_compile *p,
+				      struct brw_instruction *do_insn);
 struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count);
 /* Forward jumps:
  */
@@ -1009,6 +1014,7 @@ void brw_math_invert( struct brw_compile *p,
 void brw_set_src1( struct brw_instruction *insn,
                           struct brw_reg reg );
 
+void brw_set_uip_jip(struct brw_compile *p);
 
 /* brw_optimize.c */
 void brw_optimize(struct brw_compile *p);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 9cb941dacf..9c764fe779 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -41,19 +41,20 @@
  * Internal helper for constructing instructions
  */
 
-static void guess_execution_size( struct brw_instruction *insn,
-				  struct brw_reg reg )
+static void guess_execution_size(struct brw_compile *p,
+				 struct brw_instruction *insn,
+				 struct brw_reg reg)
 {
-   if (reg.width == BRW_WIDTH_8 && 
-       insn->header.compression_control == BRW_COMPRESSION_COMPRESSED) 
+   if (reg.width == BRW_WIDTH_8 && p->compressed)
       insn->header.execution_size = BRW_EXECUTE_16;
    else
       insn->header.execution_size = reg.width;	/* note - definitions are compatible */
 }
 
 
-static void brw_set_dest( struct brw_instruction *insn,
-			  struct brw_reg dest )
+static void brw_set_dest(struct brw_compile *p,
+			 struct brw_instruction *insn,
+			 struct brw_reg dest)
 {
    if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE &&
        dest.file != BRW_MESSAGE_REGISTER_FILE)
@@ -100,7 +101,7 @@ static void brw_set_dest( struct brw_instruction *insn,
    /* NEW: Set the execution size based on dest.width and
     * insn->compression_control:
     */
-   guess_execution_size(insn, dest);
+   guess_execution_size(p, insn, dest);
 }
 
 extern int reg_type_size[];
@@ -629,7 +630,7 @@ static struct brw_instruction *brw_alu1( struct brw_compile *p,
 					 struct brw_reg src )
 {
    struct brw_instruction *insn = next_insn(p, opcode);
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src);   
    return insn;
 }
@@ -641,7 +642,7 @@ static struct brw_instruction *brw_alu2(struct brw_compile *p,
 					struct brw_reg src1 )
 {
    struct brw_instruction *insn = next_insn(p, opcode);   
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, src1);
    return insn;
@@ -680,7 +681,7 @@ void brw_##OP(struct brw_compile *p,					      \
 {									      \
    struct brw_instruction *rnd, *add;					      \
    rnd = next_insn(p, BRW_OPCODE_##OP);					      \
-   brw_set_dest(rnd, dest);						      \
+   brw_set_dest(p, rnd, dest);						      \
    brw_set_src0(rnd, src);						      \
    rnd->header.destreg__conditionalmod = 0x7; /* turn on round-increments */  \
 									      \
@@ -779,7 +780,7 @@ struct brw_instruction *brw_MUL(struct brw_compile *p,
 void brw_NOP(struct brw_compile *p)
 {
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);   
-   brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+   brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
    brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
    brw_set_src1(insn, brw_imm_ud(0x0));
 }
@@ -840,11 +841,11 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size)
    /* Override the defaults for this instruction:
     */
    if (intel->gen < 6) {
-      brw_set_dest(insn, brw_ip_reg());
+      brw_set_dest(p, insn, brw_ip_reg());
       brw_set_src0(insn, brw_ip_reg());
       brw_set_src1(insn, brw_imm_d(0x0));
    } else {
-      brw_set_dest(insn, brw_imm_w(0));
+      brw_set_dest(p, insn, brw_imm_w(0));
       insn->bits1.branch_gen6.jump_count = 0;
       brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -870,7 +871,7 @@ brw_IF_gen6(struct brw_compile *p, uint32_t conditional,
 
    insn = next_insn(p, BRW_OPCODE_IF);
 
-   brw_set_dest(insn, brw_imm_w(0));
+   brw_set_dest(p, insn, brw_imm_w(0));
    insn->header.execution_size = BRW_EXECUTE_8;
    insn->bits1.branch_gen6.jump_count = 0;
    brw_set_src0(insn, src0);
@@ -905,11 +906,11 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p,
    }
 
    if (intel->gen < 6) {
-      brw_set_dest(insn, brw_ip_reg());
+      brw_set_dest(p, insn, brw_ip_reg());
       brw_set_src0(insn, brw_ip_reg());
       brw_set_src1(insn, brw_imm_d(0x0));
    } else {
-      brw_set_dest(insn, brw_imm_w(0));
+      brw_set_dest(p, insn, brw_imm_w(0));
       insn->bits1.branch_gen6.jump_count = 0;
       brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -965,11 +966,11 @@ void brw_ENDIF(struct brw_compile *p,
       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_ENDIF);
 
       if (intel->gen < 6) {
-	 brw_set_dest(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
+	 brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
 	 brw_set_src0(insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
 	 brw_set_src1(insn, brw_imm_d(0x0));
       } else {
-	 brw_set_dest(insn, brw_imm_w(0));
+	 brw_set_dest(p, insn, brw_imm_w(0));
 	 brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 	 brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
       }
@@ -1029,16 +1030,44 @@ void brw_ENDIF(struct brw_compile *p,
 
 struct brw_instruction *brw_BREAK(struct brw_compile *p, int pop_count)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_instruction *insn;
+
    insn = next_insn(p, BRW_OPCODE_BREAK);
-   brw_set_dest(insn, brw_ip_reg());
+   if (intel->gen >= 6) {
+      brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+      brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+      brw_set_src1(insn, brw_imm_d(0x0));
+   } else {
+      brw_set_dest(p, insn, brw_ip_reg());
+      brw_set_src0(insn, brw_ip_reg());
+      brw_set_src1(insn, brw_imm_d(0x0));
+      insn->bits3.if_else.pad0 = 0;
+      insn->bits3.if_else.pop_count = pop_count;
+   }
+   insn->header.compression_control = BRW_COMPRESSION_NONE;
+   insn->header.execution_size = BRW_EXECUTE_8;
+
+   return insn;
+}
+
+struct brw_instruction *brw_CONT_gen6(struct brw_compile *p,
+				      struct brw_instruction *do_insn)
+{
+   struct brw_instruction *insn;
+   int br = 2;
+
+   insn = next_insn(p, BRW_OPCODE_CONTINUE);
+   brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+   brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+   brw_set_dest(p, insn, brw_ip_reg());
    brw_set_src0(insn, brw_ip_reg());
    brw_set_src1(insn, brw_imm_d(0x0));
+
+   insn->bits3.break_cont.uip = br * (do_insn - insn);
+
    insn->header.compression_control = BRW_COMPRESSION_NONE;
    insn->header.execution_size = BRW_EXECUTE_8;
-   /* insn->header.mask_control = BRW_MASK_DISABLE; */
-   insn->bits3.if_else.pad0 = 0;
-   insn->bits3.if_else.pop_count = pop_count;
    return insn;
 }
 
@@ -1046,7 +1075,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count)
 {
    struct brw_instruction *insn;
    insn = next_insn(p, BRW_OPCODE_CONTINUE);
-   brw_set_dest(insn, brw_ip_reg());
+   brw_set_dest(p, insn, brw_ip_reg());
    brw_set_src0(insn, brw_ip_reg());
    brw_set_src1(insn, brw_imm_d(0x0));
    insn->header.compression_control = BRW_COMPRESSION_NONE;
@@ -1058,17 +1087,33 @@ struct brw_instruction *brw_CONT(struct brw_compile *p, int pop_count)
 }
 
 /* DO/WHILE loop:
+ *
+ * The DO/WHILE is just an unterminated loop -- break or continue are
+ * used for control within the loop.  We have a few ways they can be
+ * done.
+ *
+ * For uniform control flow, the WHILE is just a jump, so ADD ip, ip,
+ * jip and no DO instruction.
+ *
+ * For non-uniform control flow pre-gen6, there's a DO instruction to
+ * push the mask, and a WHILE to jump back, and BREAK to get out and
+ * pop the mask.
+ *
+ * For gen6, there's no more mask stack, so no need for DO.  WHILE
+ * just points back to the first instruction of the loop.
  */
 struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
 {
-   if (p->single_program_flow) {
+   struct intel_context *intel = &p->brw->intel;
+
+   if (intel->gen >= 6 || p->single_program_flow) {
       return &p->store[p->nr_insn];
    } else {
       struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO);
 
       /* Override the defaults for this instruction:
        */
-      brw_set_dest(insn, brw_null_reg());
+      brw_set_dest(p, insn, brw_null_reg());
       brw_set_src0(insn, brw_null_reg());
       brw_set_src1(insn, brw_null_reg());
 
@@ -1094,34 +1139,42 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p,
    if (intel->gen >= 5)
       br = 2;
 
-   if (p->single_program_flow)
-      insn = next_insn(p, BRW_OPCODE_ADD);
-   else
+   if (intel->gen >= 6) {
       insn = next_insn(p, BRW_OPCODE_WHILE);
 
-   brw_set_dest(insn, brw_ip_reg());
-   brw_set_src0(insn, brw_ip_reg());
-   brw_set_src1(insn, brw_imm_d(0x0));
+      brw_set_dest(p, insn, brw_imm_w(0));
+      insn->bits1.branch_gen6.jump_count = br * (do_insn - insn);
+      brw_set_src0(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+      brw_set_src1(insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 
-   insn->header.compression_control = BRW_COMPRESSION_NONE;
+      insn->header.execution_size = do_insn->header.execution_size;
+      assert(insn->header.execution_size == BRW_EXECUTE_8);
+   } else {
+      if (p->single_program_flow) {
+	 insn = next_insn(p, BRW_OPCODE_ADD);
 
-   if (p->single_program_flow) {
-      insn->header.execution_size = BRW_EXECUTE_1;
+	 brw_set_dest(p, insn, brw_ip_reg());
+	 brw_set_src0(insn, brw_ip_reg());
+	 brw_set_src1(insn, brw_imm_d((do_insn - insn) * 16));
+	 insn->header.execution_size = BRW_EXECUTE_1;
+      } else {
+	 insn = next_insn(p, BRW_OPCODE_WHILE);
 
-      insn->bits3.d = (do_insn - insn) * 16;
-   } else {
-      insn->header.execution_size = do_insn->header.execution_size;
+	 assert(do_insn->header.opcode == BRW_OPCODE_DO);
 
-      assert(do_insn->header.opcode == BRW_OPCODE_DO);
-      insn->bits3.if_else.jump_count = br * (do_insn - insn + 1);
-      insn->bits3.if_else.pop_count = 0;
-      insn->bits3.if_else.pad0 = 0;
-   }
+	 brw_set_dest(p, insn, brw_ip_reg());
+	 brw_set_src0(insn, brw_ip_reg());
+	 brw_set_src1(insn, brw_imm_d(0));
 
-/*    insn->header.mask_control = BRW_MASK_ENABLE; */
+	 insn->header.execution_size = do_insn->header.execution_size;
+	 insn->bits3.if_else.jump_count = br * (do_insn - insn + 1);
+	 insn->bits3.if_else.pop_count = 0;
+	 insn->bits3.if_else.pad0 = 0;
+      }
+   }
+   insn->header.compression_control = BRW_COMPRESSION_NONE;
+   p->current->header.predicate_control = BRW_PREDICATE_NONE;
 
-   /* insn->header.mask_control = BRW_MASK_DISABLE; */
-   p->current->header.predicate_control = BRW_PREDICATE_NONE;   
    return insn;
 }
 
@@ -1159,7 +1212,7 @@ void brw_CMP(struct brw_compile *p,
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
 
    insn->header.destreg__conditionalmod = conditional;
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, src1);
 
@@ -1184,7 +1237,7 @@ void brw_WAIT (struct brw_compile *p)
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT);
    struct brw_reg src = brw_notification_1_reg();
 
-   brw_set_dest(insn, src);
+   brw_set_dest(p, insn, src);
    brw_set_src0(insn, src);
    brw_set_src1(insn, brw_null_reg());
    insn->header.execution_size = 0; /* must */
@@ -1219,6 +1272,10 @@ void brw_math( struct brw_compile *p,
       assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
       assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
 
+      /* Source modifiers are ignored for extended math instructions. */
+      assert(!src.negate);
+      assert(!src.abs);
+
       if (function != BRW_MATH_FUNCTION_INT_DIV_QUOTIENT &&
 	  function != BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
 	 assert(src.type == BRW_REGISTER_TYPE_F);
@@ -1228,8 +1285,9 @@ void brw_math( struct brw_compile *p,
        * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
        */
       insn->header.destreg__conditionalmod = function;
+      insn->header.saturate = saturate;
 
-      brw_set_dest(insn, dest);
+      brw_set_dest(p, insn, dest);
       brw_set_src0(insn, src);
       brw_set_src1(insn, brw_null_reg());
    } else {
@@ -1242,7 +1300,7 @@ void brw_math( struct brw_compile *p,
       insn->header.predicate_control = 0;
       insn->header.destreg__conditionalmod = msg_reg_nr;
 
-      brw_set_dest(insn, dest);
+      brw_set_dest(p, insn, dest);
       brw_set_src0(insn, src);
       brw_set_math_message(p->brw,
 			   insn,
@@ -1284,12 +1342,18 @@ void brw_math2(struct brw_compile *p,
       assert(src1.type == BRW_REGISTER_TYPE_F);
    }
 
+   /* Source modifiers are ignored for extended math instructions. */
+   assert(!src0.negate);
+   assert(!src0.abs);
+   assert(!src1.negate);
+   assert(!src1.abs);
+
    /* Math is the same ISA format as other opcodes, except that CondModifier
     * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
     */
    insn->header.destreg__conditionalmod = function;
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, src1);
 }
@@ -1318,8 +1382,13 @@ void brw_math_16( struct brw_compile *p,
        * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
        */
       insn->header.destreg__conditionalmod = function;
+      insn->header.saturate = saturate;
+
+      /* Source modifiers are ignored for extended math instructions. */
+      assert(!src.negate);
+      assert(!src.abs);
 
-      brw_set_dest(insn, dest);
+      brw_set_dest(p, insn, dest);
       brw_set_src0(insn, src);
       brw_set_src1(insn, brw_null_reg());
       return;
@@ -1334,7 +1403,7 @@ void brw_math_16( struct brw_compile *p,
    insn = next_insn(p, BRW_OPCODE_SEND);
    insn->header.destreg__conditionalmod = msg_reg_nr;
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src);
    brw_set_math_message(p->brw,
 			insn, 
@@ -1351,7 +1420,7 @@ void brw_math_16( struct brw_compile *p,
    insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
    insn->header.destreg__conditionalmod = msg_reg_nr+1;
 
-   brw_set_dest(insn, offset(dest,1));
+   brw_set_dest(p, insn, offset(dest,1));
    brw_set_src0(insn, src);
    brw_set_math_message(p->brw, 
 			insn, 
@@ -1446,7 +1515,7 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
 	 send_commit_msg = 1;
       }
 
-      brw_set_dest(insn, dest);
+      brw_set_dest(p, insn, dest);
       brw_set_src0(insn, brw_null_reg());
 
       brw_set_dp_write_message(p->brw,
@@ -1516,7 +1585,7 @@ brw_oword_block_read_scratch(struct brw_compile *p,
       insn->header.compression_control = BRW_COMPRESSION_NONE;
       insn->header.destreg__conditionalmod = mrf.nr;
 
-      brw_set_dest(insn, dest);	/* UW? */
+      brw_set_dest(p, insn, dest);	/* UW? */
       brw_set_src0(insn, brw_null_reg());
 
       brw_set_dp_read_message(p->brw,
@@ -1569,7 +1638,7 @@ void brw_oword_block_read(struct brw_compile *p,
    /* cast dest to a uword[8] vector */
    dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    if (intel->gen >= 6) {
       brw_set_src0(insn, mrf);
    } else {
@@ -1614,7 +1683,7 @@ void brw_dword_scattered_read(struct brw_compile *p,
    /* cast dest to a uword[8] vector */
    dest = retype(vec8(dest), BRW_REGISTER_TYPE_UW);
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, brw_null_reg());
 
    brw_set_dp_read_message(p->brw,
@@ -1639,29 +1708,21 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
                       GLuint location,
                       GLuint bind_table_index)
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_instruction *insn;
    GLuint msg_reg_nr = 1;
-   struct brw_reg b;
 
-   /*
-   printf("vs const read msg, location %u, msg_reg_nr %d\n",
-          location, msg_reg_nr);
-   */
+   if (intel->gen >= 6)
+      location /= 16;
 
    /* Setup MRF[1] with location/offset into const buffer */
    brw_push_insn_state(p);
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
    brw_set_mask_control(p, BRW_MASK_DISABLE);
    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-
-   /* XXX I think we're setting all the dwords of MRF[1] to 'location'.
-    * when the docs say only dword[2] should be set.  Hmmm.  But it works.
-    */
-   b = brw_message_reg(msg_reg_nr);
-   b = retype(b, BRW_REGISTER_TYPE_UD);
-   /*b = get_element_ud(b, 2);*/
-   brw_MOV(p, b, brw_imm_ud(location));
-
+   brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 2),
+		     BRW_REGISTER_TYPE_UD),
+	   brw_imm_ud(location));
    brw_pop_insn_state(p);
 
    insn = next_insn(p, BRW_OPCODE_SEND);
@@ -1671,8 +1732,12 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
    insn->header.destreg__conditionalmod = msg_reg_nr;
    insn->header.mask_control = BRW_MASK_DISABLE;
 
-   brw_set_dest(insn, dest);
-   brw_set_src0(insn, brw_null_reg());
+   brw_set_dest(p, insn, dest);
+   if (intel->gen >= 6) {
+      brw_set_src0(insn, brw_message_reg(msg_reg_nr));
+   } else {
+      brw_set_src0(insn, brw_null_reg());
+   }
 
    brw_set_dp_read_message(p->brw,
 			   insn,
@@ -1706,7 +1771,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
    /* M1.0 is block offset 0, M1.4 is block offset 1, all other
     * fields ignored.
     */
-   brw_ADD(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD),
+   brw_ADD(p, retype(brw_message_reg(1), BRW_REGISTER_TYPE_D),
 	   addr_reg, brw_imm_d(offset));
    brw_pop_insn_state(p);
 
@@ -1717,7 +1782,7 @@ void brw_dp_READ_4_vs_relative(struct brw_compile *p,
    insn->header.destreg__conditionalmod = 0;
    insn->header.mask_control = BRW_MASK_DISABLE;
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, brw_vec8_grf(0, 0));
 
    if (intel->gen == 6)
@@ -1782,7 +1847,7 @@ void brw_fb_WRITE(struct brw_compile *p,
    else
       msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_dp_write_message(p->brw,
 			    insn,
@@ -1860,7 +1925,7 @@ void brw_SAMPLE(struct brw_compile *p,
 
 	 struct brw_reg m1 = brw_message_reg(msg_reg_nr);
 
-	 guess_execution_size(p->current, dest);
+	 guess_execution_size(p, p->current, dest);
 	 if (p->current->header.execution_size == BRW_EXECUTE_16)
 	    dispatch_16 = GL_TRUE;
 
@@ -1895,12 +1960,15 @@ void brw_SAMPLE(struct brw_compile *p,
        * and the first message register index comes from src0.
        */
       if (intel->gen >= 6) {
-	  brw_push_insn_state(p);
-	  brw_set_mask_control( p, BRW_MASK_DISABLE );
-	  /* m1 contains header? */
-	  brw_MOV(p, brw_message_reg(msg_reg_nr), src0);
-	  brw_pop_insn_state(p);
-	  src0 = brw_message_reg(msg_reg_nr);
+	 if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
+	     src0.nr != BRW_ARF_NULL) {
+	    brw_push_insn_state(p);
+	    brw_set_mask_control( p, BRW_MASK_DISABLE );
+	    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
+	    brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0);
+	    brw_pop_insn_state(p);
+	 }
+	 src0 = brw_message_reg(msg_reg_nr);
       }
 
       insn = next_insn(p, BRW_OPCODE_SEND);
@@ -1909,7 +1977,7 @@ void brw_SAMPLE(struct brw_compile *p,
       if (intel->gen < 6)
 	  insn->header.destreg__conditionalmod = msg_reg_nr;
 
-      brw_set_dest(insn, dest);
+      brw_set_dest(p, insn, dest);
       brw_set_src0(insn, src0);
       brw_set_sampler_message(p->brw, insn,
 			      binding_table_index,
@@ -1970,7 +2038,7 @@ void brw_urb_WRITE(struct brw_compile *p,
 
    assert(msg_length < BRW_MAX_MRF);
 
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, brw_imm_d(0));
 
@@ -1989,6 +2057,80 @@ void brw_urb_WRITE(struct brw_compile *p,
 		       swizzle);
 }
 
+static int
+brw_find_next_block_end(struct brw_compile *p, int start)
+{
+   int ip;
+
+   for (ip = start + 1; ip < p->nr_insn; ip++) {
+      struct brw_instruction *insn = &p->store[ip];
+
+      switch (insn->header.opcode) {
+      case BRW_OPCODE_ENDIF:
+      case BRW_OPCODE_ELSE:
+      case BRW_OPCODE_WHILE:
+	 return ip;
+      }
+   }
+   assert(!"not reached");
+   return start + 1;
+}
+
+/* There is no DO instruction on gen6, so to find the end of the loop
+ * we have to see if the loop is jumping back before our start
+ * instruction.
+ */
+static int
+brw_find_loop_end(struct brw_compile *p, int start)
+{
+   int ip;
+   int br = 2;
+
+   for (ip = start + 1; ip < p->nr_insn; ip++) {
+      struct brw_instruction *insn = &p->store[ip];
+
+      if (insn->header.opcode == BRW_OPCODE_WHILE) {
+	 if (ip + insn->bits1.branch_gen6.jump_count / br < start)
+	    return ip;
+      }
+   }
+   assert(!"not reached");
+   return start + 1;
+}
+
+/* After program generation, go back and update the UIP and JIP of
+ * BREAK and CONT instructions to their correct locations.
+ */
+void
+brw_set_uip_jip(struct brw_compile *p)
+{
+   struct intel_context *intel = &p->brw->intel;
+   int ip;
+   int br = 2;
+
+   if (intel->gen < 6)
+      return;
+
+   for (ip = 0; ip < p->nr_insn; ip++) {
+      struct brw_instruction *insn = &p->store[ip];
+
+      switch (insn->header.opcode) {
+      case BRW_OPCODE_BREAK:
+	 insn->bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip) - ip);
+	 insn->bits3.break_cont.uip = br * (brw_find_loop_end(p, ip) - ip + 1);
+	 break;
+      case BRW_OPCODE_CONTINUE:
+	 /* JIP is set at CONTINUE emit time, since that's when we
+	  * know where the start of the loop is.
+	  */
+	 insn->bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip) - ip);
+	 assert(insn->bits3.break_cont.uip != 0);
+	 assert(insn->bits3.break_cont.jip != 0);
+	 break;
+      }
+   }
+}
+
 void brw_ff_sync(struct brw_compile *p,
 		   struct brw_reg dest,
 		   GLuint msg_reg_nr,
@@ -2013,7 +2155,7 @@ void brw_ff_sync(struct brw_compile *p,
    }
 
    insn = next_insn(p, BRW_OPCODE_SEND);
-   brw_set_dest(insn, dest);
+   brw_set_dest(p, insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, brw_imm_d(0));
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 283d5aad49..4eead32cbb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -101,10 +101,12 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
       clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
 
       do_mat_op_to_vec(shader->ir);
-      do_mod_to_fract(shader->ir);
-      do_div_to_mul_rcp(shader->ir);
-      do_sub_to_add_neg(shader->ir);
-      do_explog_to_explog2(shader->ir);
+      lower_instructions(shader->ir,
+			 MOD_TO_FRACT |
+			 DIV_TO_MUL_RCP |
+			 SUB_TO_ADD_NEG |
+			 EXP_TO_EXP2 |
+			 LOG_TO_LOG2);
       do_lower_texture_projection(shader->ir);
       brw_do_cubemap_normalize(shader->ir);
 
@@ -130,6 +132,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
 						GL_TRUE, /* temp */
 						GL_TRUE /* uniform */
 						) || progress;
+	 progress = lower_quadop_vector(shader->ir, false) || progress;
       } while (progress);
 
       validate_ir_tree(shader->ir);
@@ -174,6 +177,46 @@ type_size(const struct glsl_type *type)
    }
 }
 
+/**
+ * Returns how many MRFs an FS opcode will write over.
+ *
+ * Note that this is not the 0 or 1 implied writes in an actual gen
+ * instruction -- the FS opcodes often generate MOVs in addition.
+ */
+int
+fs_visitor::implied_mrf_writes(fs_inst *inst)
+{
+   if (inst->mlen == 0)
+      return 0;
+
+   switch (inst->opcode) {
+   case FS_OPCODE_RCP:
+   case FS_OPCODE_RSQ:
+   case FS_OPCODE_SQRT:
+   case FS_OPCODE_EXP2:
+   case FS_OPCODE_LOG2:
+   case FS_OPCODE_SIN:
+   case FS_OPCODE_COS:
+      return 1;
+   case FS_OPCODE_POW:
+      return 2;
+   case FS_OPCODE_TEX:
+   case FS_OPCODE_TXB:
+   case FS_OPCODE_TXL:
+      return 1;
+   case FS_OPCODE_FB_WRITE:
+      return 2;
+   case FS_OPCODE_PULL_CONSTANT_LOAD:
+   case FS_OPCODE_UNSPILL:
+      return 1;
+   case FS_OPCODE_SPILL:
+      return 2;
+   default:
+      assert(!"not reached");
+      return inst->mlen;
+   }
+}
+
 int
 fs_visitor::virtual_grf_alloc(int size)
 {
@@ -299,6 +342,10 @@ fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
 	 case GLSL_TYPE_BOOL:
 	    c->prog_data.param_convert[param] = PARAM_CONVERT_F2B;
 	    break;
+	 default:
+	    assert(!"not reached");
+	    c->prog_data.param_convert[param] = PARAM_NO_CONVERT;
+	    break;
 	 }
 
 	 c->prog_data.param[param] = &vec_values[i];
@@ -400,6 +447,7 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
    fs_reg wpos = *reg;
    fs_reg neg_y = this->pixel_y;
    neg_y.negate = true;
+   bool flip = !ir->origin_upper_left ^ c->key.render_to_fbo;
 
    /* gl_FragCoord.x */
    if (ir->pixel_center_integer) {
@@ -410,13 +458,13 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
    wpos.reg_offset++;
 
    /* gl_FragCoord.y */
-   if (ir->origin_upper_left && ir->pixel_center_integer) {
+   if (!flip && ir->pixel_center_integer) {
       emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
    } else {
       fs_reg pixel_y = this->pixel_y;
       float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
 
-      if (!ir->origin_upper_left) {
+      if (flip) {
 	 pixel_y.negate = true;
 	 offset += c->key.drawable_height - 1.0;
       }
@@ -426,8 +474,13 @@ fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
    wpos.reg_offset++;
 
    /* gl_FragCoord.z */
-   emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
-		interp_reg(FRAG_ATTRIB_WPOS, 2)));
+   if (intel->gen >= 6) {
+      emit(fs_inst(BRW_OPCODE_MOV, wpos,
+		   fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
+   } else {
+      emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
+		   interp_reg(FRAG_ATTRIB_WPOS, 2)));
+   }
    wpos.reg_offset++;
 
    /* gl_FragCoord.w: Already set up in emit_interpolation */
@@ -552,8 +605,13 @@ fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
     * might be able to do better by doing execsize = 1 math and then
     * expanding that result out, but we would need to be careful with
     * masking.
+    *
+    * The hardware ignores source modifiers (negate and abs) on math
+    * instructions, so we also move to a temp to set those up.
     */
-   if (intel->gen >= 6 && src.file == UNIFORM) {
+   if (intel->gen >= 6 && (src.file == UNIFORM ||
+			   src.abs ||
+			   src.negate)) {
       fs_reg expanded = fs_reg(this, glsl_type::float_type);
       emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
       src = expanded;
@@ -696,6 +754,27 @@ fs_visitor::visit(ir_dereference_array *ir)
    }
 }
 
+/* Instruction selection: Produce a MOV.sat instead of
+ * MIN(MAX(val, 0), 1) when possible.
+ */
+bool
+fs_visitor::try_emit_saturate(ir_expression *ir)
+{
+   ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
+
+   if (!sat_val)
+      return false;
+
+   sat_val->accept(this);
+   fs_reg src = this->result;
+
+   this->result = fs_reg(this, ir->type);
+   fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, src));
+   inst->saturate = true;
+
+   return true;
+}
+
 void
 fs_visitor::visit(ir_expression *ir)
 {
@@ -703,6 +782,11 @@ fs_visitor::visit(ir_expression *ir)
    fs_reg op[2], temp;
    fs_inst *inst;
 
+   assert(ir->get_num_operands() <= 2);
+
+   if (try_emit_saturate(ir))
+      return;
+
    for (operand = 0; operand < ir->get_num_operands(); operand++) {
       ir->operands[operand]->accept(this);
       if (this->result.file == BAD_FILE) {
@@ -773,9 +857,11 @@ fs_visitor::visit(ir_expression *ir)
       assert(!"not reached: should be handled by ir_explog_to_explog2");
       break;
    case ir_unop_sin:
+   case ir_unop_sin_reduced:
       emit_math(FS_OPCODE_SIN, this->result, op[0]);
       break;
    case ir_unop_cos:
+   case ir_unop_cos_reduced:
       emit_math(FS_OPCODE_COS, this->result, op[0]);
       break;
 
@@ -849,7 +935,6 @@ fs_visitor::visit(ir_expression *ir)
       break;
 
    case ir_binop_dot:
-   case ir_binop_cross:
    case ir_unop_any:
       assert(!"not reached: should be handled by brw_fs_channel_expressions");
       break;
@@ -858,6 +943,10 @@ fs_visitor::visit(ir_expression *ir)
       assert(!"not reached: should be handled by lower_noise");
       break;
 
+   case ir_quadop_vector:
+      assert(!"not reached: should be handled by lower_quadop_vector");
+      break;
+
    case ir_unop_sqrt:
       emit_math(FS_OPCODE_SQRT, this->result, op[0]);
       break;
@@ -1348,28 +1437,70 @@ fs_visitor::visit(ir_discard *ir)
 void
 fs_visitor::visit(ir_constant *ir)
 {
-   fs_reg reg(this, ir->type);
-   this->result = reg;
+   /* Set this->result to reg at the bottom of the function because some code
+    * paths will cause this visitor to be applied to other fields.  This will
+    * cause the value stored in this->result to be modified.
+    *
+    * Make reg constant so that it doesn't get accidentally modified along the
+    * way.  Yes, I actually had this problem. :(
+    */
+   const fs_reg reg(this, ir->type);
+   fs_reg dst_reg = reg;
 
-   for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
-      switch (ir->type->base_type) {
-      case GLSL_TYPE_FLOAT:
-	 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
-	 break;
-      case GLSL_TYPE_UINT:
-	 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
-	 break;
-      case GLSL_TYPE_INT:
-	 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
-	 break;
-      case GLSL_TYPE_BOOL:
-	 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
-	 break;
-      default:
-	 assert(!"Non-float/uint/int/bool constant");
+   if (ir->type->is_array()) {
+      const unsigned size = type_size(ir->type->fields.array);
+
+      for (unsigned i = 0; i < ir->type->length; i++) {
+	 ir->array_elements[i]->accept(this);
+	 fs_reg src_reg = this->result;
+
+	 dst_reg.type = src_reg.type;
+	 for (unsigned j = 0; j < size; j++) {
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, src_reg));
+	    src_reg.reg_offset++;
+	    dst_reg.reg_offset++;
+	 }
+      }
+   } else if (ir->type->is_record()) {
+      foreach_list(node, &ir->components) {
+	 ir_instruction *const field = (ir_instruction *) node;
+	 const unsigned size = type_size(field->type);
+
+	 field->accept(this);
+	 fs_reg src_reg = this->result;
+
+	 dst_reg.type = src_reg.type;
+	 for (unsigned j = 0; j < size; j++) {
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, src_reg));
+	    src_reg.reg_offset++;
+	    dst_reg.reg_offset++;
+	 }
+      }
+   } else {
+      const unsigned size = type_size(ir->type);
+
+      for (unsigned i = 0; i < size; i++) {
+	 switch (ir->type->base_type) {
+	 case GLSL_TYPE_FLOAT:
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.f[i])));
+	    break;
+	 case GLSL_TYPE_UINT:
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.u[i])));
+	    break;
+	 case GLSL_TYPE_INT:
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg(ir->value.i[i])));
+	    break;
+	 case GLSL_TYPE_BOOL:
+	    emit(fs_inst(BRW_OPCODE_MOV, dst_reg, fs_reg((int)ir->value.b[i])));
+	    break;
+	 default:
+	    assert(!"Non-float/uint/int/bool constant");
+	 }
+	 dst_reg.reg_offset++;
       }
-      reg.reg_offset++;
    }
+
+   this->result = reg;
 }
 
 void
@@ -1381,6 +1512,7 @@ fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
       fs_reg op[2];
       fs_inst *inst;
 
+      assert(expr->get_num_operands() <= 2);
       for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
 	 assert(expr->operands[i]->type->is_scalar());
 
@@ -1488,6 +1620,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
       fs_inst *inst;
       fs_reg temp;
 
+      assert(expr->get_num_operands() <= 2);
       for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
 	 assert(expr->operands[i]->type->is_scalar());
 
@@ -1497,7 +1630,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
 
       switch (expr->operation) {
       case ir_unop_logic_not:
-	 inst = emit(fs_inst(BRW_OPCODE_IF, temp, op[0], fs_reg(1)));
+	 inst = emit(fs_inst(BRW_OPCODE_IF, temp, op[0], fs_reg(0)));
 	 inst->conditional_mod = BRW_CONDITIONAL_Z;
 	 return;
 
@@ -1874,7 +2007,7 @@ fs_visitor::emit_interpolation_setup_gen6()
    emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
 
    this->current_annotation = "compute 1/pos.w";
-   this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
+   this->wpos_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
    this->pixel_w = fs_reg(this, glsl_type::float_type);
    emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
 
@@ -1902,17 +2035,17 @@ fs_visitor::emit_fb_writes()
       nr += 2;
    }
 
-   if (c->key.aa_dest_stencil_reg) {
+   if (c->aa_dest_stencil_reg) {
       emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
-		   fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
+		   fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
    }
 
    /* Reserve space for color. It'll be filled in per MRT below. */
    int color_mrf = nr;
    nr += 4;
 
-   if (c->key.source_depth_to_render_target) {
-      if (c->key.computes_depth) {
+   if (c->source_depth_to_render_target) {
+      if (c->computes_depth) {
 	 /* Hand over gl_FragDepth. */
 	 assert(this->frag_depth);
 	 fs_reg depth = *(variable_storage(this->frag_depth));
@@ -1921,20 +2054,22 @@ fs_visitor::emit_fb_writes()
       } else {
 	 /* Pass through the payload depth. */
 	 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
-		      fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
+		      fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
       }
    }
 
-   if (c->key.dest_depth_reg) {
+   if (c->dest_depth_reg) {
       emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
-		   fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
+		   fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
    }
 
    fs_reg color = reg_undef;
    if (this->frag_color)
       color = *(variable_storage(this->frag_color));
-   else if (this->frag_data)
+   else if (this->frag_data) {
       color = *(variable_storage(this->frag_data));
+      color.type = BRW_REGISTER_TYPE_F;
+   }
 
    for (int target = 0; target < c->key.nr_color_regions; target++) {
       this->current_annotation = talloc_asprintf(this->mem_ctx,
@@ -2375,7 +2510,7 @@ fs_visitor::generate_pull_constant_load(fs_inst *inst, struct brw_reg dst)
 void
 fs_visitor::assign_curb_setup()
 {
-   c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
+   c->prog_data.first_curbe_grf = c->nr_payload_regs;
    c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
 
    /* Map the offsets in the UNIFORM file to fixed HW regs. */
@@ -2515,6 +2650,7 @@ fs_visitor::split_virtual_grfs()
 	 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
 	    int reg = virtual_grf_alloc(1);
 	    assert(reg == new_virtual_grf[i] + j - 1);
+	    (void) reg;
 	 }
 	 this->virtual_grf_sizes[i] = 1;
       }
@@ -2768,6 +2904,7 @@ fs_visitor::propagate_constants()
 	       }
 	       break;
 	    case BRW_OPCODE_CMP:
+	    case BRW_OPCODE_SEL:
 	       if (i == 1) {
 		  scan_inst->src[i] = inst->src[0];
 		  progress = true;
@@ -2796,26 +2933,17 @@ bool
 fs_visitor::dead_code_eliminate()
 {
    bool progress = false;
-   int num_vars = this->virtual_grf_next;
-   bool dead[num_vars];
-
-   for (int i = 0; i < num_vars; i++) {
-      dead[i] = this->virtual_grf_def[i] >= this->virtual_grf_use[i];
-
-      if (dead[i]) {
-	 /* Mark off its interval so it won't interfere with anything. */
-	 this->virtual_grf_def[i] = -1;
-	 this->virtual_grf_use[i] = -1;
-      }
-   }
+   int pc = 0;
 
    foreach_iter(exec_list_iterator, iter, this->instructions) {
       fs_inst *inst = (fs_inst *)iter.get();
 
-      if (inst->dst.file == GRF && dead[inst->dst.reg]) {
+      if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
 	 inst->remove();
 	 progress = true;
       }
+
+      pc++;
    }
 
    return progress;
@@ -2933,11 +3061,60 @@ fs_visitor::compute_to_mrf()
       /* Found a move of a GRF to a MRF.  Let's see if we can go
        * rewrite the thing that made this GRF to write into the MRF.
        */
-      bool found = false;
       fs_inst *scan_inst;
       for (scan_inst = (fs_inst *)inst->prev;
 	   scan_inst->prev != NULL;
 	   scan_inst = (fs_inst *)scan_inst->prev) {
+	 if (scan_inst->dst.file == GRF &&
+	     scan_inst->dst.reg == inst->src[0].reg) {
+	    /* Found the last thing to write our reg we want to turn
+	     * into a compute-to-MRF.
+	     */
+
+	    if (scan_inst->opcode == FS_OPCODE_TEX) {
+	       /* texturing writes several continuous regs, so we can't
+		* compute-to-mrf that.
+		*/
+	       break;
+	    }
+
+	    /* If it's predicated, it (probably) didn't populate all
+	     * the channels.
+	     */
+	    if (scan_inst->predicated)
+	       break;
+
+	    /* SEND instructions can't have MRF as a destination. */
+	    if (scan_inst->mlen)
+	       break;
+
+	    if (intel->gen >= 6) {
+	       /* gen6 math instructions must have the destination be
+		* GRF, so no compute-to-MRF for them.
+		*/
+	       if (scan_inst->opcode == FS_OPCODE_RCP ||
+		   scan_inst->opcode == FS_OPCODE_RSQ ||
+		   scan_inst->opcode == FS_OPCODE_SQRT ||
+		   scan_inst->opcode == FS_OPCODE_EXP2 ||
+		   scan_inst->opcode == FS_OPCODE_LOG2 ||
+		   scan_inst->opcode == FS_OPCODE_SIN ||
+		   scan_inst->opcode == FS_OPCODE_COS ||
+		   scan_inst->opcode == FS_OPCODE_POW) {
+		  break;
+	       }
+	    }
+
+	    if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
+	       /* Found the creator of our MRF's source value. */
+	       scan_inst->dst.file = MRF;
+	       scan_inst->dst.hw_reg = inst->dst.hw_reg;
+	       scan_inst->saturate |= inst->saturate;
+	       inst->remove();
+	       progress = true;
+	    }
+	    break;
+	 }
+
 	 /* We don't handle flow control here.  Most computation of
 	  * values that end up in MRFs are shortly before the MRF
 	  * write anyway.
@@ -2971,71 +3148,88 @@ fs_visitor::compute_to_mrf()
 	 }
 
 	 if (scan_inst->mlen > 0) {
-	    /* Found a SEND instruction, which will do some amount of
-	     * implied write that may overwrite our MRF that we were
-	     * hoping to compute-to-MRF somewhere above it.  Nothing
-	     * we have implied-writes more than 2 MRFs from base_mrf,
-	     * though.
+	    /* Found a SEND instruction, which means that there are
+	     * live values in MRFs from base_mrf to base_mrf +
+	     * scan_inst->mlen - 1.  Don't go pushing our MRF write up
+	     * above it.
 	     */
-	    int implied_write_len = MIN2(scan_inst->mlen, 2);
 	    if (inst->dst.hw_reg >= scan_inst->base_mrf &&
-		inst->dst.hw_reg < scan_inst->base_mrf + implied_write_len) {
+		inst->dst.hw_reg < scan_inst->base_mrf + scan_inst->mlen) {
 	       break;
 	    }
 	 }
+      }
+   }
 
-	 if (scan_inst->dst.file == GRF &&
-	     scan_inst->dst.reg == inst->src[0].reg) {
-	    /* Found the last thing to write our reg we want to turn
-	     * into a compute-to-MRF.
-	     */
+   return progress;
+}
 
-	    if (scan_inst->opcode == FS_OPCODE_TEX) {
-	       /* texturing writes several continuous regs, so we can't
-		* compute-to-mrf that.
-		*/
-	       break;
-	    }
+/**
+ * Walks through basic blocks, locking for repeated MRF writes and
+ * removing the later ones.
+ */
+bool
+fs_visitor::remove_duplicate_mrf_writes()
+{
+   fs_inst *last_mrf_move[16];
+   bool progress = false;
 
-	    /* If it's predicated, it (probably) didn't populate all
-	     * the channels.
-	     */
-	    if (scan_inst->predicated)
-	       break;
+   memset(last_mrf_move, 0, sizeof(last_mrf_move));
 
-	    /* SEND instructions can't have MRF as a destination. */
-	    if (scan_inst->mlen)
-	       break;
+   foreach_iter(exec_list_iterator, iter, this->instructions) {
+      fs_inst *inst = (fs_inst *)iter.get();
 
-	    if (intel->gen >= 6) {
-	       /* gen6 math instructions must have the destination be
-		* GRF, so no compute-to-MRF for them.
-		*/
-	       if (scan_inst->opcode == FS_OPCODE_RCP ||
-		   scan_inst->opcode == FS_OPCODE_RSQ ||
-		   scan_inst->opcode == FS_OPCODE_SQRT ||
-		   scan_inst->opcode == FS_OPCODE_EXP2 ||
-		   scan_inst->opcode == FS_OPCODE_LOG2 ||
-		   scan_inst->opcode == FS_OPCODE_SIN ||
-		   scan_inst->opcode == FS_OPCODE_COS ||
-		   scan_inst->opcode == FS_OPCODE_POW) {
-		  break;
-	       }
-	    }
+      switch (inst->opcode) {
+      case BRW_OPCODE_DO:
+      case BRW_OPCODE_WHILE:
+      case BRW_OPCODE_IF:
+      case BRW_OPCODE_ELSE:
+      case BRW_OPCODE_ENDIF:
+	 memset(last_mrf_move, 0, sizeof(last_mrf_move));
+	 continue;
+      default:
+	 break;
+      }
 
-	    if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
-	       /* Found the creator of our MRF's source value. */
-	       found = true;
-	       break;
+      if (inst->opcode == BRW_OPCODE_MOV &&
+	  inst->dst.file == MRF) {
+	 fs_inst *prev_inst = last_mrf_move[inst->dst.hw_reg];
+	 if (prev_inst && inst->equals(prev_inst)) {
+	    inst->remove();
+	    progress = true;
+	    continue;
+	 }
+      }
+
+      /* Clear out the last-write records for MRFs that were overwritten. */
+      if (inst->dst.file == MRF) {
+	 last_mrf_move[inst->dst.hw_reg] = NULL;
+      }
+
+      if (inst->mlen > 0) {
+	 /* Found a SEND instruction, which will include two of fewer
+	  * implied MRF writes.  We could do better here.
+	  */
+	 for (int i = 0; i < implied_mrf_writes(inst); i++) {
+	    last_mrf_move[inst->base_mrf + i] = NULL;
+	 }
+      }
+
+      /* Clear out any MRF move records whose sources got overwritten. */
+      if (inst->dst.file == GRF) {
+	 for (unsigned int i = 0; i < Elements(last_mrf_move); i++) {
+	    if (last_mrf_move[i] &&
+		last_mrf_move[i]->src[0].reg == inst->dst.reg) {
+	       last_mrf_move[i] = NULL;
 	    }
 	 }
       }
-      if (found) {
-	 scan_inst->dst.file = MRF;
-	 scan_inst->dst.hw_reg = inst->dst.hw_reg;
-	 scan_inst->saturate |= inst->saturate;
-	 inst->remove();
-	 progress = true;
+
+      if (inst->opcode == BRW_OPCODE_MOV &&
+	  inst->dst.file == MRF &&
+	  inst->src[0].file == GRF &&
+	  !inst->predicated) {
+	 last_mrf_move[inst->dst.hw_reg] = inst;
       }
    }
 
@@ -3091,6 +3285,7 @@ static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
 	 break;
       default:
 	 assert(!"not reached");
+	 brw_reg = brw_null_reg();
 	 break;
       }
       break;
@@ -3105,6 +3300,10 @@ static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
       assert(!"not reached");
       brw_reg = brw_null_reg();
       break;
+   default:
+      assert(!"not reached");
+      brw_reg = brw_null_reg();
+      break;
    }
    if (reg->abs)
       brw_reg = brw_abs(brw_reg);
@@ -3159,6 +3358,7 @@ fs_visitor::generate_code()
 
       brw_set_conditionalmod(p, inst->conditional_mod);
       brw_set_predicate_control(p, inst->predicated);
+      brw_set_saturate(p, inst->saturate);
 
       switch (inst->opcode) {
       case BRW_OPCODE_MOV:
@@ -3245,7 +3445,11 @@ fs_visitor::generate_code()
 	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 	 break;
       case BRW_OPCODE_CONTINUE:
-	 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
+	 /* FINISHME: We need to write the loop instruction support still. */
+	 if (intel->gen >= 6)
+	    brw_CONT_gen6(p, loop_stack[loop_stack_depth - 1]);
+	 else
+	    brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 	 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 	 break;
 
@@ -3259,16 +3463,18 @@ fs_visitor::generate_code()
 	 assert(loop_stack_depth > 0);
 	 loop_stack_depth--;
 	 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
-	 /* patch all the BREAK/CONT instructions from last BGNLOOP */
-	 while (inst0 > loop_stack[loop_stack_depth]) {
-	    inst0--;
-	    if (inst0->header.opcode == BRW_OPCODE_BREAK &&
-		inst0->bits3.if_else.jump_count == 0) {
-	       inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
+	 if (intel->gen < 6) {
+	    /* patch all the BREAK/CONT instructions from last BGNLOOP */
+	    while (inst0 > loop_stack[loop_stack_depth]) {
+	       inst0--;
+	       if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+		   inst0->bits3.if_else.jump_count == 0) {
+		  inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 	    }
-	    else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
-		     inst0->bits3.if_else.jump_count == 0) {
-	       inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
+	       else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+			inst0->bits3.if_else.jump_count == 0) {
+		  inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
+	       }
 	    }
 	 }
       }
@@ -3340,12 +3546,31 @@ fs_visitor::generate_code()
 		      ((uint32_t *)&p->store[i])[0]);
 	    }
 	    brw_disasm(stdout, &p->store[i], intel->gen);
-	    printf("\n");
 	 }
       }
 
       last_native_inst = p->nr_insn;
    }
+
+   brw_set_uip_jip(p);
+
+   /* OK, while the INTEL_DEBUG=wm above is very nice for debugging FS
+    * emit issues, it doesn't get the jump distances into the output,
+    * which is often something we want to debug.  So this is here in
+    * case you're doing that.
+    */
+   if (0) {
+      if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
+	 for (unsigned int i = 0; i < p->nr_insn; i++) {
+	    printf("0x%08x 0x%08x 0x%08x 0x%08x ",
+		   ((uint32_t *)&p->store[i])[3],
+		   ((uint32_t *)&p->store[i])[2],
+		   ((uint32_t *)&p->store[i])[1],
+		   ((uint32_t *)&p->store[i])[0]);
+	    brw_disasm(stdout, &p->store[i], intel->gen);
+	 }
+      }
+   }
 }
 
 GLboolean
@@ -3410,6 +3635,9 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
       bool progress;
       do {
 	 progress = false;
+
+	 progress = v.remove_duplicate_mrf_writes() || progress;
+
 	 v.calculate_live_intervals();
 	 progress = v.propagate_constants() || progress;
 	 progress = v.register_coalesce() || progress;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 9b7fcde858..de7b15312a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -96,10 +96,7 @@ public:
 
    void init()
    {
-      this->reg = 0;
-      this->reg_offset = 0;
-      this->negate = 0;
-      this->abs = 0;
+      memset(this, 0, sizeof(*this));
       this->hw_reg = -1;
       this->smear = -1;
    }
@@ -151,6 +148,21 @@ public:
    fs_reg(enum register_file file, int hw_reg, uint32_t type);
    fs_reg(class fs_visitor *v, const struct glsl_type *type);
 
+   bool equals(fs_reg *r)
+   {
+      return (file == r->file &&
+	      reg == r->reg &&
+	      reg_offset == r->reg_offset &&
+	      hw_reg == r->hw_reg &&
+	      type == r->type &&
+	      negate == r->negate &&
+	      abs == r->abs &&
+	      memcmp(&fixed_hw_reg, &r->fixed_hw_reg,
+		     sizeof(fixed_hw_reg)) == 0 &&
+	      smear == r->smear &&
+	      imm.u == r->imm.u);
+   }
+
    /** Register file: ARF, GRF, MRF, IMM. */
    enum register_file file;
    /** virtual register number.  0 = fixed hw reg */
@@ -174,6 +186,10 @@ public:
    } imm;
 };
 
+static const fs_reg reg_undef;
+static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
+static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
+
 class fs_inst : public exec_node {
 public:
    /* Callers of this talloc-based new need not call delete. It's
@@ -190,18 +206,14 @@ public:
 
    void init()
    {
+      memset(this, 0, sizeof(*this));
       this->opcode = BRW_OPCODE_NOP;
-      this->saturate = false;
       this->conditional_mod = BRW_CONDITIONAL_NONE;
-      this->predicated = false;
-      this->sampler = 0;
-      this->target = 0;
-      this->eot = false;
-      this->header_present = false;
-      this->shadow_compare = false;
-      this->mlen = 0;
-      this->base_mrf = 0;
-      this->offset = 0;
+
+      this->dst = reg_undef;
+      this->src[0] = reg_undef;
+      this->src[1] = reg_undef;
+      this->src[2] = reg_undef;
    }
 
    fs_inst()
@@ -273,6 +285,26 @@ public:
 	 assert(src[2].reg_offset >= 0);
    }
 
+   bool equals(fs_inst *inst)
+   {
+      return (opcode == inst->opcode &&
+	      dst.equals(&inst->dst) &&
+	      src[0].equals(&inst->src[0]) &&
+	      src[1].equals(&inst->src[1]) &&
+	      src[2].equals(&inst->src[2]) &&
+	      saturate == inst->saturate &&
+	      predicated == inst->predicated &&
+	      conditional_mod == inst->conditional_mod &&
+	      mlen == inst->mlen &&
+	      base_mrf == inst->base_mrf &&
+	      sampler == inst->sampler &&
+	      target == inst->target &&
+	      eot == inst->eot &&
+	      header_present == inst->header_present &&
+	      shadow_compare == inst->shadow_compare &&
+	      offset == inst->offset);
+   }
+
    int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
    fs_reg dst;
    fs_reg src[3];
@@ -375,6 +407,7 @@ public:
    bool register_coalesce();
    bool compute_to_mrf();
    bool dead_code_eliminate();
+   bool remove_duplicate_mrf_writes();
    bool virtual_grf_interferes(int a, int b);
    void generate_code();
    void generate_fb_write(fs_inst *inst);
@@ -400,6 +433,7 @@ public:
    fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate);
    fs_inst *emit_math(fs_opcodes op, fs_reg dst, fs_reg src0);
    fs_inst *emit_math(fs_opcodes op, fs_reg dst, fs_reg src0, fs_reg src1);
+   bool try_emit_saturate(ir_expression *ir);
    void emit_bool_to_cond_code(ir_rvalue *condition);
    void emit_if_gen6(ir_if *ir);
    void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset);
@@ -411,6 +445,7 @@ public:
    struct brw_reg interp_reg(int location, int channel);
    int setup_uniform_values(int loc, const glsl_type *type);
    void setup_builtin_uniform_values(ir_variable *ir);
+   int implied_mrf_writes(fs_inst *inst);
 
    struct brw_context *brw;
    const struct gl_fragment_program *fp;
@@ -454,9 +489,5 @@ public:
    int grf_used;
 };
 
-static const fs_reg reg_undef;
-static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
-static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
-
 GLboolean brw_do_channel_expressions(struct exec_list *instructions);
 GLboolean brw_do_vector_splitting(struct exec_list *instructions);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 2a6da4058b..20bfa4c3ea 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -205,6 +205,8 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
    case ir_unop_round_even:
    case ir_unop_sin:
    case ir_unop_cos:
+   case ir_unop_sin_reduced:
+   case ir_unop_cos_reduced:
    case ir_unop_dFdx:
    case ir_unop_dFdy:
       for (i = 0; i < vector_elements; i++) {
@@ -288,34 +290,6 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
       break;
    }
 
-   case ir_binop_cross: {
-      for (i = 0; i < vector_elements; i++) {
-	 int swiz0 = (i + 1) % 3;
-	 int swiz1 = (i + 2) % 3;
-	 ir_expression *temp1, *temp2;
-
-	 temp1 = new(mem_ctx) ir_expression(ir_binop_mul,
-					    element_type,
-					    get_element(op_var[0], swiz0),
-					    get_element(op_var[1], swiz1));
-
-	 temp2 = new(mem_ctx) ir_expression(ir_binop_mul,
-					    element_type,
-					    get_element(op_var[1], swiz0),
-					    get_element(op_var[0], swiz1));
-
-	 temp2 = new(mem_ctx) ir_expression(ir_unop_neg,
-					    element_type,
-					    temp2,
-					    NULL);
-
-	 assign(ir, i, new(mem_ctx) ir_expression(ir_binop_add,
-						  element_type,
-						  temp1, temp2));
-      }
-      break;
-   }
-
    case ir_binop_logic_and:
    case ir_binop_logic_xor:
    case ir_binop_logic_or:
@@ -356,6 +330,9 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
    case ir_unop_noise:
       assert(!"noise should have been broken down to function call");
       break;
+   case ir_quadop_vector:
+      assert(!"should have been lowered");
+      break;
    }
 
    ir->remove();
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index b0c76f4094..73b41fdbce 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -166,6 +166,9 @@ static void populate_key( struct brw_context *brw,
 			  struct brw_gs_prog_key *key )
 {
    struct gl_context *ctx = &brw->intel.ctx;
+   struct intel_context *intel = &brw->intel;
+   int prim_gs_always;
+
    memset(key, 0, sizeof(*key));
 
    /* CACHE_NEW_VS_PROG */
@@ -185,10 +188,14 @@ static void populate_key( struct brw_context *brw,
       key->pv_first = GL_TRUE;
    }
 
-   key->need_gs_prog = (key->hint_gs_always ||
-			brw->primitive == GL_QUADS ||
+   if (intel->gen == 6)
+       prim_gs_always = brw->primitive == GL_LINE_LOOP;
+   else
+       prim_gs_always = brw->primitive == GL_QUADS ||
 			brw->primitive == GL_QUAD_STRIP ||
-			brw->primitive == GL_LINE_LOOP);
+			brw->primitive == GL_LINE_LOOP;
+
+   key->need_gs_prog = (key->hint_gs_always || prim_gs_always);
 }
 
 /* Calculate interpolants for triangle and line rasterization.
@@ -205,8 +212,10 @@ static void prepare_gs_prog(struct brw_context *brw)
       brw->gs.prog_active = key.need_gs_prog;
    }
 
+   drm_intel_bo_unreference(brw->gs.prog_bo);
+   brw->gs.prog_bo = NULL;
+
    if (brw->gs.prog_active) {
-      drm_intel_bo_unreference(brw->gs.prog_bo);
       brw->gs.prog_bo = brw_search_cache(&brw->cache, BRW_GS_PROG,
 					 &key, sizeof(key),
 					 NULL, 0,
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 1d350bc041..a91b0528fa 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -38,40 +38,6 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 
-
-
-
-
-/***********************************************************************
- * Blend color
- */
-
-static void upload_blend_constant_color(struct brw_context *brw)
-{
-   struct gl_context *ctx = &brw->intel.ctx;
-   struct brw_blend_constant_color bcc;
-
-   memset(&bcc, 0, sizeof(bcc));      
-   bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
-   bcc.header.length = sizeof(bcc)/4-2;
-   bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
-   bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
-   bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
-   bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
-
-   BRW_CACHED_BATCH_STRUCT(brw, &bcc);
-}
-
-
-const struct brw_tracked_state brw_blend_constant_color = {
-   .dirty = {
-      .mesa = _NEW_COLOR,
-      .brw = BRW_NEW_CONTEXT,
-      .cache = 0
-   },
-   .emit = upload_blend_constant_color
-};
-
 /* Constant single cliprect for framebuffer object or DRI2 drawing */
 static void upload_drawing_rect(struct brw_context *brw)
 {
@@ -339,6 +305,9 @@ static void upload_polygon_stipple(struct brw_context *brw)
    struct brw_polygon_stipple bps;
    GLuint i;
 
+   if (!ctx->Polygon.StippleFlag)
+      return;
+
    memset(&bps, 0, sizeof(bps));
    bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
    bps.header.length = sizeof(bps)/4-2;
@@ -381,6 +350,9 @@ static void upload_polygon_stipple_offset(struct brw_context *brw)
    struct gl_context *ctx = &brw->intel.ctx;
    struct brw_polygon_stipple_offset bpso;
 
+   if (!ctx->Polygon.StippleFlag)
+      return;
+
    memset(&bpso, 0, sizeof(bpso));
    bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
    bpso.header.length = sizeof(bpso)/4-2;
@@ -409,7 +381,7 @@ static void upload_polygon_stipple_offset(struct brw_context *brw)
 
 const struct brw_tracked_state brw_polygon_stipple_offset = {
    .dirty = {
-      .mesa = _NEW_WINDOW_POS,
+      .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE,
       .brw = BRW_NEW_CONTEXT,
       .cache = 0
    },
@@ -421,9 +393,10 @@ const struct brw_tracked_state brw_polygon_stipple_offset = {
  */
 static void upload_aa_line_parameters(struct brw_context *brw)
 {
+   struct gl_context *ctx = &brw->intel.ctx;
    struct brw_aa_line_parameters balp;
 
-   if (!brw->has_aa_line_parameters)
+   if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters)
       return;
 
    /* use legacy aa line coverage computation */
@@ -436,7 +409,7 @@ static void upload_aa_line_parameters(struct brw_context *brw)
 
 const struct brw_tracked_state brw_aa_line_parameters = {
    .dirty = {
-      .mesa = 0,
+      .mesa = _NEW_LINE,
       .brw = BRW_NEW_CONTEXT,
       .cache = 0
    },
@@ -454,6 +427,9 @@ static void upload_line_stipple(struct brw_context *brw)
    GLfloat tmp;
    GLint tmpi;
 
+   if (!ctx->Line.StippleFlag)
+      return;
+
    memset(&bls, 0, sizeof(bls));
    bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
    bls.header.length = sizeof(bls)/4 - 2;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index 1367d81469..94efa79109 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -142,7 +142,6 @@ static GLboolean brwProgramStringNotify( struct gl_context *ctx,
       if (newFP == curFP)
 	 brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
       newFP->id = brw->program_id++;      
-      newFP->isGLSL = brw_wm_is_glsl(fprog);
 
       /* Don't reject fragment shaders for their Mesa IR state when we're
        * using the new FS backend.
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 3beed16945..4bb93e7336 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -164,7 +164,8 @@ void brw_destroy_caches( struct brw_context *brw );
 /***********************************************************************
  * brw_state_batch.c
  */
-#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)))
+#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data(brw->intel.batch, (s), \
+							sizeof(*(s)), false)
 #define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) )
 
 GLboolean brw_cached_batch_struct( struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c
index be3989eb7d..a21af13caa 100644
--- a/src/mesa/drivers/dri/i965/brw_state_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_state_batch.c
@@ -48,7 +48,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
    struct header *newheader = (struct header *)data;
 
    if (brw->emit_state_always) {
-      intel_batchbuffer_data(brw->intel.batch, data, sz);
+      intel_batchbuffer_data(brw->intel.batch, data, sz, false);
       return GL_TRUE;
    }
 
@@ -75,7 +75,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw,
 
  emit:
    memcpy(item->header, newheader, sz);
-   intel_batchbuffer_data(brw->intel.batch, data, sz);
+   intel_batchbuffer_data(brw->intel.batch, data, sz, false);
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index b79b33c2e3..e262887471 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -107,14 +107,14 @@ static void dump_wm_surface_state(struct brw_context *brw)
       char name[20];
 
       if (surf_bo == NULL) {
-	 fprintf(stderr, "  WM SS%d: NULL\n", i);
+	 fprintf(stderr, "WM SURF%d: NULL\n", i);
 	 continue;
       }
       drm_intel_bo_map(surf_bo, GL_FALSE);
       surfoff = surf_bo->offset + brw->wm.surf_offset[i];
       surf = (struct brw_surface_state *)(surf_bo->virtual + brw->wm.surf_offset[i]);
 
-      sprintf(name, "WM SS%d", i);
+      sprintf(name, "WM SURF%d", i);
       state_out(name, surf, surfoff, 0, "%s %s\n",
 		get_965_surfacetype(surf->ss0.surface_type),
 		get_965_surface_format(surf->ss0.surface_format));
@@ -132,6 +132,53 @@ static void dump_wm_surface_state(struct brw_context *brw)
    }
 }
 
+
+static void dump_wm_sampler_state(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->intel.ctx;
+   int i;
+
+   if (!brw->wm.sampler_bo) {
+      fprintf(stderr, "WM_SAMPLER: NULL\n");
+      return;
+   }
+
+   drm_intel_bo_map(brw->wm.sampler_bo, GL_FALSE);
+   for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
+      unsigned int offset;
+      struct brw_sampler_state *samp;
+      struct brw_sampler_default_color *sdc;
+      char name[20];
+
+      if (!ctx->Texture.Unit[i]._ReallyEnabled) {
+	 fprintf(stderr, "WM SAMP%d: disabled\n", i);
+	 continue;
+      }
+
+      offset = brw->wm.sampler_bo->offset +
+	 i * sizeof(struct brw_sampler_state);
+      samp = (struct brw_sampler_state *)(brw->wm.sampler_bo->virtual +
+					  i * sizeof(struct brw_sampler_state));
+
+      sprintf(name, "WM SAMP%d", i);
+      state_out(name, samp, offset, 0, "filtering\n");
+      state_out(name, samp, offset, 1, "wrapping, lod\n");
+      state_out(name, samp, offset, 2, "default color pointer\n");
+      state_out(name, samp, offset, 3, "chroma key, aniso\n");
+
+      sprintf(name, " WM SDC%d", i);
+
+      drm_intel_bo_map(brw->wm.sdc_bo[i], GL_FALSE);
+      sdc = (struct brw_sampler_default_color *)(brw->wm.sdc_bo[i]->virtual);
+      state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 0, "r\n");
+      state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 1, "g\n");
+      state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 2, "b\n");
+      state_out(name, sdc, brw->wm.sdc_bo[i]->offset, 3, "a\n");
+      drm_intel_bo_unmap(brw->wm.sdc_bo[i]);
+   }
+   drm_intel_bo_unmap(brw->wm.sampler_bo);
+}
+
 static void dump_sf_viewport_state(struct brw_context *brw)
 {
    const char *name = "SF VP";
@@ -324,6 +371,7 @@ void brw_debug_batch(struct intel_context *intel)
 
    state_struct_out("WM bind", brw->wm.bind_bo, 4 * brw->wm.nr_surfaces);
    dump_wm_surface_state(brw);
+   dump_wm_sampler_state(brw);
 
    if (intel->gen < 6)
        state_struct_out("VS", brw->vs.state_bo, sizeof(struct brw_vs_unit_state));
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 338f3876b3..eba4411ca7 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -129,7 +129,7 @@ const struct brw_tracked_state *gen6_atoms[] =
 
    &brw_vs_constants, /* Before vs_surfaces and constant_buffer */
    &brw_wm_constants, /* Before wm_surfaces and constant_buffer */
-   &gen6_wm_constants, /* Before wm_surfaces and constant_buffer */
+   &gen6_wm_constants, /* Before wm_state */
 
    &brw_vs_surfaces,		/* must do before unit */
    &brw_wm_constant_surface,	/* must do before wm surfaces/bind bo */
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 8ce9af9c4f..461f27048c 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1064,6 +1064,15 @@ struct brw_sampler_default_color {
    GLfloat color[4];
 };
 
+struct gen5_sampler_default_color {
+   uint8_t ub[4];
+   float f[4];
+   uint16_t hf[4];
+   uint16_t us[4];
+   int16_t s[4];
+   uint8_t b[4];
+};
+
 struct brw_sampler_state
 {
    
@@ -1169,7 +1178,12 @@ struct brw_surface_state
       GLuint cube_neg_y:1; 
       GLuint cube_pos_x:1; 
       GLuint cube_neg_x:1; 
-      GLuint pad:4;
+      GLuint pad:2;
+      /* Required on gen6 for surfaces accessed through render cache messages.
+       */
+      GLuint render_cache_read_write:1;
+      /* Ironlake and newer: instead of replicating one of the texels */
+      GLuint cube_corner_average:1;
       GLuint mipmap_layout_mode:1; 
       GLuint vert_line_stride_ofs:1; 
       GLuint vert_line_stride:1; 
@@ -1539,6 +1553,21 @@ struct brw_instruction
 	 GLuint  pad0:12;
       } if_else;
 
+      struct
+      {
+	 /* Signed jump distance to the ip to jump to if all channels
+	  * are disabled after the break or continue.  It should point
+	  * to the end of the innermost control flow block, as that's
+	  * where some channel could get re-enabled.
+	  */
+	 int jip:16;
+
+	 /* Signed jump distance to the location to resume execution
+	  * of this channel if it's enabled for the break or continue.
+	  */
+	 int uip:16;
+      } break_cont;
+
       struct {
 	 GLuint function:4;
 	 GLuint int_type:1;
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index 4a41c7a517..6ae75d22c1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -99,8 +99,8 @@ static void do_vs_prog( struct brw_context *brw,
    (void) ctx;
 
    aux_size = sizeof(c.prog_data);
-   if (c.vp->use_const_buffer)
-      aux_size += c.vp->program.Base.Parameters->NumParameters;
+   /* constant_map */
+   aux_size += c.vp->program.Base.Parameters->NumParameters;
 
    drm_intel_bo_unreference(brw->vs.prog_bo);
    brw->vs.prog_bo = brw_upload_cache_with_auxdata(&brw->cache, BRW_VS_PROG,
@@ -130,6 +130,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
    key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
    key.copy_edgeflag = (ctx->Polygon.FrontMode != GL_FILL ||
 			ctx->Polygon.BackMode != GL_FILL);
+   key.two_side_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
 
    /* _NEW_POINT */
    if (ctx->Point.PointSprite) {
@@ -157,7 +158,7 @@ static void brw_upload_vs_prog(struct brw_context *brw)
  */
 const struct brw_tracked_state brw_vs_prog = {
    .dirty = {
-      .mesa  = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT,
+      .mesa  = _NEW_TRANSFORM | _NEW_POLYGON | _NEW_POINT | _NEW_LIGHT,
       .brw   = BRW_NEW_VERTEX_PROGRAM,
       .cache = 0
    },
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h b/src/mesa/drivers/dri/i965/brw_vs.h
index 9338a6b7db..0b88cc1ec7 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -44,6 +44,7 @@ struct brw_vs_prog_key {
    GLuint nr_userclip:4;
    GLuint copy_edgeflag:1;
    GLuint point_coord_replace:8;
+   GLuint two_side_color: 1;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 7e43324a1f..326bb1e562 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -140,9 +140,13 @@ clear_current_const(struct brw_vs_compile *c)
 static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 {
    struct intel_context *intel = &c->func.brw->intel;
-   GLuint i, reg = 0, mrf;
+   GLuint i, reg = 0, mrf, j;
    int attributes_in_vue;
    int first_reladdr_output;
+   int max_constant;
+   int constant = 0;
+   int vert_result_reoder[VERT_RESULT_MAX];
+   int bfc = 0;
 
    /* Determine whether to use a real constant buffer or use a block
     * of GRF registers for constants.  The later is faster but only
@@ -181,62 +185,81 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 
    }
 
-   /* Vertex program parameters from curbe:
+   /* Assign some (probably all) of the vertex program constants to
+    * the push constant buffer/CURBE.
+    *
+    * There's an obvious limit to the numer of push constants equal to
+    * the number of register available, and that number is smaller
+    * than the minimum maximum number of vertex program parameters, so
+    * support for pull constants is required if we overflow.
+    * Additionally, on gen6 the number of push constants is even
+    * lower.
+    *
+    * When there's relative addressing, we don't know what range of
+    * Mesa IR registers can be accessed.  And generally, when relative
+    * addressing is used we also have too many constants to load them
+    * all as push constants.  So, we'll just support relative
+    * addressing out of the pull constant buffers, and try to load as
+    * many statically-accessed constants into the push constant buffer
+    * as we can.
     */
-   if (c->vp->use_const_buffer) {
-      int max_constant = BRW_MAX_GRF - 20 - c->vp->program.Base.NumTemporaries;
-      int constant = 0;
-
-      /* We've got more constants than we can load with the push
-       * mechanism.  This is often correlated with reladdr loads where
-       * we should probably be using a pull mechanism anyway to avoid
-       * excessive reading.  However, the pull mechanism is slow in
-       * general.  So, we try to allocate as many non-reladdr-loaded
-       * constants through the push buffer as we can before giving up.
-       */
-      memset(c->constant_map, -1, c->vp->program.Base.Parameters->NumParameters);
-      for (i = 0;
-	   i < c->vp->program.Base.NumInstructions && constant < max_constant;
-	   i++) {
-	 struct prog_instruction *inst = &c->vp->program.Base.Instructions[i];
-	 int arg;
-
-	 for (arg = 0; arg < 3 && constant < max_constant; arg++) {
-	    if ((inst->SrcReg[arg].File != PROGRAM_STATE_VAR &&
-		 inst->SrcReg[arg].File != PROGRAM_CONSTANT &&
-		 inst->SrcReg[arg].File != PROGRAM_UNIFORM &&
-		 inst->SrcReg[arg].File != PROGRAM_ENV_PARAM &&
-		 inst->SrcReg[arg].File != PROGRAM_LOCAL_PARAM) ||
-		inst->SrcReg[arg].RelAddr)
-	       continue;
-
-	    if (c->constant_map[inst->SrcReg[arg].Index] == -1) {
-	       c->constant_map[inst->SrcReg[arg].Index] = constant++;
-	    }
+   if (intel->gen >= 6) {
+      /* We can only load 32 regs of push constants. */
+      max_constant = 32 * 2 - c->key.nr_userclip;
+   } else {
+      max_constant = BRW_MAX_GRF - 20 - c->vp->program.Base.NumTemporaries;
+   }
+
+   /* constant_map maps from ParameterValues[] index to index in the
+    * push constant buffer, or -1 if it's only in the pull constant
+    * buffer.
+    */
+   memset(c->constant_map, -1, c->vp->program.Base.Parameters->NumParameters);
+   for (i = 0;
+	i < c->vp->program.Base.NumInstructions && constant < max_constant;
+	i++) {
+      struct prog_instruction *inst = &c->vp->program.Base.Instructions[i];
+      int arg;
+
+      for (arg = 0; arg < 3 && constant < max_constant; arg++) {
+	 if (inst->SrcReg[arg].File != PROGRAM_STATE_VAR &&
+	     inst->SrcReg[arg].File != PROGRAM_CONSTANT &&
+	     inst->SrcReg[arg].File != PROGRAM_UNIFORM &&
+	     inst->SrcReg[arg].File != PROGRAM_ENV_PARAM &&
+	     inst->SrcReg[arg].File != PROGRAM_LOCAL_PARAM) {
+	    continue;
 	 }
-      }
 
-      for (i = 0; i < constant; i++) {
-         c->regs[PROGRAM_STATE_VAR][i] = stride( brw_vec4_grf(reg+i/2,
-							      (i%2) * 4),
-						 0, 4, 1);
+	 if (inst->SrcReg[arg].RelAddr) {
+	    c->vp->use_const_buffer = GL_TRUE;
+	    continue;
+	 }
+
+	 if (c->constant_map[inst->SrcReg[arg].Index] == -1) {
+	    c->constant_map[inst->SrcReg[arg].Index] = constant++;
+	 }
       }
-      reg += (constant + 1) / 2;
-      c->prog_data.curb_read_length = reg - 1;
-      /* XXX 0 causes a bug elsewhere... */
-      c->prog_data.nr_params = MAX2(constant * 4, 4);
    }
-   else {
-      /* use a section of the GRF for constants */
-      GLuint nr_params = c->vp->program.Base.Parameters->NumParameters;
-      for (i = 0; i < nr_params; i++) {
-         c->regs[PROGRAM_STATE_VAR][i] = stride( brw_vec4_grf(reg+i/2, (i%2) * 4), 0, 4, 1);
-      }
-      reg += (nr_params + 1) / 2;
-      c->prog_data.curb_read_length = reg - 1;
 
-      c->prog_data.nr_params = nr_params * 4;
+   /* If we ran out of push constant space, then we'll also upload all
+    * constants through the pull constant buffer so that they can be
+    * accessed no matter what.  For relative addressing (the common
+    * case) we need them all in place anyway.
+    */
+   if (constant == max_constant)
+      c->vp->use_const_buffer = GL_TRUE;
+
+   for (i = 0; i < constant; i++) {
+      c->regs[PROGRAM_STATE_VAR][i] = stride(brw_vec4_grf(reg + i / 2,
+							  (i % 2) * 4),
+					     0, 4, 1);
    }
+   reg += (constant + 1) / 2;
+   c->prog_data.curb_read_length = reg - 1;
+   c->prog_data.nr_params = constant * 4;
+   /* XXX 0 causes a bug elsewhere... */
+   if (intel->gen < 6 && c->prog_data.nr_params == 0)
+      c->prog_data.nr_params = 4;
 
    /* Allocate input regs:  
     */
@@ -270,7 +293,36 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
       mrf = 4;
 
    first_reladdr_output = get_first_reladdr_output(&c->vp->program);
-   for (i = 0; i < VERT_RESULT_MAX; i++) {
+
+   for (i = 0; i < VERT_RESULT_MAX; i++)
+       vert_result_reoder[i] = i;
+
+   /* adjust attribute order in VUE for BFC0/BFC1 on Gen6+ */
+   if (intel->gen >= 6 && c->key.two_side_color) {
+       if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1)) &&
+           (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))) {
+           assert(c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0));
+           assert(c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0));
+           bfc = 2;
+       } else if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0)) &&
+           (c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0)))
+           bfc = 1;
+
+       if (bfc) {
+           for (i = 0; i < bfc; i++) {
+               vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 0] = VERT_RESULT_COL0 + i;
+               vert_result_reoder[VERT_RESULT_COL0 + i * 2 + 1] = VERT_RESULT_BFC0 + i;
+           }
+
+           for (i = VERT_RESULT_COL0 + bfc * 2; i < VERT_RESULT_BFC0 + bfc; i++) {
+               vert_result_reoder[i] = i - bfc;
+           }
+       }
+   }
+
+   for (j = 0; j < VERT_RESULT_MAX; j++) {
+      i = vert_result_reoder[j];
+
       if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) {
 	 c->nr_outputs++;
          assert(i < Elements(c->regs[PROGRAM_OUTPUT]));
@@ -281,7 +333,6 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 	 else if (i == VERT_RESULT_PSIZ) {
 	    c->regs[PROGRAM_OUTPUT][i] = brw_vec8_grf(reg, 0);
 	    reg++;
-	    mrf++;		/* just a placeholder?  XXX fix later stages & remove this */
 	 }
 	 else {
 	    /* Two restrictions on our compute-to-MRF here.  The
@@ -574,9 +625,18 @@ static void emit_max( struct brw_compile *p,
 		      struct brw_reg arg0,
 		      struct brw_reg arg1 )
 {
-   brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
-   brw_SEL(p, dst, arg0, arg1);
-   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   struct intel_context *intel = &p->brw->intel;
+
+   if (intel->gen >= 6) {
+      brw_set_conditionalmod(p, BRW_CONDITIONAL_GE);
+      brw_SEL(p, dst, arg0, arg1);
+      brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
+      brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   } else {
+      brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0, arg1);
+      brw_SEL(p, dst, arg0, arg1);
+      brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   }
 }
 
 static void emit_min( struct brw_compile *p, 
@@ -584,9 +644,34 @@ static void emit_min( struct brw_compile *p,
 		      struct brw_reg arg0,
 		      struct brw_reg arg1 )
 {
-   brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
-   brw_SEL(p, dst, arg0, arg1);
-   brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   struct intel_context *intel = &p->brw->intel;
+
+   if (intel->gen >= 6) {
+      brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
+      brw_SEL(p, dst, arg0, arg1);
+      brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
+      brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   } else {
+      brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, arg1);
+      brw_SEL(p, dst, arg0, arg1);
+      brw_set_predicate_control(p, BRW_PREDICATE_NONE);
+   }
+}
+
+static void emit_arl(struct brw_compile *p,
+		     struct brw_reg dst,
+		     struct brw_reg src)
+{
+   struct intel_context *intel = &p->brw->intel;
+
+   if (intel->gen >= 6) {
+      struct brw_reg dst_f = retype(dst, BRW_REGISTER_TYPE_F);
+
+      brw_RNDD(p, dst_f, src);
+      brw_MOV(p, dst, dst_f);
+   } else {
+      brw_RNDD(p, dst, src);
+   }
 }
 
 static void emit_math1_gen4(struct brw_vs_compile *c,
@@ -680,7 +765,7 @@ emit_math1(struct brw_vs_compile *c,
       emit_math1_gen4(c, function, dst, arg0, precision);
 }
 
-static void emit_math2( struct brw_vs_compile *c, 
+static void emit_math2_gen4( struct brw_vs_compile *c, 
 			GLuint function,
 			struct brw_reg dst,
 			struct brw_reg arg0,
@@ -688,14 +773,11 @@ static void emit_math2( struct brw_vs_compile *c,
 			GLuint precision)
 {
    struct brw_compile *p = &c->func;
-   struct intel_context *intel = &p->brw->intel;
    struct brw_reg tmp = dst;
    GLboolean need_tmp = GL_FALSE;
 
-   if (dst.file != BRW_GENERAL_REGISTER_FILE)
-      need_tmp = GL_TRUE;
-
-   if (intel->gen < 6 && dst.dw1.bits.writemask != 0xf)
+   if (dst.file != BRW_GENERAL_REGISTER_FILE ||
+       dst.dw1.bits.writemask != 0xf)
       need_tmp = GL_TRUE;
 
    if (need_tmp) 
@@ -718,6 +800,53 @@ static void emit_math2( struct brw_vs_compile *c,
    }
 }
 
+static void emit_math2_gen6( struct brw_vs_compile *c, 
+			GLuint function,
+			struct brw_reg dst,
+			struct brw_reg arg0,
+			struct brw_reg arg1,
+			GLuint precision)
+{
+   struct brw_compile *p = &c->func;
+   struct brw_reg tmp_src0, tmp_src1, tmp_dst;
+
+   tmp_src0 = get_tmp(c);
+   tmp_src1 = get_tmp(c);
+   tmp_dst = get_tmp(c);
+
+   brw_MOV(p, tmp_src0, arg0);
+   brw_MOV(p, tmp_src1, arg1);
+   
+   brw_set_access_mode(p, BRW_ALIGN_1);
+   brw_math2(p,
+	    tmp_dst,
+	    function,
+	    tmp_src0,
+	    tmp_src1);
+   brw_set_access_mode(p, BRW_ALIGN_16);
+
+   brw_MOV(p, dst, tmp_dst);
+
+   release_tmp(c, tmp_src0);
+   release_tmp(c, tmp_src1);
+   release_tmp(c, tmp_dst);
+}
+
+static void emit_math2( struct brw_vs_compile *c, 
+			GLuint function,
+			struct brw_reg dst,
+			struct brw_reg arg0,
+			struct brw_reg arg1,
+			GLuint precision)
+{
+   struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
+
+   if (intel->gen >= 6)
+      emit_math2_gen6(c, function, dst, arg0, arg1, precision);
+   else
+      emit_math2_gen4(c, function, dst, arg0, arg1, precision);
+}
 
 static void emit_exp_noalias( struct brw_vs_compile *c,
 			      struct brw_reg dst,
@@ -990,8 +1119,6 @@ get_constant(struct brw_vs_compile *c,
 
    assert(argIndex < 3);
 
-   assert(c->func.brw->intel.gen < 6); /* FINISHME */
-
    if (c->current_const[argIndex].index != src->Index) {
       /* Keep track of the last constant loaded in this slot, for reuse. */
       c->current_const[argIndex].index = src->Index;
@@ -1022,14 +1149,14 @@ get_reladdr_constant(struct brw_vs_compile *c,
 {
    const struct prog_src_register *src = &inst->SrcReg[argIndex];
    struct brw_compile *p = &c->func;
+   struct brw_context *brw = p->brw;
+   struct intel_context *intel = &brw->intel;
    struct brw_reg const_reg = c->current_const[argIndex].reg;
-   struct brw_reg addrReg = c->regs[PROGRAM_ADDRESS][0];
-   struct brw_reg byte_addr_reg = retype(get_tmp(c), BRW_REGISTER_TYPE_D);
+   struct brw_reg addr_reg = c->regs[PROGRAM_ADDRESS][0];
+   uint32_t offset;
 
    assert(argIndex < 3);
 
-   assert(c->func.brw->intel.gen < 6); /* FINISHME */
-
    /* Can't reuse a reladdr constant load. */
    c->current_const[argIndex].index = -1;
 
@@ -1038,15 +1165,21 @@ get_reladdr_constant(struct brw_vs_compile *c,
 	  src->Index, argIndex, c->current_const[argIndex].reg.nr);
 #endif
 
-   brw_MUL(p, byte_addr_reg, addrReg, brw_imm_ud(16));
+   if (intel->gen >= 6) {
+      offset = src->Index;
+   } else {
+      struct brw_reg byte_addr_reg = retype(get_tmp(c), BRW_REGISTER_TYPE_D);
+      brw_MUL(p, byte_addr_reg, addr_reg, brw_imm_d(16));
+      addr_reg = byte_addr_reg;
+      offset = 16 * src->Index;
+   }
 
    /* fetch the first vec4 */
    brw_dp_READ_4_vs_relative(p,
-			     const_reg,                     /* writeback dest */
-			     byte_addr_reg,                 /* address register */
-			     16 * src->Index,               /* byte offset */
-			     SURF_INDEX_VERT_CONST_BUFFER   /* binding table index */
-			     );
+			     const_reg,
+			     addr_reg,
+			     offset,
+			     SURF_INDEX_VERT_CONST_BUFFER);
 
    return const_reg;
 }
@@ -1241,22 +1374,18 @@ get_src_reg( struct brw_vs_compile *c,
    case PROGRAM_UNIFORM:
    case PROGRAM_ENV_PARAM:
    case PROGRAM_LOCAL_PARAM:
-      if (c->vp->use_const_buffer) {
-	 if (!relAddr && c->constant_map[index] != -1) {
-	    assert(c->regs[PROGRAM_STATE_VAR][c->constant_map[index]].nr != 0);
-	    return c->regs[PROGRAM_STATE_VAR][c->constant_map[index]];
-	 } else if (relAddr)
+      if (!relAddr && c->constant_map[index] != -1) {
+	 /* Take from the push constant buffer if possible. */
+	 assert(c->regs[PROGRAM_STATE_VAR][c->constant_map[index]].nr != 0);
+	 return c->regs[PROGRAM_STATE_VAR][c->constant_map[index]];
+      } else {
+	 /* Must be in the pull constant buffer then .*/
+	 assert(c->vp->use_const_buffer);
+	 if (relAddr)
 	    return get_reladdr_constant(c, inst, argIndex);
 	 else
 	    return get_constant(c, inst, argIndex);
       }
-      else if (relAddr) {
-         return deref(c, c->regs[PROGRAM_STATE_VAR][0], index, 16);
-      }
-      else {
-         assert(c->regs[PROGRAM_STATE_VAR][index].nr != 0);
-         return c->regs[PROGRAM_STATE_VAR][index];
-      }
    case PROGRAM_ADDRESS:
       assert(index == 0);
       return c->regs[file][index];
@@ -1585,6 +1714,8 @@ static void emit_vertex_write( struct brw_vs_compile *c)
 	 break;
       if (!(c->prog_data.outputs_written & BITFIELD64_BIT(i)))
 	 continue;
+      if (i == VERT_RESULT_PSIZ)
+	 continue;
 
       if (i >= VERT_RESULT_TEX0 &&
 	  c->regs[PROGRAM_OUTPUT][i].file == BRW_GENERAL_REGISTER_FILE) {
@@ -1848,7 +1979,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, args[0], BRW_MATH_PRECISION_FULL);
 	 break;
       case OPCODE_ARL:
-	 brw_RNDD(p, dst, args[0]);
+	 emit_arl(p, dst, args[0]);
 	 break;
       case OPCODE_FLR:
 	 brw_RNDD(p, dst, args[0]);
@@ -1895,7 +2026,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 emit_math1(c, BRW_MATH_FUNCTION_INV, dst, args[0], BRW_MATH_PRECISION_FULL);
 	 break;
       case OPCODE_RSQ:
-	 emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, args[0], BRW_MATH_PRECISION_FULL);
+	 emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, brw_abs(args[0]), BRW_MATH_PRECISION_FULL);
 	 break;
 
       case OPCODE_SEQ:
@@ -1969,35 +2100,42 @@ void brw_vs_emit(struct brw_vs_compile *c )
          break;
       case OPCODE_CONT:
 	 brw_set_predicate_control(p, get_predicate(inst));
-	 brw_CONT(p, if_depth_in_loop[loop_depth]);
+	 if (intel->gen >= 6) {
+	    brw_CONT_gen6(p, loop_inst[loop_depth - 1]);
+	 } else {
+	    brw_CONT(p, if_depth_in_loop[loop_depth]);
+	 }
          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
          break;
-      case OPCODE_ENDLOOP: 
-         {
-	    clear_current_const(c);
-            struct brw_instruction *inst0, *inst1;
-	    GLuint br = 1;
-
-            loop_depth--;
-
-	    if (intel->gen == 5)
-	       br = 2;
-
-            inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
-            /* patch all the BREAK/CONT instructions from last BEGINLOOP */
-            while (inst0 > loop_inst[loop_depth]) {
-               inst0--;
-               if (inst0->header.opcode == BRW_OPCODE_BREAK &&
+
+      case OPCODE_ENDLOOP: {
+	 clear_current_const(c);
+	 struct brw_instruction *inst0, *inst1;
+	 GLuint br = 1;
+
+	 loop_depth--;
+
+	 if (intel->gen == 5)
+	    br = 2;
+
+	 inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
+
+	 if (intel->gen < 6) {
+	    /* patch all the BREAK/CONT instructions from last BEGINLOOP */
+	    while (inst0 > loop_inst[loop_depth]) {
+	       inst0--;
+	       if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 		   inst0->bits3.if_else.jump_count == 0) {
-                  inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
-               }
-               else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
-			inst0->bits3.if_else.jump_count == 0) {
-                  inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
-               }
-            }
-         }
+		  inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
+	       } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
+			  inst0->bits3.if_else.jump_count == 0) {
+		  inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
+	       }
+	    }
+	 }
+      }
          break;
+
       case OPCODE_BRA:
 	 brw_set_predicate_control(p, get_predicate(inst));
          brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
@@ -2088,6 +2226,7 @@ void brw_vs_emit(struct brw_vs_compile *c )
    }
 
    brw_resolve_cals(p);
+   brw_set_uip_jip(p);
 
    brw_optimize(p);
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index a6d2a2377f..656501b4f7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -119,6 +119,62 @@ brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
    brw_wm_emit(c);
 }
 
+static void
+brw_wm_payload_setup(struct brw_context *brw,
+		     struct brw_wm_compile *c)
+{
+   struct intel_context *intel = &brw->intel;
+   bool uses_depth = (c->fp->program.Base.InputsRead &
+		      (1 << FRAG_ATTRIB_WPOS)) != 0;
+
+   if (intel->gen >= 6) {
+      /* R0-1: masks, pixel X/Y coordinates. */
+      c->nr_payload_regs = 2;
+      /* R2: only for 32-pixel dispatch.*/
+      /* R3-4: perspective pixel location barycentric */
+      c->nr_payload_regs += 2;
+      /* R5-6: perspective pixel location bary for dispatch width != 8 */
+      if (c->dispatch_width == 16) {
+	 c->nr_payload_regs += 2;
+      }
+      /* R7-10: perspective centroid barycentric */
+      /* R11-14: perspective sample barycentric */
+      /* R15-18: linear pixel location barycentric */
+      /* R19-22: linear centroid barycentric */
+      /* R23-26: linear sample barycentric */
+
+      /* R27: interpolated depth if uses source depth */
+      if (uses_depth) {
+	 c->source_depth_reg = c->nr_payload_regs;
+	 c->nr_payload_regs++;
+	 if (c->dispatch_width == 16) {
+	    /* R28: interpolated depth if not 8-wide. */
+	    c->nr_payload_regs++;
+	 }
+      }
+      /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
+       */
+      if (uses_depth) {
+	 c->source_w_reg = c->nr_payload_regs;
+	 c->nr_payload_regs++;
+	 if (c->dispatch_width == 16) {
+	    /* R30: interpolated W if not 8-wide. */
+	    c->nr_payload_regs++;
+	 }
+      }
+      /* R31: MSAA position offsets. */
+      /* R32-: bary for 32-pixel. */
+      /* R58-59: interp W for 32-pixel. */
+
+      if (c->fp->program.Base.OutputsWritten &
+	  BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+	 c->source_depth_to_render_target = GL_TRUE;
+	 c->computes_depth = GL_TRUE;
+      }
+   } else {
+      brw_wm_lookup_iz(intel, c);
+   }
+}
 
 /**
  * All Mesa program -> GPU code generation goes through this function.
@@ -167,23 +223,18 @@ static void do_wm_prog( struct brw_context *brw,
 
    brw_init_compile(brw, &c->func);
 
-   /* temporary sanity check assertion */
-   ASSERT(fp->isGLSL == brw_wm_is_glsl(&c->fp->program));
+   brw_wm_payload_setup(brw, c);
 
    if (!brw_wm_fs_emit(brw, c)) {
       /*
        * Shader which use GLSL features such as flow control are handled
        * differently from "simple" shaders.
        */
-      if (fp->isGLSL) {
-	 c->dispatch_width = 8;
-	 brw_wm_glsl_emit(brw, c);
-      }
-      else {
-	 c->dispatch_width = 16;
-	 brw_wm_non_glsl_emit(brw, c);
-      }
+      c->dispatch_width = 16;
+      brw_wm_payload_setup(brw, c);
+      brw_wm_non_glsl_emit(brw, c);
    }
+   c->prog_data.dispatch_width = c->dispatch_width;
 
    /* Scratch space is used for register spilling */
    if (c->last_scratch) {
@@ -220,12 +271,10 @@ static void do_wm_prog( struct brw_context *brw,
 static void brw_wm_populate_key( struct brw_context *brw,
 				 struct brw_wm_prog_key *key )
 {
-   struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &brw->intel.ctx;
    /* BRW_NEW_FRAGMENT_PROGRAM */
    const struct brw_fragment_program *fp = 
       (struct brw_fragment_program *)brw->fragment_program;
-   GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
    GLuint lookup = 0;
    GLuint line_aa;
    GLuint i;
@@ -285,57 +334,9 @@ static void brw_wm_populate_key( struct brw_context *brw,
       }
    }
 
-   if (intel->gen >= 6) {
-      /* R0-1: masks, pixel X/Y coordinates. */
-      key->nr_payload_regs = 2;
-      /* R2: only for 32-pixel dispatch.*/
-      /* R3-4: perspective pixel location barycentric */
-      key->nr_payload_regs += 2;
-      /* R5-6: perspective pixel location bary for dispatch width != 8 */
-      if (!fp->isGLSL) { /* dispatch_width != 8 */
-	 key->nr_payload_regs += 2;
-      }
-      /* R7-10: perspective centroid barycentric */
-      /* R11-14: perspective sample barycentric */
-      /* R15-18: linear pixel location barycentric */
-      /* R19-22: linear centroid barycentric */
-      /* R23-26: linear sample barycentric */
-
-      /* R27: interpolated depth if uses source depth */
-      if (uses_depth) {
-	 key->source_depth_reg = key->nr_payload_regs;
-	 key->nr_payload_regs++;
-	 if (!fp->isGLSL) { /* dispatch_width != 8 */
-	    /* R28: interpolated depth if not 8-wide. */
-	    key->nr_payload_regs++;
-	 }
-      }
-      /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W.
-       */
-      if (uses_depth) {
-	 key->source_w_reg = key->nr_payload_regs;
-	 key->nr_payload_regs++;
-	 if (!fp->isGLSL) { /* dispatch_width != 8 */
-	    /* R30: interpolated W if not 8-wide. */
-	    key->nr_payload_regs++;
-	 }
-      }
-      /* R31: MSAA position offsets. */
-      /* R32-: bary for 32-pixel. */
-      /* R58-59: interp W for 32-pixel. */
-
-      if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
-	 key->source_depth_to_render_target = GL_TRUE;
-	 key->computes_depth = GL_TRUE;
-      }
-
-   } else {
-      brw_wm_lookup_iz(intel,
-	      	       line_aa,
-		       lookup,
-		       uses_depth,
-		       key);
-   }
+   key->iz_lookup = lookup;
+   key->line_aa = line_aa;
+   key->stats_wm = brw->intel.stats_wm;
 
    /* BRW_NEW_WM_INPUT_DIMENSIONS */
    key->proj_attrib_mask = brw->wm.input_size_masks[4-1];
@@ -377,6 +378,10 @@ static void brw_wm_populate_key( struct brw_context *brw,
 	       swizzles[2] = SWIZZLE_ZERO;
 	    } else if (t->DepthMode == GL_LUMINANCE) {
 	       swizzles[3] = SWIZZLE_ONE;
+	    } else if (t->DepthMode == GL_RED) {
+	       swizzles[1] = SWIZZLE_ZERO;
+	       swizzles[2] = SWIZZLE_ZERO;
+	       swizzles[3] = SWIZZLE_ZERO;
 	    }
 	 }
 
@@ -423,6 +428,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
     */
    if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) {
       key->drawable_height = ctx->DrawBuffer->Height;
+      key->render_to_fbo = ctx->DrawBuffer->Name != 0;
    }
 
    key->nr_color_regions = brw->state.nr_color_regions;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 99bd15c187..e7f3cfbb75 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -59,18 +59,12 @@
 #define AA_ALWAYS    2
 
 struct brw_wm_prog_key {
-   GLuint source_depth_reg:3;
-   GLuint source_w_reg:3;
-   GLuint aa_dest_stencil_reg:3;
-   GLuint dest_depth_reg:3;
-   GLuint nr_payload_regs:4;
-   GLuint computes_depth:1;	/* could be derived from program string */
-   GLuint source_depth_to_render_target:1;
+   GLuint stats_wm:1;
    GLuint flat_shade:1;
    GLuint linear_color:1;  /**< linear interpolation vs perspective interp */
-   GLuint runtime_check_aads_emit:1;
    GLuint nr_color_regions:5;
-   
+   GLuint render_to_fbo:1;
+
    GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */
    GLuint shadowtex_mask:16;
    GLuint yuvtex_mask:16;
@@ -80,6 +74,8 @@ struct brw_wm_prog_key {
 
    GLushort drawable_height;
    GLbitfield64 vp_outputs_written;
+   GLuint iz_lookup;
+   GLuint line_aa;
    GLuint program_string_id:32;
 };
 
@@ -203,6 +199,15 @@ struct brw_wm_compile {
       PASS2_DONE
    } state;
 
+   GLuint source_depth_reg:3;
+   GLuint source_w_reg:3;
+   GLuint aa_dest_stencil_reg:3;
+   GLuint dest_depth_reg:3;
+   GLuint nr_payload_regs:4;
+   GLuint computes_depth:1;	/* could be derived from program string */
+   GLuint source_depth_to_render_target:1;
+   GLuint runtime_check_aads_emit:1;
+
    /* Initial pass - translate fp instructions to fp instructions,
     * simplifying and adding instructions for interpolation and
     * framebuffer writes.
@@ -305,14 +310,9 @@ void brw_wm_print_insn( struct brw_wm_compile *c,
 void brw_wm_print_program( struct brw_wm_compile *c,
 			   const char *stage );
 
-void brw_wm_lookup_iz( struct intel_context *intel,
-		       GLuint line_aa,
-		       GLuint lookup,
-		       GLboolean ps_uses_depth,
-		       struct brw_wm_prog_key *key );
+void brw_wm_lookup_iz(struct intel_context *intel,
+		      struct brw_wm_compile *c);
 
-GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
-void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c);
 GLboolean brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c);
 
 /* brw_wm_emit.c */
@@ -380,7 +380,6 @@ void emit_fb_write(struct brw_wm_compile *c,
 void emit_frontfacing(struct brw_compile *p,
 		      const struct brw_reg *dst,
 		      GLuint mask);
-void emit_kil_nv(struct brw_wm_compile *c);
 void emit_linterp(struct brw_compile *p,
 		  const struct brw_reg *dst,
 		  GLuint mask,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 96fecc97ee..be86e0e128 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -219,43 +219,45 @@ void emit_wpos_xy(struct brw_wm_compile *c,
 		  const struct brw_reg *arg0)
 {
    struct brw_compile *p = &c->func;
+   struct intel_context *intel = &p->brw->intel;
+   struct brw_reg delta_x = retype(arg0[0], BRW_REGISTER_TYPE_W);
+   struct brw_reg delta_y = retype(arg0[1], BRW_REGISTER_TYPE_W);
 
    if (mask & WRITEMASK_X) {
+      if (intel->gen >= 6) {
+	 struct brw_reg delta_x_f = retype(delta_x, BRW_REGISTER_TYPE_F);
+	 brw_MOV(p, delta_x_f, delta_x);
+	 delta_x = delta_x_f;
+      }
+
       if (c->fp->program.PixelCenterInteger) {
 	 /* X' = X */
-	 brw_MOV(p,
-		 dst[0],
-		 retype(arg0[0], BRW_REGISTER_TYPE_W));
+	 brw_MOV(p, dst[0], delta_x);
       } else {
 	 /* X' = X + 0.5 */
-	 brw_ADD(p,
-		 dst[0],
-		 retype(arg0[0], BRW_REGISTER_TYPE_W),
-		 brw_imm_f(0.5));
+	 brw_ADD(p, dst[0], delta_x, brw_imm_f(0.5));
       }
    }
 
    if (mask & WRITEMASK_Y) {
+      if (intel->gen >= 6) {
+	 struct brw_reg delta_y_f = retype(delta_y, BRW_REGISTER_TYPE_F);
+	 brw_MOV(p, delta_y_f, delta_y);
+	 delta_y = delta_y_f;
+      }
+
       if (c->fp->program.OriginUpperLeft) {
 	 if (c->fp->program.PixelCenterInteger) {
 	    /* Y' = Y */
-	    brw_MOV(p,
-		    dst[1],
-		    retype(arg0[1], BRW_REGISTER_TYPE_W));
+	    brw_MOV(p, dst[1], delta_y);
 	 } else {
-	    /* Y' = Y + 0.5 */
-	    brw_ADD(p,
-		    dst[1],
-		    retype(arg0[1], BRW_REGISTER_TYPE_W),
-		    brw_imm_f(0.5));
+	    brw_ADD(p, dst[1], delta_y, brw_imm_f(0.5));
 	 }
       } else {
 	 float center_offset = c->fp->program.PixelCenterInteger ? 0.0 : 0.5;
 
 	 /* Y' = (height - 1) - Y + center */
-	 brw_ADD(p,
-		 dst[1],
-		 negate(retype(arg0[1], BRW_REGISTER_TYPE_W)),
+	 brw_ADD(p, dst[1], negate(delta_y),
 		 brw_imm_f(c->key.drawable_height - 1 + center_offset));
       }
    }
@@ -896,10 +898,14 @@ void emit_math1(struct brw_wm_compile *c,
 		      BRW_MATH_SATURATE_NONE);
    struct brw_reg src;
 
-   if (intel->gen >= 6 && (arg0[0].hstride == BRW_HORIZONTAL_STRIDE_0 ||
-			   arg0[0].file != BRW_GENERAL_REGISTER_FILE)) {
+   if (intel->gen >= 6 && ((arg0[0].hstride == BRW_HORIZONTAL_STRIDE_0 ||
+			    arg0[0].file != BRW_GENERAL_REGISTER_FILE) ||
+			   arg0[0].negate || arg0[0].abs)) {
       /* Gen6 math requires that source and dst horizontal stride be 1,
        * and that the argument be in the GRF.
+       *
+       * The hardware ignores source modifiers (negate and abs) on math
+       * instructions, so we also move to a temp to set those up.
        */
       src = dst[dst_chan];
       brw_MOV(p, src, arg0[0]);
@@ -967,34 +973,23 @@ void emit_math2(struct brw_wm_compile *c,
       struct brw_reg temp_dst = dst[dst_chan];
 
       if (arg0[0].hstride == BRW_HORIZONTAL_STRIDE_0) {
-	 if (arg1[0].hstride == BRW_HORIZONTAL_STRIDE_0) {
-	    /* Both scalar arguments.  Do scalar calc. */
-	    src0.hstride = BRW_HORIZONTAL_STRIDE_1;
-	    src1.hstride = BRW_HORIZONTAL_STRIDE_1;
-	    temp_dst.hstride = BRW_HORIZONTAL_STRIDE_1;
-	    temp_dst.width = BRW_WIDTH_1;
-
-	    if (arg0[0].subnr != 0) {
-	       brw_MOV(p, temp_dst, src0);
-	       src0 = temp_dst;
-
-	       /* Ouch.  We've used the temp as a dst, and we still
-		* need a temp to store arg1 in, because src and dst
-		* offsets have to be equal.  Leaving this up to
-		* glsl2-965 to handle correctly.
-		*/
-	       assert(arg1[0].subnr == 0);
-	    } else if (arg1[0].subnr != 0) {
-	       brw_MOV(p, temp_dst, src1);
-	       src1 = temp_dst;
-	    }
-	 } else {
-	    brw_MOV(p, temp_dst, src0);
-	    src0 = temp_dst;
-	 }
-      } else if (arg1[0].hstride == BRW_HORIZONTAL_STRIDE_0) {
-	 brw_MOV(p, temp_dst, src1);
-	 src1 = temp_dst;
+	 brw_MOV(p, temp_dst, src0);
+	 src0 = temp_dst;
+      }
+
+      if (arg1[0].hstride == BRW_HORIZONTAL_STRIDE_0) {
+	 /* This is a heinous hack to get a temporary register for use
+	  * in case both arg0 and arg1 are constants.  Why you're
+	  * doing exponentiation on constant values in the shader, we
+	  * don't know.
+	  *
+	  * max_wm_grf is almost surely less than the maximum GRF, and
+	  * gen6 doesn't care about the number of GRFs used in a
+	  * shader like pre-gen6 did.
+	  */
+	 struct brw_reg temp = brw_vec8_grf(c->max_wm_grf, 0);
+	 brw_MOV(p, temp, src1);
+	 src1 = temp;
       }
 
       brw_set_saturate(p, (mask & SATURATE) ? 1 : 0);
@@ -1012,14 +1007,6 @@ void emit_math2(struct brw_wm_compile *c,
 		   sechalf(src0),
 		   sechalf(src1));
       }
-
-      /* Splat a scalar result into all the channels. */
-      if (arg0[0].hstride == BRW_HORIZONTAL_STRIDE_0 &&
-	  arg1[0].hstride == BRW_HORIZONTAL_STRIDE_0) {
-	 temp_dst.hstride = BRW_HORIZONTAL_STRIDE_0;
-	 temp_dst.vstride = BRW_VERTICAL_STRIDE_0;
-	 brw_MOV(p, dst[dst_chan], temp_dst);
-      }
    } else {
       GLuint saturate = ((mask & SATURATE) ?
 			 BRW_MATH_SATURATE_SATURATE :
@@ -1301,9 +1288,15 @@ static void emit_kil( struct brw_wm_compile *c,
 		      struct brw_reg *arg0)
 {
    struct brw_compile *p = &c->func;
-   struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
+   struct intel_context *intel = &p->brw->intel;
+   struct brw_reg pixelmask;
    GLuint i, j;
 
+   if (intel->gen >= 6)
+      pixelmask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
+   else
+      pixelmask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
+
    for (i = 0; i < 4; i++) {
       /* Check if we've already done the comparison for this reg
        * -- common when someone does KIL TEMP.wwww.
@@ -1319,26 +1312,11 @@ static void emit_kil( struct brw_wm_compile *c,
       brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0));   
       brw_set_predicate_control_flag_value(p, 0xff);
       brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-      brw_AND(p, r0uw, brw_flag_reg(), r0uw);
+      brw_AND(p, pixelmask, brw_flag_reg(), pixelmask);
       brw_pop_insn_state(p);
    }
 }
 
-/* KIL_NV kills the pixels that are currently executing, not based on a test
- * of the arguments.
- */
-void emit_kil_nv( struct brw_wm_compile *c )
-{
-   struct brw_compile *p = &c->func;
-   struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
-
-   brw_push_insn_state(p);
-   brw_set_mask_control(p, BRW_MASK_DISABLE);
-   brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */
-   brw_AND(p, r0uw, c->emit_mask_reg, r0uw);
-   brw_pop_insn_state(p);
-}
-
 static void fire_fb_write( struct brw_wm_compile *c,
 			   GLuint base_reg,
 			   GLuint nr,
@@ -1387,8 +1365,8 @@ static void emit_aa( struct brw_wm_compile *c,
 		     GLuint reg )
 {
    struct brw_compile *p = &c->func;
-   GLuint comp = c->key.aa_dest_stencil_reg / 2;
-   GLuint off = c->key.aa_dest_stencil_reg % 2;
+   GLuint comp = c->aa_dest_stencil_reg / 2;
+   GLuint off = c->aa_dest_stencil_reg % 2;
    struct brw_reg aa = offset(arg1[comp], off);
 
    brw_push_insn_state(p);
@@ -1416,11 +1394,10 @@ void emit_fb_write(struct brw_wm_compile *c,
    struct intel_context *intel = &brw->intel;
    GLuint nr = 2;
    GLuint channel;
-   int base_reg; /* For gen6 fb write with no header, starting from color payload directly!. */
 
    /* Reserve a space for AA - may not be needed:
     */
-   if (c->key.aa_dest_stencil_reg)
+   if (c->aa_dest_stencil_reg)
       nr += 1;
 
    /* I don't really understand how this achieves the color interleave
@@ -1428,11 +1405,6 @@ void emit_fb_write(struct brw_wm_compile *c,
     */
    brw_push_insn_state(p);
 
-   if (intel->gen >= 6)
-	base_reg = nr;
-   else
-	base_reg = 0;
-
    for (channel = 0; channel < 4; channel++) {
       if (intel->gen >= 6) {
 	 /* gen6 SIMD16 single source DP write looks like:
@@ -1493,9 +1465,9 @@ void emit_fb_write(struct brw_wm_compile *c,
 
    brw_pop_insn_state(p);
 
-   if (c->key.source_depth_to_render_target)
+   if (c->source_depth_to_render_target)
    {
-      if (c->key.computes_depth) 
+      if (c->computes_depth)
 	 brw_MOV(p, brw_message_reg(nr), arg2[2]);
       else 
 	 brw_MOV(p, brw_message_reg(nr), arg1[1]); /* ? */
@@ -1503,10 +1475,10 @@ void emit_fb_write(struct brw_wm_compile *c,
       nr += 2;
    }
 
-   if (c->key.dest_depth_reg)
+   if (c->dest_depth_reg)
    {
-      GLuint comp = c->key.dest_depth_reg / 2;
-      GLuint off = c->key.dest_depth_reg % 2;
+      GLuint comp = c->dest_depth_reg / 2;
+      GLuint off = c->dest_depth_reg % 2;
 
       if (off != 0) {
          brw_push_insn_state(p);
@@ -1524,15 +1496,27 @@ void emit_fb_write(struct brw_wm_compile *c,
    }
 
    if (intel->gen >= 6) {
-      /* Subtract off the message header, since we send headerless. */
-      nr -= 2;
+      /* Load the message header.  There's no implied move from src0
+       * to the base mrf on gen6.
+       */
+      brw_push_insn_state(p);
+      brw_set_mask_control(p, BRW_MASK_DISABLE);
+      brw_MOV(p, brw_message_reg(0), brw_vec8_grf(0, 0));
+      brw_pop_insn_state(p);
+
+      if (target != 0) {
+	 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
+					0,
+					2), BRW_REGISTER_TYPE_UD),
+		 brw_imm_ud(target));
+      }
    }
 
-   if (!c->key.runtime_check_aads_emit) {
-      if (c->key.aa_dest_stencil_reg)
+   if (!c->runtime_check_aads_emit) {
+      if (c->aa_dest_stencil_reg)
 	 emit_aa(c, arg1, 2);
 
-      fire_fb_write(c, base_reg, nr, target, eot);
+      fire_fb_write(c, 0, nr, target, eot);
    }
    else {
       struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
@@ -1897,10 +1881,6 @@ void brw_wm_emit( struct brw_wm_compile *c )
 	 emit_kil(c, args[0]);
 	 break;
 
-      case OPCODE_KIL_NV:
-	 emit_kil_nv(c);
-	 break;
-
       default:
 	 printf("Unsupported opcode %i (%s) in fragment shader\n",
 		inst->opcode, inst->opcode < MAX_OPCODE ?
diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index 2cae698880..4759b289a0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -338,11 +338,13 @@ static struct prog_src_register get_delta_xy( struct brw_wm_compile *c )
 
 static struct prog_src_register get_pixel_w( struct brw_wm_compile *c )
 {
-   /* This is only called for producing 1/w in pre-gen6 interp.  for
-    * gen6, the interp opcodes don't use this argument.
+   /* This is called for producing 1/w in pre-gen6 interp.  for gen6,
+    * the interp opcodes don't use this argument.  But to keep the
+    * nr_args = 3 expectations of pinterp happy, just stuff delta_xy
+    * into the slot.
     */
    if (c->func.brw->intel.gen >= 6)
-      return src_undef();
+      return c->delta_xy;
 
    if (src_is_undef(c->pixel_w)) {
       struct prog_dst_register pixel_w = get_temp(c);
@@ -373,11 +375,7 @@ static void emit_interp( struct brw_wm_compile *c,
    struct prog_src_register interp = src_reg(PROGRAM_PAYLOAD, idx);
    struct prog_src_register deltas;
 
-   if (c->func.brw->intel.gen < 6) {
-      deltas = get_delta_xy(c);
-   } else {
-      deltas = src_undef();
-   }
+   deltas = get_delta_xy(c);
 
    /* Need to use PINTERP on attributes which have been
     * multiplied by 1/W in the SF program, and LINTERP on those
@@ -1133,6 +1131,11 @@ void brw_wm_pass_fp( struct brw_wm_compile *c )
 	 precalc_lit(c, inst);
 	 break;
 
+      case OPCODE_RSQ:
+	 out = emit_scalar_insn(c, inst);
+	 out->SrcReg[0].Abs = GL_TRUE;
+	 break;
+
       case OPCODE_TEX:
 	 precalc_tex(c, inst);
 	 break;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c
deleted file mode 100644
index 7fe8ab1f33..0000000000
--- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c
+++ /dev/null
@@ -1,1035 +0,0 @@
-#include "main/macros.h"
-#include "program/prog_parameter.h"
-#include "program/prog_print.h"
-#include "program/prog_optimize.h"
-#include "brw_context.h"
-#include "brw_eu.h"
-#include "brw_wm.h"
-
-static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
-                                  const struct prog_instruction *inst,
-                                  GLuint component);
-
-/**
- * Determine if the given fragment program uses GLSL features such
- * as flow conditionals, loops, subroutines.
- * Some GLSL shaders may use these features, others might not.
- */
-GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
-{
-    int i;
-
-    if (unlikely(INTEL_DEBUG & DEBUG_GLSL_FORCE))
-       return GL_TRUE;
-
-    for (i = 0; i < fp->Base.NumInstructions; i++) {
-	const struct prog_instruction *inst = &fp->Base.Instructions[i];
-	switch (inst->Opcode) {
-	    case OPCODE_ARL:
-	    case OPCODE_IF:
-	    case OPCODE_ENDIF:
-	    case OPCODE_CAL:
-	    case OPCODE_BRK:
-	    case OPCODE_RET:
-	    case OPCODE_BGNLOOP:
-		return GL_TRUE; 
-	    default:
-		break;
-	}
-    }
-    return GL_FALSE; 
-}
-
-
-
-static void
-reclaim_temps(struct brw_wm_compile *c);
-
-
-/** Mark GRF register as used. */
-static void
-prealloc_grf(struct brw_wm_compile *c, int r)
-{
-   c->used_grf[r] = GL_TRUE;
-}
-
-
-/** Mark given GRF register as not in use. */
-static void
-release_grf(struct brw_wm_compile *c, int r)
-{
-   /*assert(c->used_grf[r]);*/
-   c->used_grf[r] = GL_FALSE;
-   c->first_free_grf = MIN2(c->first_free_grf, r);
-}
-
-
-/** Return index of a free GRF, mark it as used. */
-static int
-alloc_grf(struct brw_wm_compile *c)
-{
-   GLuint r;
-   for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
-      if (!c->used_grf[r]) {
-         c->used_grf[r] = GL_TRUE;
-         c->first_free_grf = r + 1;  /* a guess */
-         return r;
-      }
-   }
-
-   /* no free temps, try to reclaim some */
-   reclaim_temps(c);
-   c->first_free_grf = 0;
-
-   /* try alloc again */
-   for (r = c->first_free_grf; r < BRW_WM_MAX_GRF; r++) {
-      if (!c->used_grf[r]) {
-         c->used_grf[r] = GL_TRUE;
-         c->first_free_grf = r + 1;  /* a guess */
-         return r;
-      }
-   }
-
-   for (r = 0; r < BRW_WM_MAX_GRF; r++) {
-      assert(c->used_grf[r]);
-   }
-
-   /* really, no free GRF regs found */
-   if (!c->out_of_regs) {
-      /* print warning once per compilation */
-      _mesa_warning(NULL, "i965: ran out of registers for fragment program");
-      c->out_of_regs = GL_TRUE;
-   }
-
-   return -1;
-}
-
-
-/** Return number of GRF registers used */
-static int
-num_grf_used(const struct brw_wm_compile *c)
-{
-   int r;
-   for (r = BRW_WM_MAX_GRF - 1; r >= 0; r--)
-      if (c->used_grf[r])
-         return r + 1;
-   return 0;
-}
-
-
-
-/**
- * Record the mapping of a Mesa register to a hardware register.
- */
-static void set_reg(struct brw_wm_compile *c, int file, int index, 
-	int component, struct brw_reg reg)
-{
-    c->wm_regs[file][index][component].reg = reg;
-    c->wm_regs[file][index][component].inited = GL_TRUE;
-}
-
-static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
-{
-    struct brw_reg reg;
-
-    /* if we need to allocate another temp, grow the tmp_regs[] array */
-    if (c->tmp_index == c->tmp_max) {
-       int r = alloc_grf(c);
-       if (r < 0) {
-          /*printf("Out of temps in %s\n", __FUNCTION__);*/
-          r = 50; /* XXX random register! */
-       }
-       c->tmp_regs[ c->tmp_max++ ] = r;
-    }
-
-    /* form the GRF register */
-    reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0);
-    /*printf("alloc_temp %d\n", reg.nr);*/
-    assert(reg.nr < BRW_WM_MAX_GRF);
-    return reg;
-
-}
-
-/**
- * Save current temp register info.
- * There must be a matching call to release_tmps().
- */
-static int mark_tmps(struct brw_wm_compile *c)
-{
-    return c->tmp_index;
-}
-
-static void release_tmps(struct brw_wm_compile *c, int mark)
-{
-    c->tmp_index = mark;
-}
-
-/**
- * Convert Mesa src register to brw register.
- *
- * Since we're running in SOA mode each Mesa register corresponds to four
- * hardware registers.  We allocate the hardware registers as needed here.
- *
- * \param file  register file, one of PROGRAM_x
- * \param index  register number
- * \param component  src component (X=0, Y=1, Z=2, W=3)
- * \param nr  not used?!?
- * \param neg  negate value?
- * \param abs  take absolute value?
- */
-static struct brw_reg 
-get_reg(struct brw_wm_compile *c, int file, int index, int component,
-        int nr, GLuint neg, GLuint abs)
-{
-    struct brw_reg reg;
-    switch (file) {
-	case PROGRAM_STATE_VAR:
-	case PROGRAM_CONSTANT:
-	case PROGRAM_UNIFORM:
-	    file = PROGRAM_STATE_VAR;
-	    break;
-	case PROGRAM_UNDEFINED:
-	    return brw_null_reg();	
-	case PROGRAM_TEMPORARY:
-	case PROGRAM_INPUT:
-	case PROGRAM_OUTPUT:
-	case PROGRAM_PAYLOAD:
-	    break;
-	default:
-	    _mesa_problem(NULL, "Unexpected file in get_reg()");
-	    return brw_null_reg();
-    }
-
-    assert(index < 256);
-    assert(component < 4);
-
-    /* see if we've already allocated a HW register for this Mesa register */
-    if (c->wm_regs[file][index][component].inited) {
-       /* yes, re-use */
-       reg = c->wm_regs[file][index][component].reg;
-    }
-    else {
-	/* no, allocate new register */
-       int grf = alloc_grf(c);
-       /*printf("alloc grf %d for reg %d:%d.%d\n", grf, file, index, component);*/
-       if (grf < 0) {
-          /* totally out of temps */
-          grf = 51; /* XXX random register! */
-       }
-
-       reg = brw_vec8_grf(grf, 0);
-       /*printf("Alloc new grf %d for %d.%d\n", reg.nr, index, component);*/
-
-       set_reg(c, file, index, component, reg);
-    }
-
-    if (neg & (1 << component)) {
-	reg = negate(reg);
-    }
-    if (abs)
-	reg = brw_abs(reg);
-    return reg;
-}
-
-
-
-/**
- * This is called if we run out of GRF registers.  Examine the live intervals
- * of temp regs in the program and free those which won't be used again.
- */
-static void
-reclaim_temps(struct brw_wm_compile *c)
-{
-   GLint intBegin[MAX_PROGRAM_TEMPS];
-   GLint intEnd[MAX_PROGRAM_TEMPS];
-   int index;
-
-   /*printf("Reclaim temps:\n");*/
-
-   _mesa_find_temp_intervals(c->prog_instructions, c->nr_fp_insns,
-                             intBegin, intEnd);
-
-   for (index = 0; index < MAX_PROGRAM_TEMPS; index++) {
-      if (intEnd[index] != -1 && intEnd[index] < c->cur_inst) {
-         /* program temp[i] can be freed */
-         int component;
-         /*printf("  temp[%d] is dead\n", index);*/
-         for (component = 0; component < 4; component++) {
-            if (c->wm_regs[PROGRAM_TEMPORARY][index][component].inited) {
-               int r = c->wm_regs[PROGRAM_TEMPORARY][index][component].reg.nr;
-               release_grf(c, r);
-               /*
-               printf("  Reclaim temp %d, reg %d at inst %d\n",
-                      index, r, c->cur_inst);
-               */
-               c->wm_regs[PROGRAM_TEMPORARY][index][component].inited = GL_FALSE;
-            }
-         }
-      }
-   }
-}
-
-
-
-
-/**
- * Preallocate registers.  This sets up the Mesa to hardware register
- * mapping for certain registers, such as constants (uniforms/state vars)
- * and shader inputs.
- */
-static void prealloc_reg(struct brw_wm_compile *c)
-{
-    struct intel_context *intel = &c->func.brw->intel;
-    int i, j;
-    struct brw_reg reg;
-    int urb_read_length = 0;
-    GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted;
-    GLuint reg_index = 0;
-
-    memset(c->used_grf, GL_FALSE, sizeof(c->used_grf));
-    c->first_free_grf = 0;
-
-    for (i = 0; i < 4; i++) {
-	if (i < (c->key.nr_payload_regs + 1) / 2)
-            reg = brw_vec8_grf(i * 2, 0);
-        else
-            reg = brw_vec8_grf(0, 0);
-	set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
-    }
-    set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_W, 0,
-	    brw_vec8_grf(c->key.source_w_reg, 0));
-    reg_index += c->key.nr_payload_regs;
-
-    /* constants */
-    {
-        const GLuint nr_params = c->fp->program.Base.Parameters->NumParameters;
-        const GLuint nr_temps = c->fp->program.Base.NumTemporaries;
-
-        /* use a real constant buffer, or just use a section of the GRF? */
-        /* XXX this heuristic may need adjustment... */
-        if ((nr_params + nr_temps) * 4 + reg_index > 80) {
-	   for (i = 0; i < nr_params; i++) {
-	      float *pv = c->fp->program.Base.Parameters->ParameterValues[i];
-	      for (j = 0; j < 4; j++) {
-		 c->prog_data.pull_param[c->prog_data.nr_pull_params] = &pv[j];
-		 c->prog_data.nr_pull_params++;
-	      }
-	   }
-
-	   c->prog_data.nr_params = 0;
-	}
-        /*printf("WM use_const_buffer = %d\n", c->fp->use_const_buffer);*/
-
-        if (!c->prog_data.nr_pull_params) {
-           const struct gl_program_parameter_list *plist = 
-              c->fp->program.Base.Parameters;
-           int index = 0;
-
-           /* number of float constants in CURBE */
-           c->prog_data.nr_params = 4 * nr_params;
-
-           /* loop over program constants (float[4]) */
-           for (i = 0; i < nr_params; i++) {
-              /* loop over XYZW channels */
-              for (j = 0; j < 4; j++, index++) {
-                 reg = brw_vec1_grf(reg_index + index / 8, index % 8);
-                 /* Save pointer to parameter/constant value.
-                  * Constants will be copied in prepare_constant_buffer()
-                  */
-                 c->prog_data.param[index] = &plist->ParameterValues[i][j];
-                 set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
-              }
-           }
-           /* number of constant regs used (each reg is float[8]) */
-	   c->nr_creg = ALIGN(nr_params, 2) / 2;
-	   reg_index += c->nr_creg;
-        }
-    }
-
-    /* fragment shader inputs: One 2-reg pair of interpolation
-     * coefficients for each vec4 to be set up.
-     */
-    if (intel->gen >= 6) {
-       for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
-	  if (!(c->fp->program.Base.InputsRead & BITFIELD64_BIT(i)))
-	     continue;
-
-	  reg = brw_vec8_grf(reg_index, 0);
-	  for (j = 0; j < 4; j++) {
-	     set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
-	  }
-	  reg_index += 2;
-       }
-       urb_read_length = reg_index;
-    } else {
-       for (i = 0; i < VERT_RESULT_MAX; i++) {
-	  int fp_input;
-
-	  if (i >= VERT_RESULT_VAR0)
-	     fp_input = i - VERT_RESULT_VAR0 + FRAG_ATTRIB_VAR0;
-	  else if (i <= VERT_RESULT_TEX7)
-	     fp_input = i;
-	  else
-	     fp_input = -1;
-
-	  if (fp_input >= 0 && inputs & (1 << fp_input)) {
-	     urb_read_length = reg_index;
-	     reg = brw_vec8_grf(reg_index, 0);
-	     for (j = 0; j < 4; j++)
-		set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg);
-	  }
-	  if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
-	     reg_index += 2;
-	  }
-       }
-    }
-
-    c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
-    c->prog_data.urb_read_length = urb_read_length;
-    c->prog_data.curb_read_length = c->nr_creg;
-    c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
-    reg_index++;
-    c->stack =  brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, reg_index, 0);
-    reg_index += 2;
-
-    /* mark GRF regs [0..reg_index-1] as in-use */
-    for (i = 0; i < reg_index; i++)
-       prealloc_grf(c, i);
-
-    /* Don't use GRF 126, 127.  Using them seems to lead to GPU lock-ups */
-    prealloc_grf(c, 126);
-    prealloc_grf(c, 127);
-
-    for (i = 0; i < c->nr_fp_insns; i++) {
-	const struct prog_instruction *inst = &c->prog_instructions[i];
-	struct brw_reg dst[4];
-
-	switch (inst->Opcode) {
-	case OPCODE_TEX:
-	case OPCODE_TXB:
-	    /* Allocate the channels of texture results contiguously,
-	     * since they are written out that way by the sampler unit.
-	     */
-	    for (j = 0; j < 4; j++) {
-		dst[j] = get_dst_reg(c, inst, j);
-		if (j != 0)
-		    assert(dst[j].nr == dst[j - 1].nr + 1);
-	    }
-	    break;
-	default:
-	    break;
-	}
-    }
-
-    for (i = 0; i < c->nr_fp_insns; i++) {
-	const struct prog_instruction *inst = &c->prog_instructions[i];
-
-	switch (inst->Opcode) {
-	case WM_DELTAXY:
-	    /* Allocate WM_DELTAXY destination on G45/GM45 to an
-	     * even-numbered GRF if possible so that we can use the PLN
-	     * instruction.
-	     */
-	    if (inst->DstReg.WriteMask == WRITEMASK_XY &&
-		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][0].inited &&
-		!c->wm_regs[inst->DstReg.File][inst->DstReg.Index][1].inited &&
-		(IS_G4X(intel->intelScreen->deviceID) || intel->gen == 5)) {
-		int grf;
-
-		for (grf = c->first_free_grf & ~1;
-		     grf < BRW_WM_MAX_GRF;
-		     grf += 2)
-		{
-		    if (!c->used_grf[grf] && !c->used_grf[grf + 1]) {
-			c->used_grf[grf] = GL_TRUE;
-			c->used_grf[grf + 1] = GL_TRUE;
-			c->first_free_grf = grf + 2;  /* a guess */
-
-			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 0,
-				brw_vec8_grf(grf, 0));
-			set_reg(c, inst->DstReg.File, inst->DstReg.Index, 1,
-				brw_vec8_grf(grf + 1, 0));
-			break;
-		    }
-		}
-	    }
-	default:
-	    break;
-	}
-    }
-
-    /* An instruction may reference up to three constants.
-     * They'll be found in these registers.
-     * XXX alloc these on demand!
-     */
-    if (c->prog_data.nr_pull_params) {
-       for (i = 0; i < 3; i++) {
-          c->current_const[i].index = -1;
-          c->current_const[i].reg = brw_vec8_grf(alloc_grf(c), 0);
-       }
-    }
-#if 0
-    printf("USE CONST BUFFER? %d\n", c->fp->use_const_buffer);
-    printf("AFTER PRE_ALLOC, reg_index = %d\n", reg_index);
-#endif
-}
-
-
-/**
- * Check if any of the instruction's src registers are constants, uniforms,
- * or statevars.  If so, fetch any constants that we don't already have in
- * the three GRF slots.
- */
-static void fetch_constants(struct brw_wm_compile *c,
-                            const struct prog_instruction *inst)
-{
-   struct brw_compile *p = &c->func;
-   GLuint i;
-
-   /* loop over instruction src regs */
-   for (i = 0; i < 3; i++) {
-      const struct prog_src_register *src = &inst->SrcReg[i];
-      if (src->File == PROGRAM_STATE_VAR ||
-          src->File == PROGRAM_CONSTANT ||
-          src->File == PROGRAM_UNIFORM) {
-	 c->current_const[i].index = src->Index;
-
-#if 0
-	 printf("  fetch const[%d] for arg %d into reg %d\n",
-		src->Index, i, c->current_const[i].reg.nr);
-#endif
-
-	 /* need to fetch the constant now */
-	 brw_oword_block_read(p,
-			      c->current_const[i].reg,
-			      brw_message_reg(1),
-			      16 * src->Index,
-			      SURF_INDEX_FRAG_CONST_BUFFER);
-      }
-   }
-}
-
-
-/**
- * Convert Mesa dst register to brw register.
- */
-static struct brw_reg get_dst_reg(struct brw_wm_compile *c, 
-                                  const struct prog_instruction *inst,
-                                  GLuint component)
-{
-    const int nr = 1;
-    return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
-	    0, 0);
-}
-
-
-static struct brw_reg
-get_src_reg_const(struct brw_wm_compile *c,
-                  const struct prog_instruction *inst,
-                  GLuint srcRegIndex, GLuint component)
-{
-   /* We should have already fetched the constant from the constant
-    * buffer in fetch_constants().  Now we just have to return a
-    * register description that extracts the needed component and
-    * smears it across all eight vector components.
-    */
-   const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
-   struct brw_reg const_reg;
-
-   assert(component < 4);
-   assert(srcRegIndex < 3);
-   assert(c->current_const[srcRegIndex].index != -1);
-   const_reg = c->current_const[srcRegIndex].reg;
-
-   /* extract desired float from the const_reg, and smear */
-   const_reg = stride(const_reg, 0, 1, 0);
-   const_reg.subnr = component * 4;
-
-   if (src->Negate & (1 << component))
-      const_reg = negate(const_reg);
-   if (src->Abs)
-      const_reg = brw_abs(const_reg);
-
-#if 0
-   printf("  form const[%d].%d for arg %d, reg %d\n",
-          c->current_const[srcRegIndex].index,
-          component,
-          srcRegIndex,
-          const_reg.nr);
-#endif
-
-   return const_reg;
-}
-
-
-/**
- * Convert Mesa src register to brw register.
- */
-static struct brw_reg get_src_reg(struct brw_wm_compile *c, 
-                                  const struct prog_instruction *inst,
-                                  GLuint srcRegIndex, GLuint channel)
-{
-    const struct prog_src_register *src = &inst->SrcReg[srcRegIndex];
-    const GLuint nr = 1;
-    const GLuint component = GET_SWZ(src->Swizzle, channel);
-
-    /* Only one immediate value can be used per native opcode, and it
-     * has be in the src1 slot, so not all Mesa instructions will get
-     * to take advantage of immediate constants.
-     */
-    if (brw_wm_arg_can_be_immediate(inst->Opcode, srcRegIndex)) {
-       const struct gl_program_parameter_list *params;
-
-       params = c->fp->program.Base.Parameters;
-
-       /* Extended swizzle terms */
-       if (component == SWIZZLE_ZERO) {
-	  return brw_imm_f(0.0F);
-       } else if (component == SWIZZLE_ONE) {
-	  if (src->Negate)
-	     return brw_imm_f(-1.0F);
-	  else
-	     return brw_imm_f(1.0F);
-       }
-
-       if (src->File == PROGRAM_CONSTANT) {
-	  float f = params->ParameterValues[src->Index][component];
-
-	  if (src->Abs)
-	     f = fabs(f);
-	  if (src->Negate)
-	     f = -f;
-
-	  return brw_imm_f(f);
-       }
-    }
-
-    if (c->prog_data.nr_pull_params &&
-        (src->File == PROGRAM_STATE_VAR ||
-         src->File == PROGRAM_CONSTANT ||
-         src->File == PROGRAM_UNIFORM)) {
-       return get_src_reg_const(c, inst, srcRegIndex, component);
-    }
-    else {
-       /* other type of source register */
-       return get_reg(c, src->File, src->Index, component, nr, 
-                      src->Negate, src->Abs);
-    }
-}
-
-static void emit_arl(struct brw_wm_compile *c,
-                     const struct prog_instruction *inst)
-{
-    struct brw_compile *p = &c->func;
-    struct brw_reg src0, addr_reg;
-    brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
-    addr_reg = brw_uw8_reg(BRW_ARCHITECTURE_REGISTER_FILE, 
-                           BRW_ARF_ADDRESS, 0);
-    src0 = get_src_reg(c, inst, 0, 0); /* channel 0 */
-    brw_MOV(p, addr_reg, src0);
-    brw_set_saturate(p, 0);
-}
-
-static INLINE struct brw_reg high_words( struct brw_reg reg )
-{
-    return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_W ), 1 ),
-		   0, 8, 2 );
-}
-
-static INLINE struct brw_reg low_words( struct brw_reg reg )
-{
-    return stride( retype( reg, BRW_REGISTER_TYPE_W ), 0, 8, 2 );
-}
-
-static INLINE struct brw_reg even_bytes( struct brw_reg reg )
-{
-    return stride( retype( reg, BRW_REGISTER_TYPE_B ), 0, 16, 2 );
-}
-
-static INLINE struct brw_reg odd_bytes( struct brw_reg reg )
-{
-    return stride( suboffset( retype( reg, BRW_REGISTER_TYPE_B ), 1 ),
-		   0, 16, 2 );
-}
-
-/**
- * Resolve subroutine calls after code emit is done.
- */
-static void post_wm_emit( struct brw_wm_compile *c )
-{
-    brw_resolve_cals(&c->func);
-}
-
-static void
-get_argument_regs(struct brw_wm_compile *c,
-		  const struct prog_instruction *inst,
-		  int index,
-		  struct brw_reg *dst,
-		  struct brw_reg *regs,
-		  int mask)
-{
-    struct brw_compile *p = &c->func;
-    int i, j;
-
-    for (i = 0; i < 4; i++) {
-	if (mask & (1 << i)) {
-	    regs[i] = get_src_reg(c, inst, index, i);
-
-	    /* Unalias destination registers from our sources. */
-	    if (regs[i].file == BRW_GENERAL_REGISTER_FILE) {
-	       for (j = 0; j < 4; j++) {
-		   if (memcmp(&regs[i], &dst[j], sizeof(regs[0])) == 0) {
-		       struct brw_reg tmp = alloc_tmp(c);
-		       brw_MOV(p, tmp, regs[i]);
-		       regs[i] = tmp;
-		       break;
-		   }
-	       }
-	    }
-	}
-    }
-}
-
-static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
-{
-   struct intel_context *intel = &brw->intel;
-#define MAX_IF_DEPTH 32
-#define MAX_LOOP_DEPTH 32
-    struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH];
-    int if_depth_in_loop[MAX_LOOP_DEPTH];
-    GLuint i, if_depth = 0, loop_depth = 0;
-    struct brw_compile *p = &c->func;
-    struct brw_indirect stack_index = brw_indirect(0, 0);
-
-    c->out_of_regs = GL_FALSE;
-
-    if_depth_in_loop[loop_depth] = 0;
-
-    prealloc_reg(c);
-    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
-    brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
-
-    if (intel->gen >= 6)
-	brw_set_acc_write_control(p, 1);
-
-    for (i = 0; i < c->nr_fp_insns; i++) {
-        const struct prog_instruction *inst = &c->prog_instructions[i];
-	int dst_flags;
-	struct brw_reg args[3][4], dst[4];
-	int j;
-	int mark = mark_tmps( c );
-
-        c->cur_inst = i;
-
-#if 0
-        printf("Inst %d: ", i);
-        _mesa_print_instruction(inst);
-#endif
-
-        /* fetch any constants that this instruction needs */
-        if (c->prog_data.nr_pull_params)
-           fetch_constants(c, inst);
-
-	if (inst->Opcode != OPCODE_ARL) {
-	   for (j = 0; j < 4; j++) {
-	      if (inst->DstReg.WriteMask & (1 << j))
-		 dst[j] = get_dst_reg(c, inst, j);
-	      else
-		 dst[j] = brw_null_reg();
-	   }
-	}
-	for (j = 0; j < brw_wm_nr_args(inst->Opcode); j++)
-	    get_argument_regs(c, inst, j, dst, args[j], WRITEMASK_XYZW);
-
-	dst_flags = inst->DstReg.WriteMask;
-	if (inst->SaturateMode == SATURATE_ZERO_ONE)
-	    dst_flags |= SATURATE;
-
-	if (inst->CondUpdate)
-	    brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
-	else
-	    brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
-
-	switch (inst->Opcode) {
-	    case WM_PIXELXY:
-		emit_pixel_xy(c, dst, dst_flags);
-		break;
-	    case WM_DELTAXY: 
-		emit_delta_xy(p, dst, dst_flags, args[0]);
-		break;
-	    case WM_PIXELW:
-		emit_pixel_w(c, dst, dst_flags, args[0], args[1]);
-		break;	
-	    case WM_LINTERP:
-		emit_linterp(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case WM_PINTERP:
-		emit_pinterp(p, dst, dst_flags, args[0], args[1], args[2]);
-		break;
-	    case WM_CINTERP:
-		emit_cinterp(p, dst, dst_flags, args[0]);
-		break;
-	    case WM_WPOSXY:
-		emit_wpos_xy(c, dst, dst_flags, args[0]);
-		break;
-	    case WM_FB_WRITE:
-		emit_fb_write(c, args[0], args[1], args[2],
-			      INST_AUX_GET_TARGET(inst->Aux),
-			      inst->Aux & INST_AUX_EOT);
-		break;
-	    case WM_FRONTFACING:
-		emit_frontfacing(p, dst, dst_flags);
-		break;
-	    case OPCODE_ADD:
-		emit_alu2(p, brw_ADD, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_ARL:
-		emit_arl(c, inst);
-		break;
-	    case OPCODE_FRC:
-		emit_alu1(p, brw_FRC, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_FLR:
-		emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_LRP:
-		emit_lrp(p, dst, dst_flags, args[0], args[1], args[2]);
-		break;
-	    case OPCODE_TRUNC:
-		emit_alu1(p, brw_RNDZ, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_MOV:
-	    case OPCODE_SWZ:
-		emit_alu1(p, brw_MOV, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_DP2:
-		emit_dp2(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_DP3:
-		emit_dp3(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_DP4:
-		emit_dp4(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_XPD:
-		emit_xpd(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_DPH:
-		emit_dph(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_RCP:
-		emit_math1(c, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_RSQ:
-		emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_SIN:
-		emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_COS:
-		emit_math1(c, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_EX2:
-		emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_LG2:
-		emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_CMP:
-		emit_cmp(p, dst, dst_flags, args[0], args[1], args[2]);
-		break;
-	    case OPCODE_MIN:	
-		emit_min(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_MAX:	
-		emit_max(p, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_DDX:
-	    case OPCODE_DDY:
-		emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX),
-			  args[0]);
-                break;
-	    case OPCODE_SLT:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_L, args[0], args[1]);
-		break;
-	    case OPCODE_SLE:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_LE, args[0], args[1]);
-		break;
-	    case OPCODE_SGT:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_G, args[0], args[1]);
-		break;
-	    case OPCODE_SGE:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_GE, args[0], args[1]);
-		break;
-	    case OPCODE_SEQ:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_EQ, args[0], args[1]);
-		break;
-	    case OPCODE_SNE:
-		emit_sop(p, dst, dst_flags,
-			 BRW_CONDITIONAL_NEQ, args[0], args[1]);
-		break;
-	    case OPCODE_SSG:
-		emit_sign(p, dst, dst_flags, args[0]);
-		break;
-	    case OPCODE_MUL:
-		emit_alu2(p, brw_MUL, dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_POW:
-		emit_math2(c, BRW_MATH_FUNCTION_POW,
-			   dst, dst_flags, args[0], args[1]);
-		break;
-	    case OPCODE_MAD:
-		emit_mad(p, dst, dst_flags, args[0], args[1], args[2]);
-		break;
-	    case OPCODE_TEX:
-		emit_tex(c, dst, dst_flags, args[0],
-			 get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
-				 0, 1, 0, 0),
-			 inst->TexSrcTarget,
-			 inst->TexSrcUnit,
-			 (c->key.shadowtex_mask & (1 << inst->TexSrcUnit)) != 0);
-		break;
-	    case OPCODE_TXB:
-		emit_txb(c, dst, dst_flags, args[0],
-			 get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH,
-				 0, 1, 0, 0),
-			 inst->TexSrcTarget,
-			 c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]);
-		break;
-	    case OPCODE_KIL_NV:
-		emit_kil_nv(c);
-		break;
-	    case OPCODE_IF:
-		assert(if_depth < MAX_IF_DEPTH);
-		if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8);
-		if_depth_in_loop[loop_depth]++;
-		break;
-	    case OPCODE_ELSE:
-		assert(if_depth > 0);
-		if_inst[if_depth-1]  = brw_ELSE(p, if_inst[if_depth-1]);
-		break;
-	    case OPCODE_ENDIF:
-		assert(if_depth > 0);
-		brw_ENDIF(p, if_inst[--if_depth]);
-		if_depth_in_loop[loop_depth]--;
-		break;
-	    case OPCODE_BGNSUB:
-		brw_save_label(p, inst->Comment, p->nr_insn);
-		break;
-	    case OPCODE_ENDSUB:
-		/* no-op */
-		break;
-	    case OPCODE_CAL: 
-		brw_push_insn_state(p);
-		brw_set_mask_control(p, BRW_MASK_DISABLE);
-                brw_set_access_mode(p, BRW_ALIGN_1);
-                brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
-                brw_set_access_mode(p, BRW_ALIGN_16);
-                brw_ADD(p, get_addr_reg(stack_index),
-                         get_addr_reg(stack_index), brw_imm_d(4));
-		brw_save_call(&c->func, inst->Comment, p->nr_insn);
-                brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
-                brw_pop_insn_state(p);
-		break;
-
-	    case OPCODE_RET:
-		brw_push_insn_state(p);
-		brw_set_mask_control(p, BRW_MASK_DISABLE);
-                brw_ADD(p, get_addr_reg(stack_index),
-                        get_addr_reg(stack_index), brw_imm_d(-4));
-                brw_set_access_mode(p, BRW_ALIGN_1);
-                brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
-                brw_set_access_mode(p, BRW_ALIGN_16);
-		brw_pop_insn_state(p);
-
-		break;
-	    case OPCODE_BGNLOOP:
-                /* XXX may need to invalidate the current_constant regs */
-		loop_inst[loop_depth++] = brw_DO(p, BRW_EXECUTE_8);
-		if_depth_in_loop[loop_depth] = 0;
-		break;
-	    case OPCODE_BRK:
-		brw_BREAK(p, if_depth_in_loop[loop_depth]);
-		brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-		break;
-	    case OPCODE_CONT:
-		brw_CONT(p, if_depth_in_loop[loop_depth]);
-		brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-		break;
-	    case OPCODE_ENDLOOP: 
-               {
-                  struct brw_instruction *inst0, *inst1;
-                  GLuint br = 1;
-
-                  if (intel->gen == 5)
-                     br = 2;
-
-		  assert(loop_depth > 0);
-                  loop_depth--;
-                  inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]);
-                  /* patch all the BREAK/CONT instructions from last BGNLOOP */
-                  while (inst0 > loop_inst[loop_depth]) {
-                     inst0--;
-                     if (inst0->header.opcode == BRW_OPCODE_BREAK &&
-			 inst0->bits3.if_else.jump_count == 0) {
-			inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
-                     }
-                     else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
-			      inst0->bits3.if_else.jump_count == 0) {
-                        inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
-                     }
-                  }
-               }
-               break;
-	    default:
-		printf("unsupported opcode %d (%s) in fragment shader\n",
-		       inst->Opcode, inst->Opcode < MAX_OPCODE ?
-		       _mesa_opcode_string(inst->Opcode) : "unknown");
-	}
-
-	/* Release temporaries containing any unaliased source regs. */
-	release_tmps( c, mark );
-
-	if (inst->CondUpdate)
-	    brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
-	else
-	    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-    }
-    post_wm_emit(c);
-
-    if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
-      printf("wm-native:\n");
-      for (i = 0; i < p->nr_insn; i++)
-	 brw_disasm(stdout, &p->store[i], intel->gen);
-      printf("\n");
-    }
-}
-
-/**
- * Do GPU code generation for shaders that use GLSL features such as
- * flow control.  Other shaders will be compiled with the 
- */
-void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
-{
-    if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
-        printf("brw_wm_glsl_emit:\n");
-    }
-
-    /* initial instruction translation/simplification */
-    brw_wm_pass_fp(c);
-
-    /* actual code generation */
-    brw_wm_emit_glsl(brw, c);
-
-    if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
-        brw_wm_print_program(c, "brw_wm_glsl_emit done");
-    }
-
-    c->prog_data.total_grf = num_grf_used(c);
-    c->prog_data.total_scratch = 0;
-}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c
index 62e556698b..471ea1c18d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c
@@ -120,14 +120,14 @@ const struct {
  * \param line_aa  AA_NEVER, AA_ALWAYS or AA_SOMETIMES
  * \param lookup  bitmask of IZ_* flags
  */
-void brw_wm_lookup_iz( struct intel_context *intel,
-		       GLuint line_aa,
-		       GLuint lookup,
-		       GLboolean ps_uses_depth,
-		       struct brw_wm_prog_key *key )
+void brw_wm_lookup_iz(struct intel_context *intel,
+		      struct brw_wm_compile *c)
 {
    GLuint reg = 2;
    GLboolean kill_stats_promoted_workaround = GL_FALSE;
+   int lookup = c->key.iz_lookup;
+   bool uses_depth = (c->fp->program.Base.InputsRead &
+		      (1 << FRAG_ATTRIB_WPOS)) != 0;
 
    assert (lookup < IZ_BIT_MAX);
 
@@ -136,36 +136,36 @@ void brw_wm_lookup_iz( struct intel_context *intel,
     * statistics are enabled..." paragraph of 11.5.3.2: Early Depth
     * Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
     */
-   if (intel->stats_wm &&
+   if (c->key.stats_wm &&
        (lookup & IZ_PS_KILL_ALPHATEST_BIT) &&
        wm_iz_table[lookup].mode == P) {
       kill_stats_promoted_workaround = GL_TRUE;
    }
 
    if (lookup & IZ_PS_COMPUTES_DEPTH_BIT)
-      key->computes_depth = 1;
+      c->computes_depth = 1;
 
-   if (wm_iz_table[lookup].sd_present || ps_uses_depth ||
+   if (wm_iz_table[lookup].sd_present || uses_depth ||
        kill_stats_promoted_workaround) {
-      key->source_depth_reg = reg;
+      c->source_depth_reg = reg;
       reg += 2;
    }
 
    if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
-      key->source_depth_to_render_target = 1;
+      c->source_depth_to_render_target = 1;
 
-   if (wm_iz_table[lookup].ds_present || line_aa != AA_NEVER) {
-      key->aa_dest_stencil_reg = reg;
-      key->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present &&
-				      line_aa == AA_SOMETIMES);
+   if (wm_iz_table[lookup].ds_present || c->key.line_aa != AA_NEVER) {
+      c->aa_dest_stencil_reg = reg;
+      c->runtime_check_aads_emit = (!wm_iz_table[lookup].ds_present &&
+				    c->key.line_aa == AA_SOMETIMES);
       reg++;
    }
 
    if (wm_iz_table[lookup].dd_present) {
-      key->dest_depth_reg = reg;
+      c->dest_depth_reg = reg;
       reg+=2;
    }
 
-   key->nr_payload_regs = reg;
+   c->nr_payload_regs = reg;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass0.c b/src/mesa/drivers/dri/i965/brw_wm_pass0.c
index 83152526b3..f78bdc3186 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass0.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass0.c
@@ -380,7 +380,7 @@ static void pass0_init_payload( struct brw_wm_compile *c )
    GLuint i;
 
    for (i = 0; i < 4; i++) {
-      GLuint j = i >= (c->key.nr_payload_regs + 1) / 2 ? 0 : i;
+      GLuint j = i >= (c->nr_payload_regs + 1) / 2 ? 0 : i;
       pass0_set_fpreg_value( c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, 
 			     &c->payload.depth[j] );
    }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass1.c b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
index 3a2874b6dd..7d6a3fa9f1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass1.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass1.c
@@ -128,8 +128,7 @@ void brw_wm_pass1( struct brw_wm_compile *c )
       if (inst->opcode == WM_FB_WRITE) {
 	 track_arg(c, inst, 0, WRITEMASK_XYZW); 
 	 track_arg(c, inst, 1, WRITEMASK_XYZW); 
-	 if (c->key.source_depth_to_render_target &&
-	     c->key.computes_depth)
+	 if (c->source_depth_to_render_target && c->computes_depth)
 	    track_arg(c, inst, 2, WRITEMASK_Z); 
 	 else
 	    track_arg(c, inst, 2, 0); 
@@ -281,7 +280,6 @@ void brw_wm_pass1( struct brw_wm_compile *c )
 
       case OPCODE_DST:
       case WM_FRONTFACING:
-      case OPCODE_KIL_NV:
       default:
 	 break;
       }
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 44e3953814..8c2b9e7020 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,6 +69,8 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
+   struct brw_context *brw = c->func.brw;
+   struct intel_context *intel = &brw->intel;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -76,32 +78,41 @@ static void init_registers( struct brw_wm_compile *c )
    for (j = 0; j < c->grf_limit; j++) 
       c->pass2_grf[j].nextuse = BRW_WM_MAX_INSN;
 
-   for (j = 0; j < (c->key.nr_payload_regs + 1) / 2; j++)
+   for (j = 0; j < (c->nr_payload_regs + 1) / 2; j++)
       prealloc_reg(c, &c->payload.depth[j], i++);
 
    for (j = 0; j < c->nr_creg; j++) 
       prealloc_reg(c, &c->creg[j], i++);
 
-   for (j = 0; j < VERT_RESULT_MAX; j++) {
-      if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
-	 int fp_index;
-
-	 if (j >= VERT_RESULT_VAR0)
-	    fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
-	 else if (j <= VERT_RESULT_TEX7)
-	    fp_index = j;
-	 else
-	    fp_index = -1;
-
-	 nr_interp_regs++;
-	 if (fp_index >= 0)
-	    prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
+   if (intel->gen >= 6) {
+      for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) {
+	 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(j)) {
+	    nr_interp_regs++;
+	    prealloc_reg(c, &c->payload.input_interp[j], i++);
+	 }
+      }
+   } else {
+      for (j = 0; j < VERT_RESULT_MAX; j++) {
+	 if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
+	    int fp_index;
+
+	    if (j >= VERT_RESULT_VAR0)
+	       fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	    else if (j <= VERT_RESULT_TEX7)
+	       fp_index = j;
+	    else
+	       fp_index = -1;
+
+	    nr_interp_regs++;
+	    if (fp_index >= 0)
+	       prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
+	 }
       }
+      assert(nr_interp_regs >= 1);
    }
 
-   assert(nr_interp_regs >= 1);
 
-   c->prog_data.first_curbe_grf = ALIGN(c->key.nr_payload_regs, 2);
+   c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2);
    c->prog_data.urb_read_length = nr_interp_regs * 2;
    c->prog_data.curb_read_length = c->nr_creg * 2;
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index fea96d3538..e7c97a1cb0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -69,12 +69,43 @@ static GLuint translate_wrap_mode( GLenum wrap )
 static drm_intel_bo *upload_default_color( struct brw_context *brw,
 				     const GLfloat *color )
 {
-   struct brw_sampler_default_color sdc;
+   struct intel_context *intel = &brw->intel;
 
-   COPY_4V(sdc.color, color); 
-   
-   return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR,
-			 &sdc, sizeof(sdc));
+   if (intel->gen >= 5) {
+      struct gen5_sampler_default_color sdc;
+
+      memset(&sdc, 0, sizeof(sdc));
+
+      UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[0], color[0]);
+      UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[1], color[1]);
+      UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[2], color[2]);
+      UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[3], color[3]);
+
+      UNCLAMPED_FLOAT_TO_USHORT(sdc.us[0], color[0]);
+      UNCLAMPED_FLOAT_TO_USHORT(sdc.us[1], color[1]);
+      UNCLAMPED_FLOAT_TO_USHORT(sdc.us[2], color[2]);
+      UNCLAMPED_FLOAT_TO_USHORT(sdc.us[3], color[3]);
+
+      UNCLAMPED_FLOAT_TO_SHORT(sdc.s[0], color[0]);
+      UNCLAMPED_FLOAT_TO_SHORT(sdc.s[1], color[1]);
+      UNCLAMPED_FLOAT_TO_SHORT(sdc.s[2], color[2]);
+      UNCLAMPED_FLOAT_TO_SHORT(sdc.s[3], color[3]);
+
+      /* XXX: Fill in half floats */
+      /* XXX: Fill in signed bytes */
+
+      COPY_4V(sdc.f, color);
+
+      return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR,
+			    &sdc, sizeof(sdc));
+   } else {
+      struct brw_sampler_default_color sdc;
+
+      COPY_4V(sdc.color, color);
+
+      return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR,
+			    &sdc, sizeof(sdc));
+   }
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 76de7b7b6f..e9ef635bca 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -87,7 +87,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
 {
    struct gl_context *ctx = &brw->intel.ctx;
    const struct gl_fragment_program *fp = brw->fragment_program;
-   const struct brw_fragment_program *bfp = (struct brw_fragment_program *) fp;
    struct intel_context *intel = &brw->intel;
 
    memset(key, 0, sizeof(*key));
@@ -132,7 +131,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
 
    /* _NEW_COLOR */
    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
-   key->is_glsl = bfp->isGLSL;
 
    /* If using the fragment shader backend, the program is always
     * 8-wide.
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 76fc94df1f..1cd736a111 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -68,104 +68,54 @@ static GLuint translate_tex_target( GLenum target )
    }
 }
 
+static uint32_t brw_format_for_mesa_format[MESA_FORMAT_COUNT] =
+{
+   [MESA_FORMAT_L8] = BRW_SURFACEFORMAT_L8_UNORM,
+   [MESA_FORMAT_I8] = BRW_SURFACEFORMAT_I8_UNORM,
+   [MESA_FORMAT_A8] = BRW_SURFACEFORMAT_A8_UNORM,
+   [MESA_FORMAT_AL88] = BRW_SURFACEFORMAT_L8A8_UNORM,
+   [MESA_FORMAT_AL1616] = BRW_SURFACEFORMAT_L16A16_UNORM,
+   [MESA_FORMAT_R8] = BRW_SURFACEFORMAT_R8_UNORM,
+   [MESA_FORMAT_R16] = BRW_SURFACEFORMAT_R16_UNORM,
+   [MESA_FORMAT_RG88] = BRW_SURFACEFORMAT_R8G8_UNORM,
+   [MESA_FORMAT_RG1616] = BRW_SURFACEFORMAT_R16G16_UNORM,
+   [MESA_FORMAT_ARGB8888] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM,
+   [MESA_FORMAT_XRGB8888] = BRW_SURFACEFORMAT_B8G8R8X8_UNORM,
+   [MESA_FORMAT_RGB565] = BRW_SURFACEFORMAT_B5G6R5_UNORM,
+   [MESA_FORMAT_ARGB1555] = BRW_SURFACEFORMAT_B5G5R5A1_UNORM,
+   [MESA_FORMAT_ARGB4444] = BRW_SURFACEFORMAT_B4G4R4A4_UNORM,
+   [MESA_FORMAT_YCBCR_REV] = BRW_SURFACEFORMAT_YCRCB_NORMAL,
+   [MESA_FORMAT_YCBCR] = BRW_SURFACEFORMAT_YCRCB_SWAPUVY,
+   [MESA_FORMAT_RGB_FXT1] = BRW_SURFACEFORMAT_FXT1,
+   [MESA_FORMAT_RGBA_FXT1] = BRW_SURFACEFORMAT_FXT1,
+   [MESA_FORMAT_RGB_DXT1] = BRW_SURFACEFORMAT_DXT1_RGB,
+   [MESA_FORMAT_RGBA_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM,
+   [MESA_FORMAT_RGBA_DXT3] = BRW_SURFACEFORMAT_BC2_UNORM,
+   [MESA_FORMAT_RGBA_DXT5] = BRW_SURFACEFORMAT_BC3_UNORM,
+   [MESA_FORMAT_SRGB_DXT1] = BRW_SURFACEFORMAT_BC1_UNORM_SRGB,
+   [MESA_FORMAT_SARGB8] = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB,
+   [MESA_FORMAT_SLA8] = BRW_SURFACEFORMAT_L8A8_UNORM_SRGB,
+   [MESA_FORMAT_SL8] = BRW_SURFACEFORMAT_L8_UNORM_SRGB,
+   [MESA_FORMAT_DUDV8] = BRW_SURFACEFORMAT_R8G8_SNORM,
+   [MESA_FORMAT_SIGNED_RGBA8888_REV] = BRW_SURFACEFORMAT_R8G8B8A8_SNORM,
+};
 
 static GLuint translate_tex_format( gl_format mesa_format,
                                     GLenum internal_format,
 				    GLenum depth_mode )
 {
    switch( mesa_format ) {
-   case MESA_FORMAT_L8:
-      return BRW_SURFACEFORMAT_L8_UNORM;
-
-   case MESA_FORMAT_I8:
-      return BRW_SURFACEFORMAT_I8_UNORM;
-
-   case MESA_FORMAT_A8:
-      return BRW_SURFACEFORMAT_A8_UNORM; 
-
-   case MESA_FORMAT_AL88:
-      return BRW_SURFACEFORMAT_L8A8_UNORM;
-
-   case MESA_FORMAT_AL1616:
-      return BRW_SURFACEFORMAT_L16A16_UNORM;
-
-   case MESA_FORMAT_R8:
-      return BRW_SURFACEFORMAT_R8_UNORM;
-
-   case MESA_FORMAT_R16:
-      return BRW_SURFACEFORMAT_R16_UNORM;
-
-   case MESA_FORMAT_RG88:
-      return BRW_SURFACEFORMAT_R8G8_UNORM;
-
-   case MESA_FORMAT_RG1616:
-      return BRW_SURFACEFORMAT_R16G16_UNORM;
-
-   case MESA_FORMAT_RGB888:
-      assert(0);		/* not supported for sampling */
-      return BRW_SURFACEFORMAT_R8G8B8_UNORM;      
-
-   case MESA_FORMAT_ARGB8888:
-      return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-
-   case MESA_FORMAT_XRGB8888:
-      return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
-
-   case MESA_FORMAT_RGBA8888_REV:
-      _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
-      return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
-
-   case MESA_FORMAT_RGB565:
-      return BRW_SURFACEFORMAT_B5G6R5_UNORM;
-
-   case MESA_FORMAT_ARGB1555:
-      return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
-
-   case MESA_FORMAT_ARGB4444:
-      return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
-
-   case MESA_FORMAT_YCBCR_REV:
-      return BRW_SURFACEFORMAT_YCRCB_NORMAL;
-
-   case MESA_FORMAT_YCBCR:
-      return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
-
-   case MESA_FORMAT_RGB_FXT1:
-   case MESA_FORMAT_RGBA_FXT1:
-      return BRW_SURFACEFORMAT_FXT1;
 
    case MESA_FORMAT_Z16:
       if (depth_mode == GL_INTENSITY) 
 	  return BRW_SURFACEFORMAT_I16_UNORM;
       else if (depth_mode == GL_ALPHA)
 	  return BRW_SURFACEFORMAT_A16_UNORM;
+      else if (depth_mode == GL_RED)
+	  return BRW_SURFACEFORMAT_R16_UNORM;
       else
 	  return BRW_SURFACEFORMAT_L16_UNORM;
 
-   case MESA_FORMAT_RGB_DXT1:
-       return BRW_SURFACEFORMAT_DXT1_RGB;
-
-   case MESA_FORMAT_RGBA_DXT1:
-       return BRW_SURFACEFORMAT_BC1_UNORM;
-       
-   case MESA_FORMAT_RGBA_DXT3:
-       return BRW_SURFACEFORMAT_BC2_UNORM;
-       
-   case MESA_FORMAT_RGBA_DXT5:
-       return BRW_SURFACEFORMAT_BC3_UNORM;
-
-   case MESA_FORMAT_SARGB8:
-      return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
-
-   case MESA_FORMAT_SLA8:
-      return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
-
-   case MESA_FORMAT_SL8:
-      return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
-
-   case MESA_FORMAT_SRGB_DXT1:
-      return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
-
    case MESA_FORMAT_S8_Z24:
       /* XXX: these different surface formats don't seem to
        * make any difference for shadow sampler/compares.
@@ -174,18 +124,14 @@ static GLuint translate_tex_format( gl_format mesa_format,
          return BRW_SURFACEFORMAT_I24X8_UNORM;
       else if (depth_mode == GL_ALPHA)
          return BRW_SURFACEFORMAT_A24X8_UNORM;
+      else if (depth_mode == GL_RED)
+         return BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS;
       else
          return BRW_SURFACEFORMAT_L24X8_UNORM;
 
-   case MESA_FORMAT_DUDV8:
-      return BRW_SURFACEFORMAT_R8G8_SNORM;
-
-   case MESA_FORMAT_SIGNED_RGBA8888_REV:
-      return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
-
    default:
-      assert(0);
-      return 0;
+      assert(brw_format_for_mesa_format[mesa_format] != 0);
+      return brw_format_for_mesa_format[mesa_format];
    }
 }
 
@@ -274,6 +220,7 @@ brw_create_constant_surface(struct brw_context *brw,
 			    drm_intel_bo **out_bo,
 			    uint32_t *out_offset)
 {
+   struct intel_context *intel = &brw->intel;
    const GLint w = width - 1;
    struct brw_surface_state surf;
    void *map;
@@ -284,6 +231,9 @@ brw_create_constant_surface(struct brw_context *brw,
    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 
+   if (intel->gen >= 6)
+      surf.ss0.render_cache_read_write = 1;
+
    assert(bo);
    surf.ss1.base_addr = bo->offset; /* reloc */
 
@@ -440,45 +390,19 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
 
       key.surface_type = BRW_SURFACE_2D;
       switch (irb->Base.Format) {
-      /* XRGB and ARGB are treated the same here because the chips in this
-       * family cannot render to XRGB targets.  This means that we have to
-       * mask writes to alpha (ala glColorMask) and reconfigure the alpha
-       * blending hardware to use GL_ONE (or GL_ZERO) for cases where
-       * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
-       */
-      case MESA_FORMAT_ARGB8888:
       case MESA_FORMAT_XRGB8888:
+	 /* XRGB is handled as ARGB because the chips in this family
+	  * cannot render to XRGB targets.  This means that we have to
+	  * mask writes to alpha (ala glColorMask) and reconfigure the
+	  * alpha blending hardware to use GL_ONE (or GL_ZERO) for
+	  * cases where GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is
+	  * used.
+	  */
 	 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 	 break;
-      case MESA_FORMAT_SARGB8:
-	 key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
-	 break;
-      case MESA_FORMAT_RGB565:
-	 key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
-	 break;
-      case MESA_FORMAT_ARGB1555:
-	 key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
-	 break;
-      case MESA_FORMAT_ARGB4444:
-	 key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
-	 break;
-      case MESA_FORMAT_A8:
-	 key.surface_format = BRW_SURFACEFORMAT_A8_UNORM;
-	 break;
-      case MESA_FORMAT_R8:
-	 key.surface_format = BRW_SURFACEFORMAT_R8_UNORM;
-	 break;
-      case MESA_FORMAT_R16:
-	 key.surface_format = BRW_SURFACEFORMAT_R16_UNORM;
-	 break;
-      case MESA_FORMAT_RG88:
-	 key.surface_format = BRW_SURFACEFORMAT_R8G8_UNORM;
-	 break;
-      case MESA_FORMAT_RG1616:
-	 key.surface_format = BRW_SURFACEFORMAT_R16G16_UNORM;
-	 break;
       default:
-	 _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
+	 key.surface_format = brw_format_for_mesa_format[irb->Base.Format];
+	 assert(key.surface_format != 0);
       }
       key.tiling = region->tiling;
       key.width = rb->Width;
diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c
index 800a255521..c2631a7b4d 100644
--- a/src/mesa/drivers/dri/i965/gen6_cc.c
+++ b/src/mesa/drivers/dri/i965/gen6_cc.c
@@ -35,6 +35,7 @@
 struct gen6_blend_state_key {
    GLboolean color_blend, alpha_enabled;
    GLboolean dither;
+   GLboolean color_mask[BRW_MAX_DRAW_BUFFERS][4];
 
    GLenum logic_op;
 
@@ -54,6 +55,9 @@ blend_state_populate_key(struct brw_context *brw,
    memset(key, 0, sizeof(*key));
 
    /* _NEW_COLOR */
+   memcpy(key->color_mask, ctx->Color.ColorMask, sizeof(key->color_mask));
+
+   /* _NEW_COLOR */
    if (ctx->Color._LogicOpEnabled)
       key->logic_op = ctx->Color.LogicOp;
    else
@@ -87,54 +91,62 @@ static drm_intel_bo *
 blend_state_create_from_key(struct brw_context *brw,
 			    struct gen6_blend_state_key *key)
 {
-   struct gen6_blend_state blend;
+   struct gen6_blend_state blend[BRW_MAX_DRAW_BUFFERS];
    drm_intel_bo *bo;
+   int b;
 
    memset(&blend, 0, sizeof(blend));
 
-   if (key->logic_op != GL_COPY) {
-      blend.blend1.logic_op_enable = 1;
-      blend.blend1.logic_op_func = intel_translate_logic_op(key->logic_op);
-   } else if (key->color_blend) {
-      GLenum eqRGB = key->blend_eq_rgb;
-      GLenum eqA = key->blend_eq_a;
-      GLenum srcRGB = key->blend_src_rgb;
-      GLenum dstRGB = key->blend_dst_rgb;
-      GLenum srcA = key->blend_src_a;
-      GLenum dstA = key->blend_dst_a;
-
-      if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
-	 srcRGB = dstRGB = GL_ONE;
-      }
-
-      if (eqA == GL_MIN || eqA == GL_MAX) {
-	 srcA = dstA = GL_ONE;
+   for (b = 0; b < BRW_MAX_DRAW_BUFFERS; b++) {
+      if (key->logic_op != GL_COPY) {
+	 blend[b].blend1.logic_op_enable = 1;
+	 blend[b].blend1.logic_op_func = intel_translate_logic_op(key->logic_op);
+      } else if (key->color_blend & (1 << b)) {
+	 GLenum eqRGB = key->blend_eq_rgb;
+	 GLenum eqA = key->blend_eq_a;
+	 GLenum srcRGB = key->blend_src_rgb;
+	 GLenum dstRGB = key->blend_dst_rgb;
+	 GLenum srcA = key->blend_src_a;
+	 GLenum dstA = key->blend_dst_a;
+
+	 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
+	    srcRGB = dstRGB = GL_ONE;
+	 }
+
+	 if (eqA == GL_MIN || eqA == GL_MAX) {
+	    srcA = dstA = GL_ONE;
+	 }
+
+	 blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB);
+	 blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB);
+	 blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB);
+
+	 blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
+	 blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA);
+	 blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA);
+
+	 blend[b].blend0.blend_enable = 1;
+	 blend[b].blend0.ia_blend_enable = (srcA != srcRGB ||
+					 dstA != dstRGB ||
+					 eqA != eqRGB);
       }
 
-      blend.blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB);
-      blend.blend0.source_blend_factor = brw_translate_blend_factor(srcRGB);
-      blend.blend0.blend_func = brw_translate_blend_equation(eqRGB);
-
-      blend.blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
-      blend.blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA);
-      blend.blend0.ia_blend_func = brw_translate_blend_equation(eqA);
+      if (key->alpha_enabled) {
+	 blend[b].blend1.alpha_test_enable = 1;
+	 blend[b].blend1.alpha_test_func = intel_translate_compare_func(key->alpha_func);
 
-      blend.blend0.blend_enable = 1;
-      blend.blend0.ia_blend_enable = (srcA != srcRGB ||
-				      dstA != dstRGB ||
-				      eqA != eqRGB);
-   }
-
-   if (key->alpha_enabled) {
-      blend.blend1.alpha_test_enable = 1;
-      blend.blend1.alpha_test_func = intel_translate_compare_func(key->alpha_func);
+      }
 
-   }
+      if (key->dither) {
+	 blend[b].blend1.dither_enable = 1;
+	 blend[b].blend1.y_dither_offset = 0;
+	 blend[b].blend1.x_dither_offset = 0;
+      }
 
-   if (key->dither) {
-      blend.blend1.dither_enable = 1;
-      blend.blend1.y_dither_offset = 0;
-      blend.blend1.x_dither_offset = 0;
+      blend[b].blend1.write_disable_r = !key->color_mask[b][0];
+      blend[b].blend1.write_disable_g = !key->color_mask[b][1];
+      blend[b].blend1.write_disable_b = !key->color_mask[b][2];
+      blend[b].blend1.write_disable_a = !key->color_mask[b][3];
    }
 
    bo = brw_upload_cache(&brw->cache, BRW_BLEND_STATE,
@@ -172,7 +184,7 @@ const struct brw_tracked_state gen6_blend_state = {
 };
 
 struct gen6_color_calc_state_key {
-   GLubyte blend_constant_color[4];
+   float blend_constant_color[4];
    GLclampf alpha_ref;
    GLubyte stencil_ref[2];
 };
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index c65b41e2b6..c7c4eb1f27 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -64,7 +64,9 @@ upload_clip_state(struct brw_context *brw)
 	     userclip << GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT |
 	     depth_clamp |
 	     provoking);
-   OUT_BATCH(GEN6_CLIP_FORCE_ZERO_RTAINDEX);
+   OUT_BATCH(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
+             U_FIXED(225.875, 3) << GEN6_CLIP_MAX_POINT_WIDTH_SHIFT |
+             GEN6_CLIP_FORCE_ZERO_RTAINDEX);
    ADVANCE_BATCH();
 }
 
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 471067e8f0..45c148baed 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -33,9 +33,10 @@
 #include "intel_batchbuffer.h"
 
 static uint32_t
-get_attr_override(struct brw_context *brw, int fs_attr)
+get_attr_override(struct brw_context *brw, int fs_attr, int two_side_color)
 {
    int attr_index = 0, i, vs_attr;
+   int bfc = 0;
 
    if (fs_attr <= FRAG_ATTRIB_TEX7)
       vs_attr = fs_attr;
@@ -57,6 +58,30 @@ get_attr_override(struct brw_context *brw, int fs_attr)
 	 attr_index++;
    }
 
+   assert(attr_index < 32);
+
+   if (two_side_color) {
+       if ((brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL1)) &&
+           (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC1))) {
+           assert(brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0));
+           assert(brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0));
+           bfc = 2;
+       } else if ((brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_COL0)) &&
+                (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(VERT_RESULT_BFC0)))
+           bfc = 1;
+   }
+
+   if (bfc && (fs_attr <= FRAG_ATTRIB_TEX7 && fs_attr > FRAG_ATTRIB_WPOS)) {
+       if (fs_attr == FRAG_ATTRIB_COL0)
+           attr_index |= (ATTRIBUTE_SWIZZLE_INPUTATTR_FACING << ATTRIBUTE_SWIZZLE_SHIFT);
+       else if (fs_attr == FRAG_ATTRIB_COL1 && bfc == 2) {
+           attr_index++;
+           attr_index |= (ATTRIBUTE_SWIZZLE_INPUTATTR_FACING << ATTRIBUTE_SWIZZLE_SHIFT);
+       } else {
+           attr_index += bfc;
+       }
+   }
+
    return attr_index;
 }
 
@@ -67,13 +92,15 @@ upload_sf_state(struct brw_context *brw)
    struct gl_context *ctx = &intel->ctx;
    /* CACHE_NEW_VS_PROG */
    uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
+   /* BRW_NEW_FRAGMENT_PROGRAM */
    uint32_t num_outputs = brw_count_bits(brw->fragment_program->Base.InputsRead);
-   uint32_t dw1, dw2, dw3, dw4, dw16;
+   uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
    int i;
    /* _NEW_BUFFER */
    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
    int attr = 0;
    int urb_start;
+   int two_side_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
 
    /* _NEW_TRANSFORM */
    if (ctx->Transform.ClipPlanesEnabled)
@@ -91,6 +118,7 @@ upload_sf_state(struct brw_context *brw)
    dw3 = 0;
    dw4 = 0;
    dw16 = 0;
+   dw17 = 0;
 
    /* _NEW_POLYGON */
    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
@@ -99,6 +127,48 @@ upload_sf_state(struct brw_context *brw)
    if (ctx->Polygon.OffsetFill)
        dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
 
+   if (ctx->Polygon.OffsetLine)
+       dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME;
+
+   if (ctx->Polygon.OffsetPoint)
+       dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT;
+
+   switch (ctx->Polygon.FrontMode) {
+   case GL_FILL:
+       dw2 |= GEN6_SF_FRONT_SOLID;
+       break;
+
+   case GL_LINE:
+       dw2 |= GEN6_SF_FRONT_WIREFRAME;
+       break;
+
+   case GL_POINT:
+       dw2 |= GEN6_SF_FRONT_POINT;
+       break;
+
+   default:
+       assert(0);
+       break;
+   }
+
+   switch (ctx->Polygon.BackMode) {
+   case GL_FILL:
+       dw2 |= GEN6_SF_BACK_SOLID;
+       break;
+
+   case GL_LINE:
+       dw2 |= GEN6_SF_BACK_WIREFRAME;
+       break;
+
+   case GL_POINT:
+       dw2 |= GEN6_SF_BACK_POINT;
+       break;
+
+   default:
+       assert(0);
+       break;
+   }
+
    /* _NEW_SCISSOR */
    if (ctx->Scissor.Enabled)
       dw3 |= GEN6_SF_SCISSOR_ENABLE;
@@ -160,6 +230,12 @@ upload_sf_state(struct brw_context *brw)
        }
    }
 
+   /* flat shading */
+   if (ctx->Light.ShadeModel == GL_FLAT) {
+       dw17 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 | FRAG_BIT_COL1)) >>
+                ((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0 : 1));
+   }
+
    BEGIN_BATCH(20);
    OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
    OUT_BATCH(dw1);
@@ -174,7 +250,7 @@ upload_sf_state(struct brw_context *brw)
 
       for (; attr < 64; attr++) {
 	 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)) {
-	    attr_overrides |= get_attr_override(brw, attr);
+	    attr_overrides |= get_attr_override(brw, attr, two_side_color);
 	    attr++;
 	    break;
 	 }
@@ -182,7 +258,7 @@ upload_sf_state(struct brw_context *brw)
 
       for (; attr < 64; attr++) {
 	 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)) {
-	    attr_overrides |= get_attr_override(brw, attr) << 16;
+	    attr_overrides |= get_attr_override(brw, attr, two_side_color) << 16;
 	    attr++;
 	    break;
 	 }
@@ -190,7 +266,7 @@ upload_sf_state(struct brw_context *brw)
       OUT_BATCH(attr_overrides);
    }
    OUT_BATCH(dw16); /* point sprite texcoord bitmask */
-   OUT_BATCH(0); /* constant interp bitmask */
+   OUT_BATCH(dw17); /* constant interp bitmask */
    OUT_BATCH(0); /* wrapshortest enables 0-7 */
    OUT_BATCH(0); /* wrapshortest enables 8-15 */
    ADVANCE_BATCH();
@@ -205,7 +281,8 @@ const struct brw_tracked_state gen6_sf_state = {
 		_NEW_BUFFERS |
 		_NEW_POINT |
 		_NEW_TRANSFORM),
-      .brw   = BRW_NEW_CONTEXT,
+      .brw   = (BRW_NEW_CONTEXT |
+		BRW_NEW_FRAGMENT_PROGRAM),
       .cache = CACHE_NEW_VS_PROG
    },
    .emit = upload_sf_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index a34123478f..de97fd3783 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -72,7 +72,7 @@ const struct brw_tracked_state gen6_urb = {
    .dirty = {
       .mesa = 0,
       .brw = BRW_NEW_CONTEXT,
-      .cache = CACHE_NEW_VS_PROG,
+      .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
    },
    .prepare = prepare_urb,
    .emit = upload_urb,
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index e94d0c0ddb..ed132bdbd9 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -54,7 +54,7 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
       ADVANCE_BATCH();
    } else {
-      int params_uploaded = 0;
+      int params_uploaded = 0, param_regs;
       float *param;
 
       if (brw->vertex_program->IsNVProgram)
@@ -88,20 +88,11 @@ upload_vs_state(struct brw_context *brw)
 	 params_uploaded++;
       }
 
-      if (vp->use_const_buffer) {
-	 for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
-	    if (brw->vs.constant_map[i] != -1) {
-	       memcpy(param + brw->vs.constant_map[i] * 4,
-		      vp->program.Base.Parameters->ParameterValues[i],
-		      4 * sizeof(float));
-	       params_uploaded++;
-	    }
-	 }
-      } else {
-	 for (i = 0; i < nr_params; i++) {
-	    memcpy(param, vp->program.Base.Parameters->ParameterValues[i],
+      for (i = 0; i < vp->program.Base.Parameters->NumParameters; i++) {
+	 if (brw->vs.constant_map[i] != -1) {
+	    memcpy(param + brw->vs.constant_map[i] * 4,
+		   vp->program.Base.Parameters->ParameterValues[i],
 		   4 * sizeof(float));
-	    param += 4;
 	    params_uploaded++;
 	 }
       }
@@ -117,13 +108,16 @@ upload_vs_state(struct brw_context *brw)
 
       drm_intel_gem_bo_unmap_gtt(constant_bo);
 
+      param_regs = (params_uploaded + 1) / 2;
+      assert(param_regs <= 32);
+
       BEGIN_BATCH(5);
       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
 		GEN6_CONSTANT_BUFFER_0_ENABLE |
 		(5 - 2));
       OUT_RELOC(constant_bo,
 		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
-		ALIGN(params_uploaded, 2) / 2 - 1);
+		param_regs - 1);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -136,6 +130,7 @@ upload_vs_state(struct brw_context *brw)
    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
    OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
+	     GEN6_VS_FLOATING_POINT_MODE_ALT |
 	     (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
    OUT_BATCH(0); /* scratch space base offset */
    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index ea5418bacf..2ae0c093eb 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -66,6 +66,21 @@ prepare_wm_constants(struct brw_context *brw)
 	 constants[i] = convert_param(brw->wm.prog_data->param_convert[i],
 				      *brw->wm.prog_data->param[i]);
       }
+
+      if (0) {
+	 printf("WM constants:\n");
+	 for (i = 0; i < brw->wm.prog_data->nr_params; i++) {
+	    if ((i & 7) == 0)
+	       printf("g%d: ", brw->wm.prog_data->first_curbe_grf + i / 8);
+	    printf("%8f ", constants[i]);
+	    if ((i & 7) == 7)
+	       printf("\n");
+	 }
+	 if ((i & 7) != 0)
+	    printf("\n");
+	 printf("\n");
+      }
+
       drm_intel_gem_bo_unmap_gtt(brw->wm.push_const_bo);
    }
 }
@@ -88,6 +103,7 @@ upload_wm_state(struct brw_context *brw)
       brw_fragment_program_const(brw->fragment_program);
    uint32_t dw2, dw4, dw5, dw6;
 
+   /* CACHE_NEW_WM_PROG */
    if (brw->wm.prog_data->nr_params == 0) {
       /* Disable the push constant buffers. */
       BEGIN_BATCH(5);
@@ -104,7 +120,8 @@ upload_wm_state(struct brw_context *brw)
 		(5 - 2));
       OUT_RELOC(brw->wm.push_const_bo,
 		I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
-		ALIGN(brw->wm.prog_data->nr_params, 8) / 8 - 1);
+		ALIGN(brw->wm.prog_data->nr_params,
+		      brw->wm.prog_data->dispatch_width) / 8 - 1);
       OUT_BATCH(0);
       OUT_BATCH(0);
       OUT_BATCH(0);
@@ -116,6 +133,9 @@ upload_wm_state(struct brw_context *brw)
    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 
+   /* OpenGL non-ieee floating point mode */
+   dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
+
    /* BRW_NEW_NR_WM_SURFACES */
    dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
 
@@ -126,8 +146,8 @@ upload_wm_state(struct brw_context *brw)
 
    dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (fp->isGLSL)
+   /* CACHE_NEW_WM_PROG */
+   if (brw->wm.prog_data->dispatch_width == 8)
       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
    else
       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
@@ -176,13 +196,14 @@ upload_wm_state(struct brw_context *brw)
 const struct brw_tracked_state gen6_wm_state = {
    .dirty = {
       .mesa  = (_NEW_LINE | _NEW_POLYGONSTIPPLE | _NEW_COLOR | _NEW_BUFFERS |
-		_NEW_PROGRAM_CONSTANTS),
+		_NEW_PROGRAM_CONSTANTS | _NEW_POLYGON),
       .brw   = (BRW_NEW_CURBE_OFFSETS |
 		BRW_NEW_FRAGMENT_PROGRAM |
                 BRW_NEW_NR_WM_SURFACES |
 		BRW_NEW_URB_FENCE |
 		BRW_NEW_BATCH),
-      .cache = CACHE_NEW_SAMPLER
+      .cache = (CACHE_NEW_SAMPLER |
+		CACHE_NEW_WM_PROG)
    },
    .emit = upload_wm_state,
 };
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index 4b498f8c5b..20574ab546 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -92,9 +92,17 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used)
 
    batch->ptr = NULL;
 
-   if (!intel->no_hw) {
-      drm_intel_bo_exec(batch->buf, used, NULL, 0,
-			(x_off & 0xffff) | (y_off << 16));
+   if (!intel->intelScreen->no_hw) {
+      int ring;
+
+      if (intel->gen < 6 || !intel->batch->is_blit) {
+	 ring = I915_EXEC_RENDER;
+      } else {
+	 ring = I915_EXEC_BLT;
+      }
+
+      drm_intel_bo_mrb_exec(batch->buf, used, NULL, 0,
+			    (x_off & 0xffff) | (y_off << 16), ring);
    }
 
    if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
@@ -242,10 +250,10 @@ intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
 
 void
 intel_batchbuffer_data(struct intel_batchbuffer *batch,
-                       const void *data, GLuint bytes)
+                       const void *data, GLuint bytes, bool is_blit)
 {
    assert((bytes & 3) == 0);
-   intel_batchbuffer_require_space(batch, bytes);
+   intel_batchbuffer_require_space(batch, bytes, is_blit);
    __memcpy(batch->ptr, data, bytes);
    batch->ptr += bytes;
 }
@@ -262,22 +270,29 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
    struct intel_context *intel = batch->intel;
 
    if (intel->gen >= 6) {
-      BEGIN_BATCH(8);
-
-      /* XXX workaround: issue any post sync != 0 before write cache flush = 1 */
-      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
-      OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
-      OUT_BATCH(0); /* write address */
-      OUT_BATCH(0); /* write data */
-
-      OUT_BATCH(_3DSTATE_PIPE_CONTROL);
-      OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
-		PIPE_CONTROL_WRITE_FLUSH |
-		PIPE_CONTROL_DEPTH_CACHE_FLUSH |
-		PIPE_CONTROL_NO_WRITE);
-      OUT_BATCH(0); /* write address */
-      OUT_BATCH(0); /* write data */
-      ADVANCE_BATCH();
+      if (intel->batch->is_blit) {
+	 BEGIN_BATCH_BLT(1);
+	 OUT_BATCH(MI_FLUSH);
+	 ADVANCE_BATCH();
+      } else {
+	 BEGIN_BATCH(8);
+	 /* XXX workaround: issue any post sync != 0 before write
+	  * cache flush = 1
+	  */
+	 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+	 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+	 OUT_BATCH(0); /* write address */
+	 OUT_BATCH(0); /* write data */
+
+	 OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+	 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
+		   PIPE_CONTROL_WRITE_FLUSH |
+		   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+		   PIPE_CONTROL_NO_WRITE);
+	 OUT_BATCH(0); /* write address */
+	 OUT_BATCH(0); /* write data */
+	 ADVANCE_BATCH();
+      }
    } else if (intel->gen >= 4) {
       BEGIN_BATCH(4);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL |
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
index 428c027c2f..635708587a 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h
@@ -31,6 +31,7 @@ struct intel_batchbuffer
    } emit;
 #endif
 
+   bool is_blit;
    GLuint dirty_state;
    GLuint reserved_space;
 };
@@ -55,7 +56,7 @@ void intel_batchbuffer_reset(struct intel_batchbuffer *batch);
  * intel_buffer_dword() calls.
  */
 void intel_batchbuffer_data(struct intel_batchbuffer *batch,
-                            const void *data, GLuint bytes);
+                            const void *data, GLuint bytes, bool is_blit);
 
 void intel_batchbuffer_release_space(struct intel_batchbuffer *batch,
                                      GLuint bytes);
@@ -114,8 +115,16 @@ intel_batchbuffer_emit_float(struct intel_batchbuffer *batch, float f)
 
 static INLINE void
 intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
-                                GLuint sz)
+                                GLuint sz, int is_blit)
 {
+
+   if (batch->intel->gen >= 6 && batch->is_blit != is_blit &&
+       batch->ptr != batch->map) {
+      intel_batchbuffer_flush(batch);
+   }
+
+   batch->is_blit = is_blit;
+
 #ifdef DEBUG
    assert(sz < batch->size - 8);
 #endif
@@ -124,9 +133,10 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch,
 }
 
 static INLINE void
-intel_batchbuffer_begin(struct intel_batchbuffer *batch, int n)
+intel_batchbuffer_begin(struct intel_batchbuffer *batch, int n, bool is_blit)
 {
-   intel_batchbuffer_require_space(batch, n * 4);
+   intel_batchbuffer_require_space(batch, n * 4, is_blit);
+
 #ifdef DEBUG
    assert(batch->map);
    assert(batch->emit.start_ptr == NULL);
@@ -154,7 +164,8 @@ intel_batchbuffer_advance(struct intel_batchbuffer *batch)
  */
 #define BATCH_LOCALS
 
-#define BEGIN_BATCH(n) intel_batchbuffer_begin(intel->batch, n)
+#define BEGIN_BATCH(n) intel_batchbuffer_begin(intel->batch, n, false)
+#define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(intel->batch, n, true)
 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d)
 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(intel->batch,f)
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {		\
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index c2917e9b07..a2822b11d9 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -38,6 +38,8 @@
 #include "intel_reg.h"
 #include "intel_regions.h"
 #include "intel_batchbuffer.h"
+#include "intel_tex.h"
+#include "intel_mipmap_tree.h"
 
 #define FILE_DEBUG_FLAG DEBUG_BLIT
 
@@ -107,10 +109,6 @@ intelEmitCopyBlit(struct intel_context *intel,
    drm_intel_bo *aper_array[3];
    BATCH_LOCALS;
 
-   /* Blits are in a different ringbuffer so we don't use them. */
-   if (intel->gen >= 6)
-      return GL_FALSE;
-
    if (dst_tiling != I915_TILING_NONE) {
       if (dst_offset & 4095)
 	 return GL_FALSE;
@@ -140,7 +138,7 @@ intelEmitCopyBlit(struct intel_context *intel,
    if (pass >= 2)
       return GL_FALSE;
 
-   intel_batchbuffer_require_space(intel->batch, 8 * 4);
+   intel_batchbuffer_require_space(intel->batch, 8 * 4, true);
    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
        __FUNCTION__,
        src_buffer, src_pitch, src_offset, src_x, src_y,
@@ -181,7 +179,7 @@ intelEmitCopyBlit(struct intel_context *intel,
    assert(dst_x < dst_x2);
    assert(dst_y < dst_y2);
 
-   BEGIN_BATCH(8);
+   BEGIN_BATCH_BLT(8);
    OUT_BATCH(CMD);
    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
    OUT_BATCH((dst_y << 16) | dst_x);
@@ -219,9 +217,6 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
    GLint cx, cy, cw, ch;
    BATCH_LOCALS;
 
-   /* Blits are in a different ringbuffer so we don't use them. */
-   assert(intel->gen < 6);
-
    /*
     * Compute values for clearing the buffers.
     */
@@ -356,7 +351,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 	 intel_batchbuffer_flush(intel->batch);
       }
 
-      BEGIN_BATCH(6);
+      BEGIN_BATCH_BLT(6);
       OUT_BATCH(CMD);
       OUT_BATCH(BR13);
       OUT_BATCH((y1 << 16) | x1);
@@ -393,10 +388,6 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    int dwords = ALIGN(src_size, 8) / 4;
    uint32_t opcode, br13, blit_cmd;
 
-   /* Blits are in a different ringbuffer so we don't use them. */
-   if (intel->gen >= 6)
-      return GL_FALSE;
-
    if (dst_tiling != I915_TILING_NONE) {
       if (dst_offset & 4095)
 	 return GL_FALSE;
@@ -420,7 +411,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    intel_batchbuffer_require_space( intel->batch,
 				    (8 * 4) +
 				    (3 * 4) +
-				    dwords * 4 );
+				    dwords * 4, true);
 
    opcode = XY_SETUP_BLT_CMD;
    if (cpp == 4)
@@ -439,7 +430,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    if (dst_tiling != I915_TILING_NONE)
       blit_cmd |= XY_DST_TILED;
 
-   BEGIN_BATCH(8 + 3);
+   BEGIN_BATCH_BLT(8 + 3);
    OUT_BATCH(opcode);
    OUT_BATCH(br13);
    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
@@ -456,9 +447,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    OUT_BATCH(((y + h) << 16) | (x + w));
    ADVANCE_BATCH();
 
-   intel_batchbuffer_data( intel->batch,
-			   src_bits,
-			   dwords * 4 );
+   intel_batchbuffer_data(intel->batch,
+			  src_bits,
+			  dwords * 4, true);
 
    intel_batchbuffer_emit_mi_flush(intel->batch);
 
@@ -480,9 +471,6 @@ intel_emit_linear_blit(struct intel_context *intel,
    GLuint pitch, height;
    GLboolean ok;
 
-   /* Blits are in a different ringbuffer so we don't use them. */
-   assert(intel->gen < 6);
-
    /* The pitch given to the GPU must be DWORD aligned, and
     * we want width to match pitch. Max width is (1 << 15 - 1),
     * rounding that down to the nearest DWORD is 1 << 15 - 4
@@ -514,3 +502,81 @@ intel_emit_linear_blit(struct intel_context *intel,
       assert(ok);
    }
 }
+
+/**
+ * Used to initialize the alpha value of an ARGB8888 teximage after
+ * loading it from an XRGB8888 source.
+ *
+ * This is very common with glCopyTexImage2D().
+ */
+void
+intel_set_teximage_alpha_to_one(struct gl_context *ctx,
+				struct intel_texture_image *intel_image)
+{
+   struct intel_context *intel = intel_context(ctx);
+   unsigned int image_x, image_y;
+   uint32_t x1, y1, x2, y2;
+   uint32_t BR13, CMD;
+   int pitch, cpp;
+   drm_intel_bo *aper_array[2];
+   struct intel_region *region = intel_image->mt->region;
+   BATCH_LOCALS;
+
+   assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888);
+
+   /* get dest x/y in destination texture */
+   intel_miptree_get_image_offset(intel_image->mt,
+				  intel_image->level,
+				  intel_image->face,
+				  0,
+				  &image_x, &image_y);
+
+   x1 = image_x;
+   y1 = image_y;
+   x2 = image_x + intel_image->base.Width;
+   y2 = image_y + intel_image->base.Height;
+
+   pitch = region->pitch;
+   cpp = region->cpp;
+
+   DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
+       __FUNCTION__,
+       intel_image->mt->region->buffer, (pitch * region->cpp),
+       x1, y1, x2 - x1, y2 - y1);
+
+   BR13 = br13_for_cpp(region->cpp) | 0xf0 << 16;
+   CMD = XY_COLOR_BLT_CMD;
+   CMD |= XY_BLT_WRITE_ALPHA;
+
+   assert(region->tiling != I915_TILING_Y);
+
+#ifndef I915
+   if (region->tiling != I915_TILING_NONE) {
+      CMD |= XY_DST_TILED;
+      pitch /= 4;
+   }
+#endif
+   BR13 |= (pitch * region->cpp);
+
+   /* do space check before going any further */
+   aper_array[0] = intel->batch->buf;
+   aper_array[1] = region->buffer;
+
+   if (drm_intel_bufmgr_check_aperture_space(aper_array,
+					     ARRAY_SIZE(aper_array)) != 0) {
+      intel_batchbuffer_flush(intel->batch);
+   }
+
+   BEGIN_BATCH_BLT(6);
+   OUT_BATCH(CMD);
+   OUT_BATCH(BR13);
+   OUT_BATCH((y1 << 16) | x1);
+   OUT_BATCH((y2 << 16) | x2);
+   OUT_RELOC_FENCED(region->buffer,
+		    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+		    0);
+   OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
+   ADVANCE_BATCH();
+
+   intel_batchbuffer_emit_mi_flush(intel->batch);
+}
diff --git a/src/mesa/drivers/dri/intel/intel_blit.h b/src/mesa/drivers/dri/intel/intel_blit.h
index 0163146573..ff69e4f8f8 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.h
+++ b/src/mesa/drivers/dri/intel/intel_blit.h
@@ -69,5 +69,7 @@ void intel_emit_linear_blit(struct intel_context *intel,
 			    drm_intel_bo *src_bo,
 			    unsigned int src_offset,
 			    unsigned int size);
+void intel_set_teximage_alpha_to_one(struct gl_context *ctx,
+				     struct intel_texture_image *intel_image);
 
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 152cdcaf37..9c222c7b48 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -519,7 +519,6 @@ static const struct dri_debug_control debug_control[] = {
    { "sing",  DEBUG_SINGLE_THREAD },
    { "thre",  DEBUG_SINGLE_THREAD },
    { "wm",    DEBUG_WM },
-   { "glsl_force", DEBUG_GLSL_FORCE },
    { "urb",   DEBUG_URB },
    { "vs",    DEBUG_VS },
    { "clip",  DEBUG_CLIP },
@@ -800,11 +799,6 @@ intelInitContext(struct intel_context *intel,
    if (INTEL_DEBUG & DEBUG_BUFMGR)
       dri_bufmgr_set_debug(intel->bufmgr, GL_TRUE);
 
-   /* XXX force SIMD8 kernel for Sandybridge before we fixed
-      SIMD16 interpolation. */
-   if (intel->gen == 6)
-       INTEL_DEBUG |= DEBUG_GLSL_FORCE;
-
    intel->batch = intel_batchbuffer_alloc(intel);
 
    intel_fbo_init(intel);
@@ -838,11 +832,6 @@ intelInitContext(struct intel_context *intel,
       intel->always_flush_cache = 1;
    }
 
-   /* Disable all hardware rendering (skip emitting batches and fences/waits
-    * to the kernel)
-    */
-   intel->no_hw = getenv("INTEL_NO_HW") != NULL;
-
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 9d5139c000..53a11ba9a7 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -29,7 +29,7 @@
 #define INTELCONTEXT_INC
 
 
-
+#include <stdbool.h>
 #include "main/mtypes.h"
 #include "main/mm.h"
 #include "dri_metaops.h"
@@ -207,7 +207,6 @@ struct intel_context
    GLboolean hw_stipple;
    GLboolean depth_buffer_is_float;
    GLboolean no_rast;
-   GLboolean no_hw;
    GLboolean always_flush_batch;
    GLboolean always_flush_cache;
 
@@ -362,7 +361,6 @@ extern int INTEL_DEBUG;
 #define DEBUG_WM        0x800000
 #define DEBUG_URB       0x1000000
 #define DEBUG_VS        0x2000000
-#define DEBUG_GLSL_FORCE 0x4000000
 #define DEBUG_CLIP      0x8000000
 
 #define DBG(...) do {						\
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 862a13d2ea..f6fe7b1753 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -42,6 +42,8 @@
 #include "intel_fbo.h"
 #include "intel_mipmap_tree.h"
 #include "intel_regions.h"
+#include "intel_tex.h"
+#include "intel_span.h"
 
 #define FILE_DEBUG_FLAG DEBUG_FBO
 
@@ -107,79 +109,27 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
    ASSERT(rb->Name != 0);
 
    switch (internalFormat) {
-   case GL_RED:
-   case GL_R8:
-      rb->Format = MESA_FORMAT_R8;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_R16:
-      rb->Format = MESA_FORMAT_R16;
-      rb->DataType = GL_UNSIGNED_SHORT;
-      break;
-   case GL_RG:
-   case GL_RG8:
-      rb->Format = MESA_FORMAT_RG88;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_RG16:
-      rb->Format = MESA_FORMAT_RG1616;
-      rb->DataType = GL_UNSIGNED_SHORT;
-      break;
-   case GL_R3_G3_B2:
-   case GL_RGB4:
-   case GL_RGB5:
-      rb->Format = MESA_FORMAT_RGB565;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_RGB:
-   case GL_RGB8:
-   case GL_RGB10:
-   case GL_RGB12:
-   case GL_RGB16:
-      rb->Format = MESA_FORMAT_XRGB8888;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_RGBA:
-   case GL_RGBA2:
-   case GL_RGBA4:
-   case GL_RGB5_A1:
-   case GL_RGBA8:
-   case GL_RGB10_A2:
-   case GL_RGBA12:
-   case GL_RGBA16:
-      rb->Format = MESA_FORMAT_ARGB8888;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_ALPHA:
-   case GL_ALPHA8:
-      rb->Format = MESA_FORMAT_A8;
-      rb->DataType = GL_UNSIGNED_BYTE;
-      break;
-   case GL_DEPTH_COMPONENT16:
-      rb->Format = MESA_FORMAT_Z16;
-      rb->DataType = GL_UNSIGNED_SHORT;
+   default:
+      /* Use the same format-choice logic as for textures.
+       * Renderbuffers aren't any different from textures for us,
+       * except they're less useful because you can't texture with
+       * them.
+       */
+      rb->Format = intelChooseTextureFormat(ctx, internalFormat,
+					    GL_NONE, GL_NONE);
       break;
    case GL_STENCIL_INDEX:
    case GL_STENCIL_INDEX1_EXT:
    case GL_STENCIL_INDEX4_EXT:
    case GL_STENCIL_INDEX8_EXT:
    case GL_STENCIL_INDEX16_EXT:
-   case GL_DEPTH_COMPONENT:
-   case GL_DEPTH_COMPONENT24:
-   case GL_DEPTH_COMPONENT32:
-   case GL_DEPTH_STENCIL_EXT:
-   case GL_DEPTH24_STENCIL8_EXT:
-      /* alloc a depth+stencil buffer */
+      /* These aren't actual texture formats, so force them here. */
       rb->Format = MESA_FORMAT_S8_Z24;
-      rb->DataType = GL_UNSIGNED_INT_24_8_EXT;
       break;
-   default:
-      _mesa_problem(ctx,
-                    "Unexpected format in intel_alloc_renderbuffer_storage");
-      return GL_FALSE;
    }
 
    rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
+   rb->DataType = intel_mesa_format_to_rb_datatype(rb->Format);
    cpp = _mesa_get_format_bytes(rb->Format);
 
    intel_flush(ctx);
@@ -338,39 +288,30 @@ intel_create_renderbuffer(gl_format format)
    switch (format) {
    case MESA_FORMAT_RGB565:
       irb->Base._BaseFormat = GL_RGB;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    case MESA_FORMAT_XRGB8888:
       irb->Base._BaseFormat = GL_RGB;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    case MESA_FORMAT_ARGB8888:
       irb->Base._BaseFormat = GL_RGBA;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    case MESA_FORMAT_Z16:
       irb->Base._BaseFormat = GL_DEPTH_COMPONENT;
-      irb->Base.DataType = GL_UNSIGNED_SHORT;
       break;
    case MESA_FORMAT_X8_Z24:
       irb->Base._BaseFormat = GL_DEPTH_COMPONENT;
-      irb->Base.DataType = GL_UNSIGNED_INT;
       break;
    case MESA_FORMAT_S8_Z24:
       irb->Base._BaseFormat = GL_DEPTH_STENCIL;
-      irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT;
       break;
    case MESA_FORMAT_A8:
       irb->Base._BaseFormat = GL_ALPHA;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    case MESA_FORMAT_R8:
       irb->Base._BaseFormat = GL_RED;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    case MESA_FORMAT_RG88:
       irb->Base._BaseFormat = GL_RG;
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
       break;
    default:
       _mesa_problem(NULL,
@@ -381,6 +322,7 @@ intel_create_renderbuffer(gl_format format)
 
    irb->Base.Format = format;
    irb->Base.InternalFormat = irb->Base._BaseFormat;
+   irb->Base.DataType = intel_mesa_format_to_rb_datatype(format);
 
    /* intel-specific methods */
    irb->Base.Delete = intel_delete_renderbuffer;
@@ -457,66 +399,16 @@ static GLboolean
 intel_update_wrapper(struct gl_context *ctx, struct intel_renderbuffer *irb, 
 		     struct gl_texture_image *texImage)
 {
-   if (texImage->TexFormat == MESA_FORMAT_ARGB8888) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to RGBA8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_XRGB8888) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to XGBA8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_SARGB8) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to SARGB8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_RGB565) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to RGB5 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to ARGB1555 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to ARGB4444 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_A8) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to A8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_R8) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to R8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_RG88) {
-      irb->Base.DataType = GL_UNSIGNED_BYTE;
-      DBG("Render to RG88 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_R16) {
-      irb->Base.DataType = GL_UNSIGNED_SHORT;
-      DBG("Render to R8 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_RG1616) {
-      irb->Base.DataType = GL_UNSIGNED_SHORT;
-      DBG("Render to RG88 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_Z16) {
-      irb->Base.DataType = GL_UNSIGNED_SHORT;
-      DBG("Render to DEPTH16 texture OK\n");
-   }
-   else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) {
-      irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT;
-      DBG("Render to DEPTH_STENCIL texture OK\n");
-   }
-   else {
+   if (!intel_span_supports_format(texImage->TexFormat)) {
       DBG("Render to texture BAD FORMAT %s\n",
 	  _mesa_get_format_name(texImage->TexFormat));
       return GL_FALSE;
+   } else {
+      DBG("Render to texture %s\n", _mesa_get_format_name(texImage->TexFormat));
    }
 
    irb->Base.Format = texImage->TexFormat;
-
+   irb->Base.DataType = intel_mesa_format_to_rb_datatype(texImage->TexFormat);
    irb->Base.InternalFormat = texImage->InternalFormat;
    irb->Base._BaseFormat = _mesa_base_fbo_format(ctx, irb->Base.InternalFormat);
    irb->Base.Width = texImage->Width;
@@ -707,20 +599,9 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
 	 continue;
       }
 
-      switch (irb->Base.Format) {
-      case MESA_FORMAT_ARGB8888:
-      case MESA_FORMAT_XRGB8888:
-      case MESA_FORMAT_SARGB8:
-      case MESA_FORMAT_RGB565:
-      case MESA_FORMAT_ARGB1555:
-      case MESA_FORMAT_ARGB4444:
-      case MESA_FORMAT_A8:
-      case MESA_FORMAT_R8:
-      case MESA_FORMAT_R16:
-      case MESA_FORMAT_RG88:
-      case MESA_FORMAT_RG1616:
-	 break;
-      default:
+      if (!intel_span_supports_format(irb->Base.Format)) {
+	 DBG("Unsupported texture/renderbuffer format attached: %s\n",
+	     _mesa_get_format_name(irb->Base.Format));
 	 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED_EXT;
       }
    }
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 061f0d278d..d683e67532 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -35,19 +35,6 @@
 #include "utils.h"
 #include "xmlpool.h"
 
-#include "intel_batchbuffer.h"
-#include "intel_buffers.h"
-#include "intel_bufmgr.h"
-#include "intel_chipset.h"
-#include "intel_fbo.h"
-#include "intel_screen.h"
-#include "intel_tex.h"
-#include "intel_regions.h"
-
-#include "i915_drm.h"
-
-#define DRI_CONF_TEXTURE_TILING(def) \
-
 PUBLIC const char __driConfigOptions[] =
    DRI_CONF_BEGIN
    DRI_CONF_SECTION_PERFORMANCE
@@ -92,6 +79,17 @@ DRI_CONF_END;
 
 const GLuint __driNConfigOptions = 11;
 
+#include "intel_batchbuffer.h"
+#include "intel_buffers.h"
+#include "intel_bufmgr.h"
+#include "intel_chipset.h"
+#include "intel_fbo.h"
+#include "intel_screen.h"
+#include "intel_tex.h"
+#include "intel_regions.h"
+
+#include "i915_drm.h"
+
 #ifdef USE_NEW_INTERFACE
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE */
@@ -452,7 +450,7 @@ intelCreateContext(gl_api api,
       return brwCreateContext(api, mesaVis,
 			      driContextPriv, sharedContextPrivate);
 #endif
-   fprintf(stderr, "Unrecognized deviceID %x\n", intelScreen->deviceID);
+   fprintf(stderr, "Unrecognized deviceID 0x%x\n", intelScreen->deviceID);
    return GL_FALSE;
 }
 
@@ -462,7 +460,8 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
    __DRIscreen *spriv = intelScreen->driScrnPriv;
    int num_fences = 0;
 
-   intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL;
+   intelScreen->no_hw = (getenv("INTEL_NO_HW") != NULL ||
+			 getenv("INTEL_DEVID_OVERRIDE") != NULL);
 
    intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ);
    if (intelScreen->bufmgr == NULL) {
@@ -497,6 +496,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
    GLenum fb_format[3];
    GLenum fb_type[3];
    unsigned int api_mask;
+   char *devid_override;
 
    static const GLenum back_buffer_modes[] = {
        GLX_NONE, GLX_SWAP_UNDEFINED_OML, GLX_SWAP_COPY_OML
@@ -523,6 +523,16 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
 			&intelScreen->deviceID))
       return GL_FALSE;
 
+   /* Allow an override of the device ID for the purpose of making the
+    * driver produce dumps for debugging of new chipset enablement.
+    * This implies INTEL_NO_HW, to avoid programming your actual GPU
+    * incorrectly.
+    */
+   devid_override = getenv("INTEL_DEVID_OVERRIDE");
+   if (devid_override) {
+      intelScreen->deviceID = strtod(devid_override, NULL);
+   }
+
    api_mask = (1 << __DRI_API_OPENGL);
 #if FEATURE_ES1
    api_mask |= (1 << __DRI_API_GLES);
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 104cadf0f9..1f41518535 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -25,6 +25,7 @@
  * 
  **************************************************************************/
 
+#include <stdbool.h>
 #include "main/glheader.h"
 #include "main/macros.h"
 #include "main/mtypes.h"
@@ -113,6 +114,26 @@ intel_set_span_functions(struct intel_context *intel,
 #define TAG2(x,y) intel_##x##y##_A8
 #include "spantmp2.h"
 
+#define SPANTMP_MESA_FMT MESA_FORMAT_R8
+#define TAG(x) intel_##x##_R8
+#define TAG2(x,y) intel_##x##y##_R8
+#include "spantmp2.h"
+
+#define SPANTMP_MESA_FMT MESA_FORMAT_RG88
+#define TAG(x) intel_##x##_RG88
+#define TAG2(x,y) intel_##x##y##_RG88
+#include "spantmp2.h"
+
+#define SPANTMP_MESA_FMT MESA_FORMAT_R16
+#define TAG(x) intel_##x##_R16
+#define TAG2(x,y) intel_##x##y##_R16
+#include "spantmp2.h"
+
+#define SPANTMP_MESA_FMT MESA_FORMAT_RG1616
+#define TAG(x) intel_##x##_RG1616
+#define TAG2(x,y) intel_##x##y##_RG1616
+#include "spantmp2.h"
+
 #define LOCAL_DEPTH_VARS						\
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);		\
    const GLint yScale = rb->Name ? 1 : -1;				\
@@ -339,6 +360,32 @@ intel_unmap_vertex_shader_textures(struct gl_context *ctx)
    }
 }
 
+typedef void (*span_init_func)(struct gl_renderbuffer *rb);
+
+static span_init_func intel_span_init_funcs[MESA_FORMAT_COUNT] =
+{
+   [MESA_FORMAT_A8] = intel_InitPointers_A8,
+   [MESA_FORMAT_RGB565] = intel_InitPointers_RGB565,
+   [MESA_FORMAT_ARGB4444] = intel_InitPointers_ARGB4444,
+   [MESA_FORMAT_ARGB1555] = intel_InitPointers_ARGB1555,
+   [MESA_FORMAT_XRGB8888] = intel_InitPointers_xRGB8888,
+   [MESA_FORMAT_ARGB8888] = intel_InitPointers_ARGB8888,
+   [MESA_FORMAT_SARGB8] = intel_InitPointers_ARGB8888,
+   [MESA_FORMAT_Z16] = intel_InitDepthPointers_z16,
+   [MESA_FORMAT_X8_Z24] = intel_InitDepthPointers_z24_s8,
+   [MESA_FORMAT_S8_Z24] = intel_InitDepthPointers_z24_s8,
+   [MESA_FORMAT_R8] = intel_InitPointers_R8,
+   [MESA_FORMAT_RG88] = intel_InitPointers_RG88,
+   [MESA_FORMAT_R16] = intel_InitPointers_R16,
+   [MESA_FORMAT_RG1616] = intel_InitPointers_RG1616,
+};
+
+bool
+intel_span_supports_format(gl_format format)
+{
+   return intel_span_init_funcs[format] != NULL;
+}
+
 /**
  * Plug in appropriate span read/write functions for the given renderbuffer.
  * These are used for the software fallbacks.
@@ -349,37 +396,6 @@ intel_set_span_functions(struct intel_context *intel,
 {
    struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb;
 
-   switch (irb->Base.Format) {
-   case MESA_FORMAT_A8:
-      intel_InitPointers_A8(rb);
-      break;
-   case MESA_FORMAT_RGB565:
-      intel_InitPointers_RGB565(rb);
-      break;
-   case MESA_FORMAT_ARGB4444:
-      intel_InitPointers_ARGB4444(rb);
-      break;
-   case MESA_FORMAT_ARGB1555:
-      intel_InitPointers_ARGB1555(rb);
-      break;
-   case MESA_FORMAT_XRGB8888:
-      intel_InitPointers_xRGB8888(rb);
-      break;
-   case MESA_FORMAT_ARGB8888:
-   case MESA_FORMAT_SARGB8:
-      intel_InitPointers_ARGB8888(rb);
-      break;
-   case MESA_FORMAT_Z16:
-      intel_InitDepthPointers_z16(rb);
-      break;
-   case MESA_FORMAT_X8_Z24:
-   case MESA_FORMAT_S8_Z24:
-      intel_InitDepthPointers_z24_s8(rb);
-      break;
-   default:
-      _mesa_problem(NULL,
-		    "Unexpected MesaFormat %d in intelSetSpanFunctions",
-		    irb->Base.Format);
-      break;
-   }
+   assert(intel_span_init_funcs[irb->Base.Format]);
+   intel_span_init_funcs[irb->Base.Format](rb);
 }
diff --git a/src/mesa/drivers/dri/intel/intel_span.h b/src/mesa/drivers/dri/intel/intel_span.h
index aa8d08e843..5a4c4e8e52 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -28,6 +28,9 @@
 #ifndef _INTEL_SPAN_H
 #define _INTEL_SPAN_H
 
+#include "main/formats.h"
+#include <stdbool.h>
+
 extern void intelInitSpanFuncs(struct gl_context * ctx);
 
 extern void intelSpanRenderFinish(struct gl_context * ctx);
@@ -38,5 +41,6 @@ void intel_renderbuffer_unmap(struct intel_context *intel,
 			      struct gl_renderbuffer *rb);
 void intel_map_vertex_shader_textures(struct gl_context *ctx);
 void intel_unmap_vertex_shader_textures(struct gl_context *ctx);
+bool intel_span_supports_format(gl_format format);
 
 #endif
diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h
index 7906554e45..b638628c71 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.h
+++ b/src/mesa/drivers/dri/intel/intel_tex.h
@@ -42,6 +42,7 @@ void intelInitTextureCopyImageFuncs(struct dd_function_table *functions);
 
 gl_format intelChooseTextureFormat(struct gl_context *ctx, GLint internalFormat,
                                    GLenum format, GLenum type);
+GLenum intel_mesa_format_to_rb_datatype(gl_format format);
 
 void intelSetTexBuffer(__DRIcontext *pDRICtx,
 		       GLint target, __DRIdrawable *pDraw);
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 284ba19e8a..c6bc3d962a 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -30,7 +30,6 @@
 #include "main/image.h"
 #include "main/teximage.h"
 #include "main/texstate.h"
-#include "main/mipmap.h"
 
 #include "drivers/common/meta.h"
 
@@ -51,44 +50,20 @@
  * Do the best we can using the blitter.  A future project is to use
  * the texture engine and fragment programs for these copies.
  */
-static const struct intel_region *
-get_teximage_source(struct intel_context *intel, GLenum internalFormat)
+static struct intel_renderbuffer *
+get_teximage_readbuffer(struct intel_context *intel, GLenum internalFormat)
 {
-   struct intel_renderbuffer *irb;
-
    DBG("%s %s\n", __FUNCTION__,
        _mesa_lookup_enum_by_nr(internalFormat));
 
    switch (internalFormat) {
    case GL_DEPTH_COMPONENT:
    case GL_DEPTH_COMPONENT16:
-      irb = intel_get_renderbuffer(intel->ctx.ReadBuffer, BUFFER_DEPTH);
-      if (irb && irb->region && irb->region->cpp == 2)
-         return irb->region;
-      return NULL;
    case GL_DEPTH24_STENCIL8_EXT:
    case GL_DEPTH_STENCIL_EXT:
-      irb = intel_get_renderbuffer(intel->ctx.ReadBuffer, BUFFER_DEPTH);
-      if (irb && irb->region && irb->region->cpp == 4)
-         return irb->region;
-      return NULL;
-   case 4:
-   case GL_RGBA:
-   case GL_RGBA8:
-      irb = intel_renderbuffer(intel->ctx.ReadBuffer->_ColorReadBuffer);
-      /* We're required to set alpha to 1.0 in this case, but we can't
-       * do that with the blitter, so fall back.  We could use the 3D
-       * engine or do two passes with the blitter, but it doesn't seem
-       * worth it for this case. */
-      if (irb->Base._BaseFormat == GL_RGB)
-	 return NULL;
-      return irb->region;
-   case 3:
-   case GL_RGB:
-   case GL_RGB8:
-      return intel_readbuf_region(intel);
+      return intel_get_renderbuffer(intel->ctx.ReadBuffer, BUFFER_DEPTH);
    default:
-      return NULL;
+      return intel_renderbuffer(intel->ctx.ReadBuffer->_ColorReadBuffer);
    }
 }
 
@@ -102,23 +77,34 @@ do_copy_texsubimage(struct intel_context *intel,
                     GLint x, GLint y, GLsizei width, GLsizei height)
 {
    struct gl_context *ctx = &intel->ctx;
-   const struct intel_region *src = get_teximage_source(intel, internalFormat);
+   struct intel_renderbuffer *irb;
+   bool copy_supported_with_alpha_override = false;
+
+   intel_prepare_render(intel);
 
-   if (!intelImage->mt || !src || !src->buffer) {
+   irb = get_teximage_readbuffer(intel, internalFormat);
+   if (!intelImage->mt || !irb || !irb->region) {
       if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS))
 	 fprintf(stderr, "%s fail %p %p (0x%08x)\n",
-		 __FUNCTION__, intelImage->mt, src, internalFormat);
+		 __FUNCTION__, intelImage->mt, irb, internalFormat);
       return GL_FALSE;
    }
 
-   if (intelImage->mt->cpp != src->cpp) {
-      fallback_debug("%s fail %d vs %d cpp\n",
-		     __FUNCTION__, intelImage->mt->cpp, src->cpp);
+   if (irb->Base.Format == MESA_FORMAT_XRGB8888 &&
+       intelImage->base.TexFormat == MESA_FORMAT_ARGB8888) {
+      copy_supported_with_alpha_override = true;
+   }
+
+   if (intelImage->base.TexFormat != irb->Base.Format &&
+       !copy_supported_with_alpha_override) {
+      if (unlikely(INTEL_DEBUG & DEBUG_FALLBACKS))
+	 fprintf(stderr, "%s mismatched formats %s, %s\n",
+		 __FUNCTION__,
+		 _mesa_get_format_name(intelImage->base.TexFormat),
+		 _mesa_get_format_name(irb->Base.Format));
       return GL_FALSE;
    }
 
-   /* intel_flush(ctx); */
-   intel_prepare_render(intel);
    {
       drm_intel_bo *dst_bo = intel_region_buffer(intel,
 						 intelImage->mt->region,
@@ -141,24 +127,24 @@ do_copy_texsubimage(struct intel_context *intel,
       if (ctx->ReadBuffer->Name == 0) {
 	 /* Flip vertical orientation for system framebuffers */
 	 y = ctx->ReadBuffer->Height - (y + height);
-	 src_pitch = -src->pitch;
+	 src_pitch = -irb->region->pitch;
       } else {
 	 /* reading from a FBO, y is already oriented the way we like */
-	 src_pitch = src->pitch;
+	 src_pitch = irb->region->pitch;
       }
 
       /* blit from src buffer to texture */
       if (!intelEmitCopyBlit(intel,
 			     intelImage->mt->cpp,
 			     src_pitch,
-			     src->buffer,
+			     irb->region->buffer,
 			     0,
-			     src->tiling,
+			     irb->region->tiling,
 			     intelImage->mt->region->pitch,
 			     dst_bo,
 			     0,
 			     intelImage->mt->region->tiling,
-			     src->draw_x + x, src->draw_y + y,
+			     irb->region->draw_x + x, irb->region->draw_y + y,
 			     image_x + dstx, image_y + dsty,
 			     width, height,
 			     GL_COPY)) {
@@ -166,6 +152,9 @@ do_copy_texsubimage(struct intel_context *intel,
       }
    }
 
+   if (copy_supported_with_alpha_override)
+      intel_set_teximage_alpha_to_one(ctx, intelImage);
+
    return GL_TRUE;
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c
index 9d73a2fb37..c9763c9ae1 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_format.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_format.c
@@ -4,6 +4,39 @@
 #include "main/formats.h"
 
 /**
+ * Returns the renderbuffer DataType for a MESA_FORMAT.
+ */
+GLenum
+intel_mesa_format_to_rb_datatype(gl_format format)
+{
+   switch (format) {
+   case MESA_FORMAT_ARGB8888:
+   case MESA_FORMAT_XRGB8888:
+   case MESA_FORMAT_SARGB8:
+   case MESA_FORMAT_R8:
+   case MESA_FORMAT_RG88:
+   case MESA_FORMAT_A8:
+   case MESA_FORMAT_AL88:
+   case MESA_FORMAT_RGB565:
+   case MESA_FORMAT_ARGB1555:
+   case MESA_FORMAT_ARGB4444:
+      return GL_UNSIGNED_BYTE;
+   case MESA_FORMAT_R16:
+   case MESA_FORMAT_RG1616:
+   case MESA_FORMAT_Z16:
+      return GL_UNSIGNED_SHORT;
+   case MESA_FORMAT_X8_Z24:
+      return GL_UNSIGNED_INT;
+   case MESA_FORMAT_S8_Z24:
+      return GL_UNSIGNED_INT_24_8_EXT;
+   default:
+      _mesa_problem(NULL, "unexpected MESA_FORMAT for renderbuffer");
+      return GL_UNSIGNED_BYTE;
+   }
+}
+
+
+/**
  * Choose hardware texture format given the user's glTexImage parameters.
  *
  * It works out that this function is fine for all the supported
@@ -204,11 +237,13 @@ intelChooseTextureFormat(struct gl_context * ctx, GLint internalFormat,
     * { R, G, 1.0, 1.0 } from a red-green texture would be useful.
     */
    case GL_RED:
+   case GL_COMPRESSED_RED:
    case GL_R8:
       return MESA_FORMAT_R8;
    case GL_R16:
       return MESA_FORMAT_R16;
    case GL_RG:
+   case GL_COMPRESSED_RG:
    case GL_RG8:
       return MESA_FORMAT_RG88;
    case GL_RG16:
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c
index 50fe9bd9f3..41cdbfd2cb 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -682,6 +682,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    struct gl_texture_object *texObj;
    struct gl_texture_image *texImage;
    int level = 0, internalFormat;
+   gl_format texFormat;
 
    texObj = _mesa_get_current_tex_object(ctx, target);
    intelObj = intel_texture_object(texObj);
@@ -700,10 +701,14 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
    if (rb->region == NULL)
       return;
 
-   if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
+   if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
       internalFormat = GL_RGB;
-   else
+      texFormat = MESA_FORMAT_XRGB8888;
+   }
+   else {
       internalFormat = GL_RGBA;
+      texFormat = MESA_FORMAT_ARGB8888;
+   }
 
    mt = intel_miptree_create_for_region(intel, target,
 					internalFormat,
@@ -724,16 +729,13 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
       intel_miptree_release(intel, &intelObj->mt);
 
    intelObj->mt = mt;
+
    _mesa_init_teximage_fields(&intel->ctx, target, texImage,
 			      rb->region->width, rb->region->height, 1,
-			      0, internalFormat);
+			      0, internalFormat, texFormat);
 
    intelImage->face = target_to_face(target);
    intelImage->level = level;
-   if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
-      texImage->TexFormat = MESA_FORMAT_XRGB8888;
-   else
-      texImage->TexFormat = MESA_FORMAT_ARGB8888;
    texImage->RowStride = rb->region->pitch;
    intel_miptree_reference(&intelImage->mt, intelObj->mt);
 
@@ -789,11 +791,10 @@ intel_image_target_texture_2d(struct gl_context *ctx, GLenum target,
    intelObj->mt = mt;
    _mesa_init_teximage_fields(&intel->ctx, target, texImage,
 			      image->region->width, image->region->height, 1,
-			      0, image->internal_format);
+			      0, image->internal_format, image->format);
 
    intelImage->face = target_to_face(target);
    intelImage->level = 0;
-   texImage->TexFormat = image->format;
    texImage->RowStride = image->region->pitch;
    intel_miptree_reference(&intelImage->mt, intelObj->mt);
 
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_class.h b/src/mesa/drivers/dri/nouveau/nouveau_class.h
deleted file mode 100644
index 687b847797..0000000000
--- a/src/mesa/drivers/dri/nouveau/nouveau_class.h
+++ /dev/null
@@ -1,4961 +0,0 @@
-/*************************************************************************
-
-   Autogenerated file, do not edit !
-
-   This file was generated by renouveau-gen from renouveau.xml, the
-   XML database of nvidia objects and methods. renouveau-gen and
-   renouveau.xml can be found in CVS module renouveau of sourceforge.net
-   project nouveau:
-
-cvs -z3 -d:pserver:anonymous@nouveau.cvs.sourceforge.net:/cvsroot/nouveau co -P renouveau
-
-**************************************************************************
-
-   Copyright (C) 2006-2008 :
-   Dmitry Baryshkov,
-   Laurent Carlier,
-   Matthieu Castet,
-   Dawid Gajownik,
-   Jeremy Kolb,
-   Stephane Loeuillet,
-   Patrice Mandin,
-   Stephane Marchesin,
-   Serge Martin,
-   Sylvain Munaut,
-   Simon Raffeiner,
-   Ben Skeggs,
-   Erik Waling,
-   koala_br,
-
-All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*************************************************************************/
-
-
-#ifndef NOUVEAU_REG_H
-#define NOUVEAU_REG_H 1
-
-
-#define NV01_ROOT									0x00000001
-
-
-
-#define NV01_CONTEXT_DMA								0x00000002
-
-
-
-#define NV01_DEVICE									0x00000003
-
-
-
-#define NV01_TIMER									0x00000004
-
-#define  NV01_TIMER_SYNCHRONIZE								0x00000100
-#define  NV01_TIMER_STOP_ALARM								0x00000104
-#define  NV01_TIMER_DMA_NOTIFY								0x00000180
-#define  NV01_TIMER_TIME(x)								(0x00000300+((x)*4))
-#define  NV01_TIMER_TIME__SIZE								0x00000002
-#define  NV01_TIMER_ALARM_NOTIFY							0x00000308
-
-
-#define NV01_CONTEXT_BETA1								0x00000012
-
-#define  NV01_CONTEXT_BETA1_NOP								0x00000100
-#define  NV01_CONTEXT_BETA1_NOTIFY							0x00000104
-#define  NV01_CONTEXT_BETA1_DMA_NOTIFY							0x00000180
-#define  NV01_CONTEXT_BETA1_BETA_1D31							0x00000300
-
-
-#define NV01_CONTEXT_COLOR_KEY								0x00000017
-
-#define  NV01_CONTEXT_COLOR_KEY_NOP							0x00000100
-#define  NV01_CONTEXT_COLOR_KEY_NOTIFY							0x00000104
-#define  NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY						0x00000180
-#define  NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT						0x00000300
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A8Y8					0x00000001
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X24Y8					0x00000002
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5				0x00000003
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X17R5G5B5					0x00000004
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8					0x00000005
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X8R8G8B8					0x00000006
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16Y16					0x00000007
-#define   NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16Y16					0x00000008
-#define  NV01_CONTEXT_COLOR_KEY_COLOR							0x00000304
-
-
-#define NV04_CONTEXT_COLOR_KEY								0x00000057
-
-
-
-#define NV01_CONTEXT_PATTERN								0x00000018
-
-#define  NV01_CONTEXT_PATTERN_NOP							0x00000100
-#define  NV01_CONTEXT_PATTERN_NOTIFY							0x00000104
-#define  NV01_CONTEXT_PATTERN_DMA_NOTIFY						0x00000180
-#define  NV01_CONTEXT_PATTERN_COLOR_FORMAT						0x00000300
-#define  NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT						0x00000304
-#define  NV01_CONTEXT_PATTERN_SHAPE							0x00000308
-#define  NV01_CONTEXT_PATTERN_COLOR(x)							(0x00000310+((x)*4))
-#define  NV01_CONTEXT_PATTERN_COLOR__SIZE						0x00000002
-#define  NV01_CONTEXT_PATTERN_PATTERN(x)						(0x00000318+((x)*4))
-#define  NV01_CONTEXT_PATTERN_PATTERN__SIZE						0x00000002
-
-
-#define NV01_CONTEXT_CLIP_RECTANGLE							0x00000019
-
-#define  NV01_CONTEXT_CLIP_RECTANGLE_NOP						0x00000100
-#define  NV01_CONTEXT_CLIP_RECTANGLE_NOTIFY						0x00000104
-#define  NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY						0x00000180
-#define  NV01_CONTEXT_CLIP_RECTANGLE_POINT						0x00000300
-#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_SHIFT					0
-#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_X_MASK					0x0000ffff
-#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_SHIFT					16
-#define   NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y_MASK					0xffff0000
-#define  NV01_CONTEXT_CLIP_RECTANGLE_SIZE						0x00000304
-#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_SHIFT					0
-#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W_MASK					0x0000ffff
-#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_SHIFT					16
-#define   NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H_MASK					0xffff0000
-
-
-#define NV01_RENDER_SOLID_LINE								0x0000001c
-
-#define  NV01_RENDER_SOLID_LINE_NOP							0x00000100
-#define  NV01_RENDER_SOLID_LINE_NOTIFY							0x00000104
-#define  NV01_RENDER_SOLID_LINE_PATCH							0x0000010c
-#define  NV01_RENDER_SOLID_LINE_DMA_NOTIFY						0x00000180
-#define  NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE						0x00000184
-#define  NV01_RENDER_SOLID_LINE_PATTERN							0x00000188
-#define  NV01_RENDER_SOLID_LINE_ROP							0x0000018c
-#define  NV01_RENDER_SOLID_LINE_BETA1							0x00000190
-#define  NV01_RENDER_SOLID_LINE_SURFACE							0x00000194
-#define  NV01_RENDER_SOLID_LINE_OPERATION						0x000002fc
-#define   NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND					0x00000000
-#define   NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND					0x00000001
-#define   NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND					0x00000002
-#define   NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY					0x00000003
-#define   NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT				0x00000004
-#define   NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT				0x00000005
-#define  NV01_RENDER_SOLID_LINE_COLOR_FORMAT						0x00000300
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A8Y8					0x00000001
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X24Y8					0x00000002
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5				0x00000003
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X17R5G5B5					0x00000004
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8					0x00000005
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X8R8G8B8					0x00000006
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16Y16					0x00000007
-#define   NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16Y16					0x00000008
-#define  NV01_RENDER_SOLID_LINE_COLOR							0x00000304
-#define  NV01_RENDER_SOLID_LINE_LINE_POINT0(x)						(0x00000400+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_LINE_POINT0__SIZE					0x00000010
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_X_SHIFT					0
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_X_MASK					0x0000ffff
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_SHIFT					16
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT0_Y_MASK					0xffff0000
-#define  NV01_RENDER_SOLID_LINE_LINE_POINT1(x)						(0x00000404+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_LINE_POINT1__SIZE					0x00000010
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_X_SHIFT					0
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_X_MASK					0x0000ffff
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_SHIFT					16
-#define   NV01_RENDER_SOLID_LINE_LINE_POINT1_Y_MASK					0xffff0000
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(x)					(0x00000480+((x)*16))
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__SIZE					0x00000010
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(x)					(0x00000484+((x)*16))
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__SIZE					0x00000010
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(x)					(0x00000488+((x)*16))
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__SIZE					0x00000010
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(x)					(0x0000048c+((x)*16))
-#define  NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__SIZE					0x00000010
-#define  NV01_RENDER_SOLID_LINE_POLYLINE(x)						(0x00000500+((x)*4))
-#define  NV01_RENDER_SOLID_LINE_POLYLINE__SIZE						0x00000020
-#define   NV01_RENDER_SOLID_LINE_POLYLINE_X_SHIFT					0
-#define   NV01_RENDER_SOLID_LINE_POLYLINE_X_MASK					0x0000ffff
-#define   NV01_RENDER_SOLID_LINE_POLYLINE_Y_SHIFT					16
-#define   NV01_RENDER_SOLID_LINE_POLYLINE_Y_MASK					0xffff0000
-#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(x)					(0x00000580+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__SIZE				0x00000010
-#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(x)					(0x00000584+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__SIZE				0x00000010
-#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(x)					(0x00000600+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__SIZE					0x00000010
-#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(x)					(0x00000604+((x)*8))
-#define  NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__SIZE					0x00000010
-#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_SHIFT				0
-#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X_MASK					0x0000ffff
-#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y_MASK					0xffff0000
-
-
-#define NV04_RENDER_SOLID_LINE								0x0000005c
-
-#define  NV04_RENDER_SOLID_LINE_BETA4							0x00000194
-#define  NV04_RENDER_SOLID_LINE_SURFACE							0x00000198
-
-
-#define NV01_RENDER_SOLID_TRIANGLE							0x0000001d
-
-#define  NV01_RENDER_SOLID_TRIANGLE_NOP							0x00000100
-#define  NV01_RENDER_SOLID_TRIANGLE_NOTIFY						0x00000104
-#define  NV01_RENDER_SOLID_TRIANGLE_PATCH						0x0000010c
-#define  NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY						0x00000180
-#define  NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE					0x00000184
-#define  NV01_RENDER_SOLID_TRIANGLE_PATTERN						0x00000188
-#define  NV01_RENDER_SOLID_TRIANGLE_ROP							0x0000018c
-#define  NV01_RENDER_SOLID_TRIANGLE_BETA1						0x00000190
-#define  NV01_RENDER_SOLID_TRIANGLE_SURFACE						0x00000194
-#define  NV01_RENDER_SOLID_TRIANGLE_OPERATION						0x000002fc
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND				0x00000000
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND					0x00000001
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND				0x00000002
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY					0x00000003
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT				0x00000004
-#define   NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT				0x00000005
-#define  NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT					0x00000300
-#define  NV01_RENDER_SOLID_TRIANGLE_COLOR						0x00000304
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0					0x00000310
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1					0x00000314
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2					0x00000318
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X					0x00000320
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y					0x00000324
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X					0x00000328
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y					0x0000032c
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X					0x00000330
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y					0x00000334
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH(x)						(0x00000400+((x)*4))
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH__SIZE					0x00000020
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_SHIFT					0
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X_MASK					0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_SHIFT					16
-#define   NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y_MASK					0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(x)				(0x00000480+((x)*8))
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__SIZE				0x00000010
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(x)				(0x00000484+((x)*8))
-#define  NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__SIZE				0x00000010
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(x)					(0x00000500+((x)*16))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__SIZE				0x00000008
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(x)					(0x00000504+((x)*16))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__SIZE				0x00000008
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(x)					(0x00000508+((x)*16))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__SIZE				0x00000008
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(x)					(0x0000050c+((x)*16))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__SIZE				0x00000008
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(x)					(0x00000580+((x)*8))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__SIZE				0x00000010
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(x)					(0x00000584+((x)*8))
-#define  NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__SIZE				0x00000010
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_SHIFT				0
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y_MASK				0xffff0000
-
-
-#define NV04_RENDER_SOLID_TRIANGLE							0x0000005d
-
-#define  NV04_RENDER_SOLID_TRIANGLE_BETA4						0x00000194
-#define  NV04_RENDER_SOLID_TRIANGLE_SURFACE						0x00000198
-
-
-#define NV01_RENDER_SOLID_RECTANGLE							0x0000001e
-
-#define  NV01_RENDER_SOLID_RECTANGLE_NOP						0x00000100
-#define  NV01_RENDER_SOLID_RECTANGLE_NOTIFY						0x00000104
-#define  NV01_RENDER_SOLID_RECTANGLE_PATCH						0x0000010c
-#define  NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY						0x00000180
-#define  NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE					0x00000184
-#define  NV01_RENDER_SOLID_RECTANGLE_PATTERN						0x00000188
-#define  NV01_RENDER_SOLID_RECTANGLE_ROP						0x0000018c
-#define  NV01_RENDER_SOLID_RECTANGLE_BETA1						0x00000190
-#define  NV01_RENDER_SOLID_RECTANGLE_SURFACE						0x00000194
-#define  NV01_RENDER_SOLID_RECTANGLE_OPERATION						0x000002fc
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND				0x00000000
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND					0x00000001
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND				0x00000002
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY					0x00000003
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT				0x00000004
-#define   NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT				0x00000005
-#define  NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT					0x00000300
-#define  NV01_RENDER_SOLID_RECTANGLE_COLOR						0x00000304
-#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(x)					(0x00000400+((x)*8))
-#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__SIZE				0x00000010
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_SHIFT				0
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_SHIFT				16
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y_MASK				0xffff0000
-#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(x)					(0x00000404+((x)*8))
-#define  NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__SIZE				0x00000010
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_SHIFT				0
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W_MASK				0x0000ffff
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_SHIFT				16
-#define   NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H_MASK				0xffff0000
-
-
-#define NV04_RENDER_SOLID_RECTANGLE							0x0000005e
-
-#define  NV04_RENDER_SOLID_RECTANGLE_BETA4						0x00000194
-#define  NV04_RENDER_SOLID_RECTANGLE_SURFACE						0x00000198
-
-
-#define NV01_IMAGE_BLIT									0x0000001f
-
-#define  NV01_IMAGE_BLIT_NOP								0x00000100
-#define  NV01_IMAGE_BLIT_NOTIFY								0x00000104
-#define  NV01_IMAGE_BLIT_PATCH								0x0000010c
-#define  NV01_IMAGE_BLIT_DMA_NOTIFY							0x00000180
-#define  NV01_IMAGE_BLIT_COLOR_KEY							0x00000184
-#define  NV01_IMAGE_BLIT_CLIP_RECTANGLE							0x00000188
-#define  NV01_IMAGE_BLIT_PATTERN							0x0000018c
-#define  NV01_IMAGE_BLIT_ROP								0x00000190
-#define  NV01_IMAGE_BLIT_BETA1								0x00000194
-#define  NV01_IMAGE_BLIT_SURFACE							0x0000019c
-#define  NV01_IMAGE_BLIT_OPERATION							0x000002fc
-#define   NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND						0x00000000
-#define   NV01_IMAGE_BLIT_OPERATION_ROP_AND						0x00000001
-#define   NV01_IMAGE_BLIT_OPERATION_BLEND_AND						0x00000002
-#define   NV01_IMAGE_BLIT_OPERATION_SRCCOPY						0x00000003
-#define   NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT					0x00000004
-#define   NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT					0x00000005
-#define  NV01_IMAGE_BLIT_IMAGE_INPUT							0x00000204
-#define  NV01_IMAGE_BLIT_POINT_IN							0x00000300
-#define   NV01_IMAGE_BLIT_POINT_IN_X_SHIFT						0
-#define   NV01_IMAGE_BLIT_POINT_IN_X_MASK						0x0000ffff
-#define   NV01_IMAGE_BLIT_POINT_IN_Y_SHIFT						16
-#define   NV01_IMAGE_BLIT_POINT_IN_Y_MASK						0xffff0000
-#define  NV01_IMAGE_BLIT_POINT_OUT							0x00000304
-#define   NV01_IMAGE_BLIT_POINT_OUT_X_SHIFT						0
-#define   NV01_IMAGE_BLIT_POINT_OUT_X_MASK						0x0000ffff
-#define   NV01_IMAGE_BLIT_POINT_OUT_Y_SHIFT						16
-#define   NV01_IMAGE_BLIT_POINT_OUT_Y_MASK						0xffff0000
-#define  NV01_IMAGE_BLIT_SIZE								0x00000308
-#define   NV01_IMAGE_BLIT_SIZE_W_SHIFT							0
-#define   NV01_IMAGE_BLIT_SIZE_W_MASK							0x0000ffff
-#define   NV01_IMAGE_BLIT_SIZE_H_SHIFT							16
-#define   NV01_IMAGE_BLIT_SIZE_H_MASK							0xffff0000
-
-
-#define NV04_IMAGE_BLIT									0x0000005f
-
-#define  NV04_IMAGE_BLIT_ROP								0x00000190
-#define  NV04_IMAGE_BLIT_BETA4								0x00000198
-#define  NV04_IMAGE_BLIT_SURFACE							0x0000019c
-
-
-#define NV12_IMAGE_BLIT									0x0000009f
-
-#define  NV12_IMAGE_BLIT_WAIT_FOR_IDLE							0x00000108
-
-
-#define NV01_IMAGE_FROM_CPU								0x00000021
-
-#define  NV01_IMAGE_FROM_CPU_NOP							0x00000100
-#define  NV01_IMAGE_FROM_CPU_NOTIFY							0x00000104
-#define  NV01_IMAGE_FROM_CPU_PATCH							0x0000010c
-#define  NV01_IMAGE_FROM_CPU_DMA_NOTIFY							0x00000180
-#define  NV01_IMAGE_FROM_CPU_COLOR_KEY							0x00000184
-#define  NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE						0x00000188
-#define  NV01_IMAGE_FROM_CPU_PATTERN							0x0000018c
-#define  NV01_IMAGE_FROM_CPU_ROP							0x00000190
-#define  NV01_IMAGE_FROM_CPU_BETA1							0x00000194
-#define  NV01_IMAGE_FROM_CPU_SURFACE							0x00000198
-#define  NV01_IMAGE_FROM_CPU_OPERATION							0x000002fc
-#define   NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND					0x00000000
-#define   NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND						0x00000001
-#define   NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND					0x00000002
-#define   NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY						0x00000003
-#define   NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT					0x00000004
-#define   NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT					0x00000005
-#define  NV01_IMAGE_FROM_CPU_COLOR_FORMAT						0x00000300
-#define   NV01_IMAGE_FROM_CPU_COLOR_FORMAT_Y8						0x00000001
-#define   NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5					0x00000002
-#define   NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5					0x00000003
-#define   NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8					0x00000004
-#define   NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8					0x00000005
-#define  NV01_IMAGE_FROM_CPU_POINT							0x00000304
-#define   NV01_IMAGE_FROM_CPU_POINT_X_SHIFT						0
-#define   NV01_IMAGE_FROM_CPU_POINT_X_MASK						0x0000ffff
-#define   NV01_IMAGE_FROM_CPU_POINT_Y_SHIFT						16
-#define   NV01_IMAGE_FROM_CPU_POINT_Y_MASK						0xffff0000
-#define  NV01_IMAGE_FROM_CPU_SIZE_OUT							0x00000308
-#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_W_SHIFT						0
-#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_W_MASK						0x0000ffff
-#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_H_SHIFT						16
-#define   NV01_IMAGE_FROM_CPU_SIZE_OUT_H_MASK						0xffff0000
-#define  NV01_IMAGE_FROM_CPU_SIZE_IN							0x0000030c
-#define   NV01_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT						0
-#define   NV01_IMAGE_FROM_CPU_SIZE_IN_W_MASK						0x0000ffff
-#define   NV01_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT						16
-#define   NV01_IMAGE_FROM_CPU_SIZE_IN_H_MASK						0xffff0000
-#define  NV01_IMAGE_FROM_CPU_COLOR(x)							(0x00000400+((x)*4))
-#define  NV01_IMAGE_FROM_CPU_COLOR__SIZE						0x00000020
-
-
-#define NV04_IMAGE_FROM_CPU								0x00000061
-
-#define  NV04_IMAGE_FROM_CPU_BETA4							0x00000198
-#define  NV04_IMAGE_FROM_CPU_SURFACE							0x0000019c
-
-
-#define NV05_IMAGE_FROM_CPU								0x00000065
-
-#define  NV05_IMAGE_FROM_CPU_COLOR_CONVERSION						0x000002f8
-
-
-#define NV10_IMAGE_FROM_CPU								0x0000008a
-
-#define  NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE						0x00000108
-
-
-#define NV30_IMAGE_FROM_CPU								0x0000038a
-
-
-
-#define NV40_IMAGE_FROM_CPU								0x0000308a
-
-
-
-#define NV01_NULL									0x00000030
-
-
-
-#define NV03_STRETCHED_IMAGE_FROM_CPU							0x00000036
-
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_NOP						0x00000100
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_NOTIFY						0x00000104
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_PATCH						0x0000010c
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY					0x00000180
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY					0x00000184
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN						0x00000188
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_ROP						0x0000018c
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_BETA1						0x00000190
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE						0x00000194
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION					0x000002fc
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT					0x00000300
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN						0x00000304
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_SHIFT					0
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W_MASK					0x0000ffff
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_SHIFT					16
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H_MASK					0xffff0000
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU						0x00000308
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV						0x0000030c
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT					0x00000310
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_SHIFT				0
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X_MASK				0x0000ffff
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_SHIFT				16
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y_MASK				0xffff0000
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE					0x00000314
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_SHIFT				0
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W_MASK				0x0000ffff
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_SHIFT				16
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H_MASK				0xffff0000
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4					0x00000318
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_SHIFT				0
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X_MASK				0x0000ffff
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_SHIFT				16
-#define   NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y_MASK				0xffff0000
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(x)						(0x00000400+((x)*4))
-#define  NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__SIZE					0x00000020
-
-
-#define NV04_STRETCHED_IMAGE_FROM_CPU							0x00000076
-
-#define  NV04_STRETCHED_IMAGE_FROM_CPU_BETA4						0x00000194
-#define  NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE						0x00000198
-
-
-#define NV05_STRETCHED_IMAGE_FROM_CPU							0x00000066
-
-#define  NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION					0x000002f8
-
-
-#define NV30_STRETCHED_IMAGE_FROM_CPU							0x00000366
-
-
-
-#define NV40_STRETCHED_IMAGE_FROM_CPU							0x00003066
-
-
-
-#define NV03_SCALED_IMAGE_FROM_MEMORY							0x00000037
-
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_NOP						0x00000100
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_NOTIFY						0x00000104
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY					0x00000180
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE					0x00000184
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN						0x00000188
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_ROP						0x0000018c
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_BETA1						0x00000190
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE						0x00000194
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT					0x00000300
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5				0x00000001
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5				0x00000002
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8				0x00000003
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8				0x00000004
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8				0x00000005
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8				0x00000006
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5				0x00000007
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8					0x00000008
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8				0x00000009
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION					0x00000304
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND				0x00000000
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND				0x00000001
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND				0x00000002
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY				0x00000003
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT			0x00000004
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT				0x00000005
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT					0x00000308
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_SHIFT				0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X_MASK				0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT				16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_MASK				0xffff0000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE					0x0000030c
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_SHIFT				0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W_MASK				0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT				16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_MASK				0xffff0000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT					0x00000310
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_SHIFT				0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X_MASK				0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT				16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_MASK				0xffff0000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE						0x00000314
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_SHIFT				0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W_MASK					0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT				16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_MASK					0xffff0000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX						0x00000318
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY						0x0000031c
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_SIZE						0x00000400
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_SHIFT					0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W_MASK					0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT					16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_MASK					0xffff0000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT						0x00000404
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_SHIFT				0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH_MASK				0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_SHIFT				16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_MASK				0x00ff0000
-#define    NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER				0x00010000
-#define    NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER				0x00020000
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_SHIFT				24
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_MASK				0xff000000
-#define    NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE			0x00000000
-#define    NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR				0x01000000
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET						0x00000408
-#define  NV03_SCALED_IMAGE_FROM_MEMORY_POINT						0x0000040c
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_SHIFT					0
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U_MASK					0x0000ffff
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_SHIFT					16
-#define   NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V_MASK					0xffff0000
-
-
-#define NV04_SCALED_IMAGE_FROM_MEMORY							0x00000077
-
-#define  NV04_SCALED_IMAGE_FROM_MEMORY_BETA4						0x00000194
-#define  NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE						0x00000198
-
-
-#define NV05_SCALED_IMAGE_FROM_MEMORY							0x00000063
-
-#define  NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION					0x000002fc
-#define   NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER				0x00000000
-#define   NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE			0x00000001
-#define   NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE			0x00000002
-
-
-#define NV10_SCALED_IMAGE_FROM_MEMORY							0x00000089
-
-#define  NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE					0x00000108
-
-
-#define NV30_SCALED_IMAGE_FROM_MEMORY							0x00000389
-
-
-
-#define NV40_SCALED_IMAGE_FROM_MEMORY							0x00003089
-
-
-
-#define NV04_DVD_SUBPICTURE								0x00000038
-
-#define  NV04_DVD_SUBPICTURE_NOP							0x00000100
-#define  NV04_DVD_SUBPICTURE_NOTIFY							0x00000104
-#define  NV04_DVD_SUBPICTURE_DMA_NOTIFY							0x00000180
-#define  NV04_DVD_SUBPICTURE_DMA_OVERLAY						0x00000184
-#define  NV04_DVD_SUBPICTURE_DMA_IMAGEIN						0x00000188
-#define  NV04_DVD_SUBPICTURE_DMA_IMAGEOUT						0x0000018c
-#define  NV04_DVD_SUBPICTURE_IMAGEOUT_POINT						0x00000300
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_X_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_POINT_Y_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE						0x00000304
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_W_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_SIZE_H_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT						0x00000308
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_SHIFT				0
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_PITCH_MASK				0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_SHIFT				16
-#define   NV04_DVD_SUBPICTURE_IMAGEOUT_FORMAT_COLOR_MASK				0xffff0000
-#define  NV04_DVD_SUBPICTURE_IMAGEOUT_OFFSET						0x0000030c
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DU_DX					0x00000310
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_DELTA_DV_DY					0x00000314
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_SIZE						0x00000318
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_W_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_SIZE_H_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT						0x0000031c
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_SHIFT				0
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_PITCH_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_SHIFT				16
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_FORMAT_COLOR_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_OFFSET						0x00000320
-#define  NV04_DVD_SUBPICTURE_IMAGEIN_POINT						0x00000324
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_U_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_IMAGEIN_POINT_V_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DU_DX					0x00000328
-#define  NV04_DVD_SUBPICTURE_OVERLAY_DELTA_DV_DY					0x0000032c
-#define  NV04_DVD_SUBPICTURE_OVERLAY_SIZE						0x00000330
-#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_W_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_OVERLAY_SIZE_H_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_OVERLAY_FORMAT						0x00000334
-#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_SHIFT				0
-#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_PITCH_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_SHIFT				16
-#define   NV04_DVD_SUBPICTURE_OVERLAY_FORMAT_COLOR_MASK					0xffff0000
-#define  NV04_DVD_SUBPICTURE_OVERLAY_OFFSET						0x00000338
-#define  NV04_DVD_SUBPICTURE_OVERLAY_POINT						0x0000033c
-#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_SHIFT					0
-#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_U_MASK					0x0000ffff
-#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_SHIFT					16
-#define   NV04_DVD_SUBPICTURE_OVERLAY_POINT_V_MASK					0xffff0000
-
-
-#define NV10_DVD_SUBPICTURE								0x00000088
-
-#define  NV10_DVD_SUBPICTURE_WAIT_FOR_IDLE						0x00000108
-
-
-#define NV04_MEMORY_TO_MEMORY_FORMAT							0x00000039
-
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_NOP						0x00000100
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_NOTIFY						0x00000104
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY					0x00000180
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN					0x00000184
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT					0x00000188
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN						0x0000030c
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT					0x00000310
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_IN						0x00000314
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT						0x00000318
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN					0x0000031c
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT					0x00000320
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT						0x00000324
-#define   NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_SHIFT				0
-#define   NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_INPUT_INC_MASK				0x000000ff
-#define   NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_SHIFT				8
-#define   NV04_MEMORY_TO_MEMORY_FORMAT_FORMAT_OUTPUT_INC_MASK				0x0000ff00
-#define  NV04_MEMORY_TO_MEMORY_FORMAT_BUF_NOTIFY					0x00000328
-
-
-#define NV50_MEMORY_TO_MEMORY_FORMAT							0x00005039
-
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_SERIALIZE						0x00000110
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN						0x00000200
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN					0x00000204
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN					0x00000208
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN					0x0000020c
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_IN					0x00000210
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Z				0x00000214
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN				0x00000218
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_SHIFT			0
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_X_MASK			0x0000ffff
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_SHIFT			16
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN_Y_MASK			0xffff0000
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT					0x0000021c
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT					0x00000220
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT					0x00000224
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT					0x00000228
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_DEPTH_OUT					0x0000022c
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Z				0x00000230
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT				0x00000234
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_SHIFT			0
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_X_MASK			0x0000ffff
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_SHIFT			16
-#define   NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT_Y_MASK			0xffff0000
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH					0x00000238
-#define  NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH					0x0000023c
-
-
-#define NV01_MEMORY_LOCAL_BANKED							0x0000003d
-
-
-
-#define NV01_MAPPING_SYSTEM								0x0000003e
-
-
-
-#define NV03_MEMORY_LOCAL_CURSOR							0x0000003f
-
-
-
-#define NV01_MEMORY_LOCAL_LINEAR							0x00000040
-
-
-
-#define NV01_MAPPING_LOCAL								0x00000041
-
-
-
-#define NV04_CONTEXT_SURFACES_2D							0x00000042
-
-#define  NV04_CONTEXT_SURFACES_2D_NOP							0x00000100
-#define  NV04_CONTEXT_SURFACES_2D_NOTIFY						0x00000104
-#define  NV04_CONTEXT_SURFACES_2D_PM_TRIGGER						0x00000140
-#define  NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY						0x00000180
-#define  NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE					0x00000184
-#define  NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN					0x00000188
-#define  NV04_CONTEXT_SURFACES_2D_FORMAT						0x00000300
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_Y8						0x00000001
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5				0x00000002
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5				0x00000003
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5					0x00000004
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_Y16						0x00000005
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8				0x00000006
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8				0x00000007
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8				0x00000008
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8				0x00000009
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8					0x0000000a
-#define   NV04_CONTEXT_SURFACES_2D_FORMAT_Y32						0x0000000b
-#define  NV04_CONTEXT_SURFACES_2D_PITCH							0x00000304
-#define   NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT					0
-#define   NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK					0x0000ffff
-#define   NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT					16
-#define   NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK					0xffff0000
-#define  NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE						0x00000308
-#define  NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN						0x0000030c
-
-
-#define NV10_CONTEXT_SURFACES_2D							0x00000062
-
-
-
-#define NV30_CONTEXT_SURFACES_2D							0x00000362
-
-
-
-#define NV40_CONTEXT_SURFACES_2D							0x00003062
-
-
-
-#define NV03_CONTEXT_ROP								0x00000043
-
-#define  NV03_CONTEXT_ROP_NOP								0x00000100
-#define  NV03_CONTEXT_ROP_NOTIFY							0x00000104
-#define  NV03_CONTEXT_ROP_DMA_NOTIFY							0x00000180
-#define  NV03_CONTEXT_ROP_ROP								0x00000300
-#define   NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SHIFT					0
-#define   NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_MASK					0x0000000f
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_CLEAR					0x00000000
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOR					0x00000001
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_INVERTED				0x00000002
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY_INVERTED				0x00000003
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND_REVERSE				0x00000004
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_INVERT					0x00000005
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_XOR					0x00000006
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NAND					0x00000007
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_AND					0x00000008
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_EQUI					0x00000009
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_NOOP					0x0000000a
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_INVERTED				0x0000000b
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_COPY					0x0000000c
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR_REVERSE					0x0000000d
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_OR						0x0000000e
-#define    NV03_CONTEXT_ROP_ROP_DST_LOGIC_OP_SET					0x0000000f
-#define   NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SHIFT					4
-#define   NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_MASK					0x000000f0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_CLEAR					0x00000000
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOR					0x00000010
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_INVERTED				0x00000020
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY_INVERTED				0x00000030
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND_REVERSE				0x00000040
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_INVERT					0x00000050
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_XOR					0x00000060
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NAND					0x00000070
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_AND					0x00000080
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_EQUI					0x00000090
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_NOOP					0x000000a0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_INVERTED				0x000000b0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_COPY					0x000000c0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR_REVERSE					0x000000d0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_OR						0x000000e0
-#define    NV03_CONTEXT_ROP_ROP_SRC_LOGIC_OP_SET					0x000000f0
-
-
-#define NV04_IMAGE_PATTERN								0x00000044
-
-#define  NV04_IMAGE_PATTERN_NOP								0x00000100
-#define  NV04_IMAGE_PATTERN_NOTIFY							0x00000104
-#define  NV04_IMAGE_PATTERN_DMA_NOTIFY							0x00000180
-#define  NV04_IMAGE_PATTERN_COLOR_FORMAT						0x00000300
-#define   NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5					0x00000001
-#define   NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5					0x00000002
-#define   NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8					0x00000003
-#define  NV04_IMAGE_PATTERN_MONOCHROME_FORMAT						0x00000304
-#define   NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6					0x00000001
-#define   NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE					0x00000002
-#define  NV04_IMAGE_PATTERN_MONOCHROME_SHAPE						0x00000308
-#define   NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8					0x00000000
-#define   NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1					0x00000001
-#define   NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64					0x00000002
-#define  NV04_IMAGE_PATTERN_PATTERN_SELECT						0x0000030c
-#define   NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO					0x00000001
-#define   NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR					0x00000002
-#define  NV04_IMAGE_PATTERN_MONOCHROME_COLOR0						0x00000310
-#define  NV04_IMAGE_PATTERN_MONOCHROME_COLOR1						0x00000314
-#define  NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0						0x00000318
-#define  NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1						0x0000031c
-#define  NV04_IMAGE_PATTERN_PATTERN_Y8(x)						(0x00000400+((x)*4))
-#define  NV04_IMAGE_PATTERN_PATTERN_Y8__SIZE						0x00000010
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_SHIFT					0
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y0_MASK						0x000000ff
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_SHIFT					8
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y1_MASK						0x0000ff00
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_SHIFT					16
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y2_MASK						0x00ff0000
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_SHIFT					24
-#define   NV04_IMAGE_PATTERN_PATTERN_Y8_Y3_MASK						0xff000000
-#define  NV04_IMAGE_PATTERN_PATTERN_R5G6B5(x)						(0x00000500+((x)*4))
-#define  NV04_IMAGE_PATTERN_PATTERN_R5G6B5__SIZE					0x00000020
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_SHIFT					0
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0_MASK					0x0000001f
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_SHIFT					5
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0_MASK					0x000007e0
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_SHIFT					11
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0_MASK					0x0000f800
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_SHIFT					16
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1_MASK					0x001f0000
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_SHIFT					21
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1_MASK					0x07e00000
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_SHIFT					27
-#define   NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1_MASK					0xf8000000
-#define  NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(x)						(0x00000600+((x)*4))
-#define  NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__SIZE					0x00000020
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_SHIFT					0
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0_MASK					0x0000001f
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_SHIFT					5
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0_MASK					0x000003e0
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_SHIFT					10
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0_MASK					0x00007c00
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_SHIFT					16
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1_MASK					0x001f0000
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_SHIFT					21
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1_MASK					0x03e00000
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_SHIFT					26
-#define   NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1_MASK					0x7c000000
-#define  NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(x)						(0x00000700+((x)*4))
-#define  NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__SIZE					0x00000040
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_SHIFT					0
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B_MASK					0x000000ff
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_SHIFT					8
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G_MASK					0x0000ff00
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_SHIFT					16
-#define   NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R_MASK					0x00ff0000
-
-
-#define NV03_VIDEO_LUT_CURSOR_DAC							0x00000046
-
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SYNCHRONIZE						0x00000100
-#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_IMAGE						0x00000104
-#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_CURSOR						0x00000108
-#define  NV03_VIDEO_LUT_CURSOR_DAC_STOP_DAC						0x0000010c
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_NOTIFY						0x00000180
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE(x)						(0x00000184+((x)*4))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_IMAGE__SIZE					0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT(x)						(0x0000018c+((x)*4))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_LUT__SIZE					0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR(x)					(0x00000194+((x)*4))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_DMA_CURSOR__SIZE					0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_GET							0x000002fc
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET(x)					(0x00000300+((x)*8))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_OFFSET__SIZE				0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT(x)					(0x00000304+((x)*8))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT__SIZE				0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_SHIFT			0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_PITCH_MASK				0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_SHIFT			16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_COLOR_MASK				0x0fff0000
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_SHIFT			28
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_IMAGE_FORMAT_NOTIFY_MASK			0xf0000000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET(x)					(0x00000340+((x)*12))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_OFFSET__SIZE				0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT(x)				(0x00000344+((x)*12))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT__SIZE				0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_SHIFT			0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_X_MASK				0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_SHIFT			16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_Y_MASK				0xffff0000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT(x)					(0x00000348+((x)*12))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_FORMAT__SIZE				0x00000002
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A				0x00000358
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_SHIFT			0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_X_MASK			0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_SHIFT			16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_CURSOR_POINT_OUT_A_Y_MASK			0xffff0000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE(x)				(0x00000380+((x)*16))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE__SIZE				0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_SHIFT				0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_W_MASK				0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_SHIFT				16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_IMAGE_SIZE_H_MASK				0xffff0000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC(x)					(0x00000384+((x)*16))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC__SIZE					0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_SHIFT				0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_START_MASK				0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_SHIFT				16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_WIDTH_MASK				0x0fff0000
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_SHIFT			28
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_HSYNC_POLARITY_MASK				0xf0000000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC(x)					(0x00000388+((x)*16))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC__SIZE					0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_SHIFT				0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_START_MASK				0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_SHIFT				16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_WIDTH_MASK				0x0fff0000
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_SHIFT			28
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_VSYNC_POLARITY_MASK				0xf0000000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE(x)				(0x0000038c+((x)*16))
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE__SIZE				0x00000002
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_SHIFT			0
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_WIDTH_MASK			0x0000ffff
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_SHIFT			16
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_HEIGHT_MASK			0x0fff0000
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_SHIFT			28
-#define   NV03_VIDEO_LUT_CURSOR_DAC_SET_DAC_TOTAL_SIZE_NOTIFY_MASK			0xf0000000
-#define  NV03_VIDEO_LUT_CURSOR_DAC_SET_PIXEL_CLOCK					0x000003a0
-
-
-#define NV03_TEXTURED_TRIANGLE								0x00000048
-
-#define  NV03_TEXTURED_TRIANGLE_NOP							0x00000100
-#define  NV03_TEXTURED_TRIANGLE_NOTIFY							0x00000104
-#define  NV03_TEXTURED_TRIANGLE_PATCH							0x0000010c
-#define  NV03_TEXTURED_TRIANGLE_DMA_NOTIFY						0x00000180
-#define  NV03_TEXTURED_TRIANGLE_DMA_TEXTURE						0x00000184
-#define  NV03_TEXTURED_TRIANGLE_CLIP_RECTANGLE						0x00000188
-#define  NV03_TEXTURED_TRIANGLE_SURFACE							0x0000018c
-#define  NV03_TEXTURED_TRIANGLE_TEXTURE_OFFSET						0x00000304
-#define  NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT						0x00000308
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_SHIFT			0
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_MASK_MASK			0x0000ffff
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_SHIFT			16
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_KEY_ENABLE_MASK			0x000f0000
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_SHIFT				20
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_COLOR_MASK				0x00f00000
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_SHIFT				24
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MIN_MASK				0x0f000000
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_SHIFT				28
-#define   NV03_TEXTURED_TRIANGLE_TEXTURE_FORMAT_SIZE_MAX_MASK				0xf0000000
-#define  NV03_TEXTURED_TRIANGLE_FILTER							0x0000030c
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_SHIFT					0
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_X_MASK					0x0000001f
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_SHIFT					8
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SPREAD_Y_MASK					0x00001f00
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_SHIFT				16
-#define   NV03_TEXTURED_TRIANGLE_FILTER_SIZE_ADJUST_MASK				0x00ff0000
-#define  NV03_TEXTURED_TRIANGLE_FOG_COLOR						0x00000310
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_SHIFT					0
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_B_MASK					0x000000ff
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_SHIFT					8
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_G_MASK					0x0000ff00
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_SHIFT					16
-#define   NV03_TEXTURED_TRIANGLE_FOG_COLOR_R_MASK					0x00ff0000
-#define  NV03_TEXTURED_TRIANGLE_CONTROL_OUT						0x00000314
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_SHIFT				0
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_INTERPOLATOR_MASK				0x0000000f
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_SHIFT				4
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_U_MASK				0x00000030
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_SHIFT				6
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_WRAP_V_MASK				0x000000c0
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_SHIFT				8
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SOURCE_COLOR_MASK				0x00000f00
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_SHIFT				12
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_CULLING_MASK				0x00007000
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_PERSPECTIVE_ENABLE			(1 << 15)
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_SHIFT				16
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_FUNC_MASK				0x000f0000
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_SHIFT			20
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_Z_WRITE_ENABLE_MASK			0x00f00000
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_SHIFT			24
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_COLOR_WRITE_ENABLE_MASK			0x07000000
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_SHIFT					27
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_ROP_MASK					0x18000000
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_BETA					(1 << 29)
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_DST_BLEND					(1 << 30)
-#define   NV03_TEXTURED_TRIANGLE_CONTROL_OUT_SRC_BLEND					(1 << 31)
-#define  NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL						0x00000318
-#define   NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_SHIFT				0
-#define   NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_REF_MASK				0x000000ff
-#define   NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_SHIFT				8
-#define   NV03_TEXTURED_TRIANGLE_ALPHA_CONTROL_ALPHA_FUNC_MASK				0xffffff00
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x)					(0x00001000+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE					0x00000080
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_SHIFT				0
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I0_MASK				0x0000000f
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_SHIFT				4
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I1_MASK				0x000000f0
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_SHIFT				8
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I2_MASK				0x00000f00
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_SHIFT				12
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I3_MASK				0x0000f000
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_SHIFT				16
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I4_MASK				0x000f0000
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_SHIFT				20
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_I5_MASK				0x00f00000
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT				24
-#define   NV03_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK				0xff000000
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x)					(0x00001004+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SX(x)						(0x00001008+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SY(x)						(0x0000100c+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ(x)						(0x00001010+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW(x)						(0x00001014+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_TU(x)						(0x00001018+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE					0x00000080
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_TV(x)						(0x0000101c+((x)*32))
-#define  NV03_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE					0x00000080
-
-
-#define NV04_GDI_RECTANGLE_TEXT								0x0000004a
-
-#define  NV04_GDI_RECTANGLE_TEXT_NOP							0x00000100
-#define  NV04_GDI_RECTANGLE_TEXT_NOTIFY							0x00000104
-#define  NV04_GDI_RECTANGLE_TEXT_PATCH							0x0000010c
-#define  NV04_GDI_RECTANGLE_TEXT_PM_TRIGGER						0x00000140
-#define  NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY						0x00000180
-#define  NV04_GDI_RECTANGLE_TEXT_DMA_FONTS						0x00000184
-#define  NV04_GDI_RECTANGLE_TEXT_PATTERN						0x00000188
-#define  NV04_GDI_RECTANGLE_TEXT_ROP							0x0000018c
-#define  NV04_GDI_RECTANGLE_TEXT_BETA1							0x00000190
-#define  NV04_GDI_RECTANGLE_TEXT_BETA4							0x00000194
-#define  NV04_GDI_RECTANGLE_TEXT_SURFACE						0x00000198
-#define  NV04_GDI_RECTANGLE_TEXT_OPERATION						0x000002fc
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND					0x00000000
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND					0x00000001
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND					0x00000002
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY					0x00000003
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT				0x00000004
-#define   NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT				0x00000005
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT						0x00000300
-#define   NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5				0x00000001
-#define   NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5				0x00000002
-#define   NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8					0x00000003
-#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT					0x00000304
-#define   NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6				0x00000001
-#define   NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE					0x00000002
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_A						0x000003fc
-#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(x)				(0x00000400+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__SIZE			0x00000020
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK			0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT			16
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK			0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(x)				(0x00000404+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__SIZE				0x00000020
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK			0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT			16
-#define   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK			0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0						0x000005f4
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1						0x000005f8
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_B						0x000005fc
-#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(x)				(0x00000600+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__SIZE			0x00000020
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK			0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT			16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK			0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(x)				(0x00000604+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__SIZE			0x00000020
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK			0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT			16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK			0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0						0x000007ec
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1						0x000007f0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_C						0x000007f4
-#define  NV04_GDI_RECTANGLE_TEXT_SIZE_C							0x000007f8
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK						0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK						0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_POINT_C						0x000007fc
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_X_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x)					(0x00000800+((x)*4))
-#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE				0x00000080
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0						0x00000be4
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1						0x00000be8
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR0_E						0x00000bec
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_E						0x00000bf0
-#define  NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E						0x00000bf4
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E						0x00000bf8
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_POINT_E						0x00000bfc
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_X_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x)				(0x00000c00+((x)*4))
-#define  NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE				0x00000080
-#define  NV04_GDI_RECTANGLE_TEXT_FONT_F							0x00000ff0
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET_MASK					0x0fffffff
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_SHIFT					28
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH_MASK					0xf0000000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0						0x00000ff4
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1						0x00000ff8
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_F						0x00000ffc
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(x)					(0x00001000+((x)*4))
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__SIZE				0x00000100
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX_MASK				0x000000ff
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_SHIFT				8
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X_MASK				0x000fff00
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_SHIFT				20
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y_MASK				0xfff00000
-#define  NV04_GDI_RECTANGLE_TEXT_FONT_G							0x000017f0
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET_MASK					0x0fffffff
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_SHIFT					28
-#define   NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH_MASK					0xf0000000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0						0x000017f4
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1						0x000017f8
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_SHIFT					0
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R_MASK					0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_SHIFT					16
-#define   NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B_MASK					0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_COLOR1_G						0x000017fc
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(x)				(0x00001800+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__SIZE				0x00000100
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_SHIFT			0
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X_MASK			0x0000ffff
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_SHIFT			16
-#define   NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y_MASK			0xffff0000
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(x)				(0x00001804+((x)*8))
-#define  NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__SIZE				0x00000100
-
-
-#define NV03_GDI_RECTANGLE_TEXT								0x0000004b
-
-#define  NV03_GDI_RECTANGLE_TEXT_NOP							0x00000100
-#define  NV03_GDI_RECTANGLE_TEXT_NOTIFY							0x00000104
-#define  NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY						0x00000180
-#define  NV03_GDI_RECTANGLE_TEXT_PATTERN						0x00000184
-#define  NV03_GDI_RECTANGLE_TEXT_ROP							0x00000188
-#define  NV03_GDI_RECTANGLE_TEXT_BETA1							0x0000018c
-#define  NV03_GDI_RECTANGLE_TEXT_SURFACE						0x00000190
-#define  NV03_GDI_RECTANGLE_TEXT_OPERATION						0x000002fc
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT						0x00000300
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT					0x00000304
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_A						0x000003fc
-#define  NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT				0x00000400
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_SHIFT			0
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y_MASK			0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_SHIFT			16
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X_MASK			0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE				0x00000404
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_SHIFT			0
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H_MASK			0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_SHIFT			16
-#define   NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W_MASK			0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B						0x000007f4
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B						0x000007f8
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_B						0x000007fc
-#define  NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0				0x00000800
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_SHIFT			0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L_MASK			0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_SHIFT			16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T_MASK			0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1				0x00000804
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_SHIFT			0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R_MASK			0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_SHIFT			16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B_MASK			0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0						0x00000bec
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1						0x00000bf0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_C						0x00000bf4
-#define  NV03_GDI_RECTANGLE_TEXT_SIZE_C							0x00000bf8
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_W_MASK						0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_C_H_MASK						0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_POINT_C						0x00000bfc
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_X_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_X_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_C_Y_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(x)					(0x00000c00+((x)*4))
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__SIZE				0x00000020
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0						0x00000fe8
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1						0x00000fec
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_D						0x00000ff0
-#define  NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D						0x00000ff4
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D						0x00000ff8
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_POINT_D						0x00000ffc
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_X_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_X_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_D_Y_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(x)					(0x00001000+((x)*4))
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__SIZE				0x00000020
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0						0x000013e4
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1						0x000013e8
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR0_E						0x000013ec
-#define  NV03_GDI_RECTANGLE_TEXT_COLOR1_E						0x000013f0
-#define  NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E						0x000013f4
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E						0x000013f8
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_POINT_E						0x000013fc
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_X_SHIFT					0
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_X_MASK					0x0000ffff
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_SHIFT					16
-#define   NV03_GDI_RECTANGLE_TEXT_POINT_E_Y_MASK					0xffff0000
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(x)				(0x00001400+((x)*4))
-#define  NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__SIZE				0x00000020
-
-
-#define NV04_SWIZZLED_SURFACE								0x00000052
-
-#define  NV04_SWIZZLED_SURFACE_NOP							0x00000100
-#define  NV04_SWIZZLED_SURFACE_NOTIFY							0x00000104
-#define  NV04_SWIZZLED_SURFACE_DMA_NOTIFY						0x00000180
-#define  NV04_SWIZZLED_SURFACE_DMA_IMAGE						0x00000184
-#define  NV04_SWIZZLED_SURFACE_FORMAT							0x00000300
-#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_SHIFT					0
-#define   NV04_SWIZZLED_SURFACE_FORMAT_COLOR_MASK					0x000000ff
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8					0x00000001
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5				0x00000002
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5				0x00000003
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5					0x00000004
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16					0x00000005
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8				0x00000006
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8				0x00000007
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8			0x00000008
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8			0x00000009
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8					0x0000000a
-#define    NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32					0x0000000b
-#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT				16
-#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_MASK					0x00ff0000
-#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT				24
-#define   NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_MASK					0xff000000
-#define  NV04_SWIZZLED_SURFACE_OFFSET							0x00000304
-
-
-#define NV20_SWIZZLED_SURFACE								0x0000009e
-
-
-
-#define NV30_SWIZZLED_SURFACE								0x0000039e
-
-
-
-#define NV40_SWIZZLED_SURFACE								0x0000309e
-
-
-
-#define NV04_CONTEXT_SURFACES_3D							0x00000053
-
-#define  NV04_CONTEXT_SURFACES_3D_NOP							0x00000100
-#define  NV04_CONTEXT_SURFACES_3D_NOTIFY						0x00000104
-#define  NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY						0x00000180
-#define  NV04_CONTEXT_SURFACES_3D_DMA_COLOR						0x00000184
-#define  NV04_CONTEXT_SURFACES_3D_DMA_ZETA						0x00000188
-#define  NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL					0x000002f8
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_SHIFT				0
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X_MASK				0x0000ffff
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_SHIFT				16
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W_MASK				0xffff0000
-#define  NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL						0x000002fc
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_SHIFT				0
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y_MASK					0x0000ffff
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_SHIFT				16
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H_MASK					0xffff0000
-#define  NV04_CONTEXT_SURFACES_3D_FORMAT						0x00000300
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_SHIFT					0
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_MASK					0x000000ff
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5			0x00000001
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5			0x00000002
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5					0x00000003
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8			0x00000004
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8			0x00000005
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8			0x00000006
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8			0x00000007
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8				0x00000008
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SHIFT					8
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_MASK					0x0000ff00
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH					0x00000100
-#define    NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE					0x00000200
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_SHIFT				16
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U_MASK				0x00ff0000
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_SHIFT				24
-#define   NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V_MASK				0xff000000
-#define  NV04_CONTEXT_SURFACES_3D_CLIP_SIZE						0x00000304
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_SHIFT					0
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W_MASK					0x0000ffff
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_SHIFT					16
-#define   NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H_MASK					0xffff0000
-#define  NV04_CONTEXT_SURFACES_3D_PITCH							0x00000308
-#define   NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_SHIFT					0
-#define   NV04_CONTEXT_SURFACES_3D_PITCH_COLOR_MASK					0x0000ffff
-#define   NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_SHIFT					16
-#define   NV04_CONTEXT_SURFACES_3D_PITCH_ZETA_MASK					0xffff0000
-#define  NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR						0x0000030c
-#define  NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA						0x00000310
-
-
-#define NV10_CONTEXT_SURFACES_3D							0x00000093
-
-
-
-#define NV04_TEXTURED_TRIANGLE								0x00000054
-
-#define  NV04_TEXTURED_TRIANGLE_NOP							0x00000100
-#define  NV04_TEXTURED_TRIANGLE_NOTIFY							0x00000104
-#define  NV04_TEXTURED_TRIANGLE_DMA_NOTIFY						0x00000180
-#define  NV04_TEXTURED_TRIANGLE_DMA_A							0x00000184
-#define  NV04_TEXTURED_TRIANGLE_DMA_B							0x00000188
-#define  NV04_TEXTURED_TRIANGLE_SURFACE							0x0000018c
-#define  NV04_TEXTURED_TRIANGLE_COLORKEY						0x00000300
-#define  NV04_TEXTURED_TRIANGLE_OFFSET							0x00000304
-#define  NV04_TEXTURED_TRIANGLE_FORMAT							0x00000308
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_DMA_A						(1 <<  0)
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_DMA_B						(1 <<  1)
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_SHIFT				2
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_MATCH_MASK				0x0000000c
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT				4
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK					0x00000030
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER				0x00000010
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER				0x00000020
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT				6
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_MASK					0x000000c0
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER				0x00000040
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER				0x00000080
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_SHIFT					8
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_MASK					0x00000f00
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8					0x00000100
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5					0x00000200
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5					0x00000300
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4					0x00000400
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5					0x00000500
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8					0x00000600
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8					0x00000700
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT				12
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK				0x0000f000
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT				16
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U_MASK				0x000f0000
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT				20
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V_MASK				0x00f00000
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_SHIFT					24
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MASK					0x07000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT				0x01000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT			0x02000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE				0x03000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER			0x04000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP					0x05000000
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_WRAPU						(1 << 27)
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_SHIFT					28
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MASK					0x70000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT				0x10000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT			0x20000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE				0x30000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER			0x40000000
-#define    NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP					0x50000000
-#define   NV04_TEXTURED_TRIANGLE_FORMAT_WRAPV						(1 << 31)
-#define  NV04_TEXTURED_TRIANGLE_FILTER							0x0000030c
-#define   NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT				0
-#define   NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK				0x000000ff
-#define   NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT				8
-#define   NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK				0x00007f00
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE				(1 << 15)
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT				16
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK				0x00ff0000
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_SHIFT					24
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_MASK					0x07000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST					0x01000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR					0x02000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST			0x03000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST			0x04000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR			0x05000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR			0x06000000
-#define   NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE			(1 << 27)
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_SHIFT					28
-#define   NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_MASK					0x70000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST				0x10000000
-#define    NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR					0x20000000
-#define   NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE			(1 << 31)
-#define  NV04_TEXTURED_TRIANGLE_BLEND							0x00000310
-#define   NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_SHIFT				0
-#define   NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MASK					0x0000000f
-#define   NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_SHIFT					4
-#define   NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MASK					0x00000030
-#define   NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_SHIFT					6
-#define   NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_MASK					0x000000c0
-#define    NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT					0x00000040
-#define    NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD				0x00000080
-#define    NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG				0x000000c0
-#define   NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE			(1 <<  8)
-#define   NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE					(1 << 12)
-#define   NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE					(1 << 16)
-#define   NV04_TEXTURED_TRIANGLE_BLEND_BLEND_ENABLE					(1 << 20)
-#define   NV04_TEXTURED_TRIANGLE_BLEND_SRC_SHIFT					24
-#define   NV04_TEXTURED_TRIANGLE_BLEND_SRC_MASK						0x0f000000
-#define   NV04_TEXTURED_TRIANGLE_BLEND_DST_SHIFT					28
-#define   NV04_TEXTURED_TRIANGLE_BLEND_DST_MASK						0xf0000000
-#define  NV04_TEXTURED_TRIANGLE_CONTROL							0x00000314
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_SHIFT				0
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF_MASK					0x000000ff
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT				8
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_MASK				0x00000f00
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE					(1 << 12)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN						(1 << 13)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE					(1 << 14)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_SHIFT					16
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_MASK					0x000f0000
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_SHIFT				20
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_MASK					0x00300000
-#define    NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_BOTH				0x00000000
-#define    NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_NONE				0x00100000
-#define    NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CW					0x00200000
-#define    NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW					0x00300000
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE					(1 << 22)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE				(1 << 23)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE					(1 << 24)
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_SHIFT					30
-#define   NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_MASK					0xc0000000
-#define  NV04_TEXTURED_TRIANGLE_FOGCOLOR						0x00000318
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_SHIFT					0
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_B_MASK					0x000000ff
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_SHIFT					8
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_G_MASK					0x0000ff00
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_SHIFT					16
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_R_MASK					0x00ff0000
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_SHIFT					24
-#define   NV04_TEXTURED_TRIANGLE_FOGCOLOR_A_MASK					0xff000000
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(x)						(0x00000400+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SX__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SY(x)						(0x00000404+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SY__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ(x)						(0x00000408+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW(x)						(0x0000040c+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR(x)					(0x00000410+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR__SIZE					0x00000010
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_SHIFT					0
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B_MASK					0x000000ff
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_SHIFT					8
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G_MASK					0x0000ff00
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_SHIFT					16
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R_MASK					0x00ff0000
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_SHIFT					24
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A_MASK					0xff000000
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(x)					(0x00000414+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR__SIZE					0x00000010
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_SHIFT				0
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B_MASK				0x000000ff
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_SHIFT				8
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G_MASK				0x0000ff00
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_SHIFT				16
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R_MASK				0x00ff0000
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_SHIFT				24
-#define   NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG_MASK				0xff000000
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_TU(x)						(0x00000418+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_TU__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_TV(x)						(0x0000041c+((x)*32))
-#define  NV04_TEXTURED_TRIANGLE_TLVERTEX_TV__SIZE					0x00000010
-#define  NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(x)					(0x00000600+((x)*4))
-#define  NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__SIZE					0x00000040
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT					0
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0_MASK					0x0000000f
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT					4
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1_MASK					0x000000f0
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT					8
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2_MASK					0x00000f00
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT					12
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3_MASK					0x0000f000
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT					16
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4_MASK					0x000f0000
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT					20
-#define   NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5_MASK					0x00f00000
-
-
-#define NV10_TEXTURED_TRIANGLE								0x00000094
-
-
-
-#define NV04_MULTITEX_TRIANGLE								0x00000055
-
-#define  NV04_MULTITEX_TRIANGLE_NOP							0x00000100
-#define  NV04_MULTITEX_TRIANGLE_NOTIFY							0x00000104
-#define  NV04_MULTITEX_TRIANGLE_DMA_NOTIFY						0x00000180
-#define  NV04_MULTITEX_TRIANGLE_DMA_A							0x00000184
-#define  NV04_MULTITEX_TRIANGLE_DMA_B							0x00000188
-#define  NV04_MULTITEX_TRIANGLE_SURFACE							0x0000018c
-#define  NV04_MULTITEX_TRIANGLE_OFFSET(x)						(0x00000308+((x)*4))
-#define  NV04_MULTITEX_TRIANGLE_OFFSET__SIZE						0x00000002
-#define  NV04_MULTITEX_TRIANGLE_FORMAT(x)						(0x00000310+((x)*4))
-#define  NV04_MULTITEX_TRIANGLE_FORMAT__SIZE						0x00000002
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_DMA_A						(1 <<  0)
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_DMA_B						(1 <<  1)
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_SHIFT				4
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_MASK					0x00000030
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_SHIFT				6
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_MASK					0x000000c0
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_SHIFT					8
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_MASK					0x00000f00
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_SHIFT				12
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS_MASK				0x0000f000
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_SHIFT				16
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U_MASK				0x000f0000
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_SHIFT				20
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V_MASK				0x00f00000
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_SHIFT					24
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MASK					0x07000000
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_WRAPU						(1 << 27)
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_SHIFT					28
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MASK					0x70000000
-#define   NV04_MULTITEX_TRIANGLE_FORMAT_WRAPV						(1 << 31)
-#define  NV04_MULTITEX_TRIANGLE_FILTER(x)						(0x00000318+((x)*4))
-#define  NV04_MULTITEX_TRIANGLE_FILTER__SIZE						0x00000002
-#define   NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_SHIFT				0
-#define   NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X_MASK				0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_SHIFT				8
-#define   NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y_MASK				0x00007f00
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE				(1 << 15)
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_SHIFT				16
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS_MASK				0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_SHIFT					24
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_MASK					0x07000000
-#define   NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE			(1 << 27)
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_SHIFT					28
-#define   NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_MASK					0x70000000
-#define   NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE			(1 << 31)
-#define  NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA(x)					(0x00000320+((x)*12))
-#define  NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__SIZE					0x00000002
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE0					(1 <<  0)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_SHIFT				2
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_MASK				0x000000fc
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_ZERO				0x00000004
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_CONSTANT			0x00000008
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PRIMARY_COLOR			0x0000000c
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PREVIOUS			0x00000010
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE0			0x00000014
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE1			0x00000018
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE1					(1 <<  8)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_SHIFT				10
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_MASK				0x0000fc00
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_ZERO				0x00000400
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_CONSTANT			0x00000800
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PRIMARY_COLOR			0x00000c00
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PREVIOUS			0x00001000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE0			0x00001400
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE1			0x00001800
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE2					(1 << 16)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_SHIFT				18
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_MASK				0x00fc0000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_ZERO				0x00040000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_CONSTANT			0x00080000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PRIMARY_COLOR			0x000c0000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PREVIOUS			0x00100000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE0			0x00140000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE1			0x00180000
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE3					(1 << 24)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_SHIFT				26
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_MASK				0x1c000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_ZERO				0x04000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_CONSTANT			0x08000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PRIMARY_COLOR			0x0c000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PREVIOUS			0x10000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE0			0x14000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE1			0x18000000
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SHIFT				29
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_MASK					0xe0000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_IDENTITY				0x20000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE2				0x40000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE4				0x60000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS				0x80000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS_SCALE2				0xe0000000
-#define  NV04_MULTITEX_TRIANGLE_COMBINE_COLOR(x)					(0x00000324+((x)*12))
-#define  NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__SIZE					0x00000002
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE0					(1 <<  0)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0					(1 <<  1)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_SHIFT				2
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_MASK				0x000000fc
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_ZERO				0x00000004
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_CONSTANT			0x00000008
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PRIMARY_COLOR			0x0000000c
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PREVIOUS			0x00000010
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE0			0x00000014
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE1			0x00000018
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE1					(1 <<  8)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA1					(1 <<  9)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_SHIFT				10
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_MASK				0x0000fc00
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_ZERO				0x00000400
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_CONSTANT			0x00000800
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PRIMARY_COLOR			0x00000c00
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PREVIOUS			0x00001000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE0			0x00001400
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE1			0x00001800
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE2					(1 << 16)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA2					(1 << 17)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_SHIFT				18
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_MASK				0x00fc0000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_ZERO				0x00040000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_CONSTANT			0x00080000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PRIMARY_COLOR			0x000c0000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PREVIOUS			0x00100000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE0			0x00140000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE1			0x00180000
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE3					(1 << 24)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA3					(1 << 25)
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_SHIFT				26
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_MASK				0x1c000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_ZERO				0x04000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_CONSTANT			0x08000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PRIMARY_COLOR			0x0c000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PREVIOUS			0x10000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE0			0x14000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE1			0x18000000
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SHIFT				29
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_MASK					0xe0000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_IDENTITY				0x20000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE2				0x40000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE4				0x60000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS				0x80000000
-#define    NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS_SCALE2				0xe0000000
-#define  NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR						0x00000334
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_SHIFT					0
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B_MASK					0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_SHIFT					8
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G_MASK					0x0000ff00
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_SHIFT					16
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R_MASK					0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_SHIFT					24
-#define   NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A_MASK					0xff000000
-#define  NV04_MULTITEX_TRIANGLE_BLEND							0x00000338
-#define   NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_SHIFT					4
-#define   NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MASK					0x00000030
-#define   NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_SHIFT					6
-#define   NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_MASK					0x000000c0
-#define    NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT					0x00000040
-#define    NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_GOURAUD				0x00000080
-#define    NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_PHONG				0x000000c0
-#define   NV04_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE			(1 <<  8)
-#define   NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE					(1 << 12)
-#define   NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE					(1 << 16)
-#define   NV04_MULTITEX_TRIANGLE_BLEND_BLEND_ENABLE					(1 << 20)
-#define   NV04_MULTITEX_TRIANGLE_BLEND_SRC_SHIFT					24
-#define   NV04_MULTITEX_TRIANGLE_BLEND_SRC_MASK						0x0f000000
-#define   NV04_MULTITEX_TRIANGLE_BLEND_DST_SHIFT					28
-#define   NV04_MULTITEX_TRIANGLE_BLEND_DST_MASK						0xf0000000
-#define  NV04_MULTITEX_TRIANGLE_CONTROL0						0x0000033c
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_SHIFT				0
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF_MASK				0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_SHIFT				8
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_MASK				0x00000f00
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_ENABLE					(1 << 12)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN					(1 << 13)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE					(1 << 14)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_SHIFT					16
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_MASK					0x000f0000
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_SHIFT				20
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_MASK				0x00300000
-#define    NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_BOTH				0x00000000
-#define    NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_NONE				0x00100000
-#define    NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CW					0x00200000
-#define    NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CCW				0x00300000
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE					(1 << 22)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE				(1 << 23)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE					(1 << 24)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE					(1 << 25)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE					(1 << 26)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE					(1 << 27)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE					(1 << 28)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE					(1 << 29)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_SHIFT				30
-#define   NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_MASK					0xc0000000
-#define  NV04_MULTITEX_TRIANGLE_CONTROL1						0x00000340
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE				(1 <<  0)
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_SHIFT				4
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC_MASK				0x000000f0
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_SHIFT				8
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF_MASK				0x0000ff00
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_SHIFT			16
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ_MASK			0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_SHIFT			24
-#define   NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE_MASK			0xff000000
-#define  NV04_MULTITEX_TRIANGLE_CONTROL2						0x00000344
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_SHIFT				0
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL_MASK				0x0000000f
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_SHIFT			4
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL_MASK				0x000000f0
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_SHIFT			8
-#define   NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS_MASK				0x00000f00
-#define  NV04_MULTITEX_TRIANGLE_FOGCOLOR						0x00000348
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_SHIFT					0
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_B_MASK					0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_SHIFT					8
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_G_MASK					0x0000ff00
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_SHIFT					16
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_R_MASK					0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_SHIFT					24
-#define   NV04_MULTITEX_TRIANGLE_FOGCOLOR_A_MASK					0xff000000
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX(x)					(0x00000400+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY(x)					(0x00000404+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(x)					(0x00000408+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(x)					(0x0000040c+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(x)					(0x00000410+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR__SIZE					0x00000008
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_SHIFT				0
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B_MASK				0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_SHIFT				8
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G_MASK				0x0000ff00
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_SHIFT				16
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R_MASK				0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_SHIFT				24
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A_MASK				0xff000000
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(x)					(0x00000414+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR__SIZE				0x00000008
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_SHIFT				0
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B_MASK				0x000000ff
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_SHIFT				8
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G_MASK				0x0000ff00
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_SHIFT				16
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R_MASK				0x00ff0000
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_SHIFT				24
-#define   NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG_MASK				0xff000000
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(x)					(0x00000418+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(x)					(0x0000041c+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(x)					(0x00000420+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(x)					(0x00000424+((x)*40))
-#define  NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1__SIZE					0x00000008
-#define  NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE(x)					(0x00000540+((x)*4))
-#define  NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__SIZE					0x00000030
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_SHIFT					0
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0_MASK					0x0000000f
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_SHIFT					4
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1_MASK					0x000000f0
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_SHIFT					8
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2_MASK					0x00000f00
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_SHIFT					12
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3_MASK					0x0000f000
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_SHIFT					16
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4_MASK					0x000f0000
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_SHIFT					20
-#define   NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5_MASK					0x00f00000
-
-
-#define NV10_MULTITEX_TRIANGLE								0x00000095
-
-
-
-#define NV10TCL										0x00000056
-
-#define  NV10TCL_NOP									0x00000100
-#define  NV10TCL_NOTIFY									0x00000104
-#define  NV10TCL_DMA_NOTIFY								0x00000180
-#define  NV10TCL_DMA_IN_MEMORY0								0x00000184
-#define  NV10TCL_DMA_IN_MEMORY1								0x00000188
-#define  NV10TCL_DMA_VTXBUF0								0x0000018c
-#define  NV10TCL_DMA_IN_MEMORY2								0x00000194
-#define  NV10TCL_DMA_IN_MEMORY3								0x00000198
-#define  NV10TCL_RT_HORIZ								0x00000200
-#define   NV10TCL_RT_HORIZ_X_SHIFT							0
-#define   NV10TCL_RT_HORIZ_X_MASK							0x0000ffff
-#define   NV10TCL_RT_HORIZ_W_SHIFT							16
-#define   NV10TCL_RT_HORIZ_W_MASK							0xffff0000
-#define  NV10TCL_RT_VERT								0x00000204
-#define   NV10TCL_RT_VERT_Y_SHIFT							0
-#define   NV10TCL_RT_VERT_Y_MASK							0x0000ffff
-#define   NV10TCL_RT_VERT_H_SHIFT							16
-#define   NV10TCL_RT_VERT_H_MASK							0xffff0000
-#define  NV10TCL_RT_FORMAT								0x00000208
-#define   NV10TCL_RT_FORMAT_TYPE_SHIFT							8
-#define   NV10TCL_RT_FORMAT_TYPE_MASK							0x00000f00
-#define    NV10TCL_RT_FORMAT_TYPE_LINEAR						0x00000100
-#define    NV10TCL_RT_FORMAT_TYPE_SWIZZLED						0x00000200
-#define   NV10TCL_RT_FORMAT_COLOR_SHIFT							0
-#define   NV10TCL_RT_FORMAT_COLOR_MASK							0x0000001f
-#define    NV10TCL_RT_FORMAT_COLOR_R5G6B5						0x00000003
-#define    NV10TCL_RT_FORMAT_COLOR_X8R8G8B8						0x00000005
-#define    NV10TCL_RT_FORMAT_COLOR_A8R8G8B8						0x00000008
-#define    NV10TCL_RT_FORMAT_COLOR_B8							0x00000009
-#define    NV10TCL_RT_FORMAT_COLOR_UNKNOWN						0x0000000d
-#define    NV10TCL_RT_FORMAT_COLOR_X8B8G8R8						0x0000000f
-#define    NV10TCL_RT_FORMAT_COLOR_A8B8G8R8						0x00000010
-#define  NV10TCL_RT_PITCH								0x0000020c
-#define   NV10TCL_RT_PITCH_COLOR_PITCH_SHIFT						0
-#define   NV10TCL_RT_PITCH_COLOR_PITCH_MASK						0x0000ffff
-#define   NV10TCL_RT_PITCH_ZETA_PITCH_SHIFT						16
-#define   NV10TCL_RT_PITCH_ZETA_PITCH_MASK						0xffff0000
-#define  NV10TCL_COLOR_OFFSET								0x00000210
-#define  NV10TCL_ZETA_OFFSET								0x00000214
-#define  NV10TCL_TX_OFFSET(x)								(0x00000218+((x)*4))
-#define  NV10TCL_TX_OFFSET__SIZE							0x00000002
-#define  NV10TCL_TX_FORMAT(x)								(0x00000220+((x)*4))
-#define  NV10TCL_TX_FORMAT__SIZE							0x00000002
-#define   NV10TCL_TX_FORMAT_DMA0							(1 <<  0)
-#define   NV10TCL_TX_FORMAT_DMA1							(1 <<  1)
-#define   NV10TCL_TX_FORMAT_CUBE_MAP							(1 <<  2)
-#define   NV10TCL_TX_FORMAT_FORMAT_SHIFT						7
-#define   NV10TCL_TX_FORMAT_FORMAT_MASK							0x00000f80
-#define    NV10TCL_TX_FORMAT_FORMAT_L8							0x00000000
-#define    NV10TCL_TX_FORMAT_FORMAT_A8							0x00000080
-#define    NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5						0x00000100
-#define    NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4						0x00000200
-#define    NV10TCL_TX_FORMAT_FORMAT_R5G6B5						0x00000280
-#define    NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8						0x00000300
-#define    NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8						0x00000380
-#define    NV10TCL_TX_FORMAT_FORMAT_INDEX8						0x00000580
-#define    NV10TCL_TX_FORMAT_FORMAT_DXT1						0x00000600
-#define    NV10TCL_TX_FORMAT_FORMAT_DXT3						0x00000700
-#define    NV10TCL_TX_FORMAT_FORMAT_DXT5						0x00000780
-#define    NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT					0x00000800
-#define    NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT						0x00000880
-#define    NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT					0x00000900
-#define    NV10TCL_TX_FORMAT_FORMAT_A8_RECT						0x00000980
-#define   NV10TCL_TX_FORMAT_MIPMAP							(1 << 15)
-#define   NV10TCL_TX_FORMAT_BASE_SIZE_U_SHIFT						16
-#define   NV10TCL_TX_FORMAT_BASE_SIZE_U_MASK						0x000f0000
-#define   NV10TCL_TX_FORMAT_BASE_SIZE_V_SHIFT						20
-#define   NV10TCL_TX_FORMAT_BASE_SIZE_V_MASK						0x00f00000
-#define   NV10TCL_TX_FORMAT_WRAP_S_SHIFT						24
-#define   NV10TCL_TX_FORMAT_WRAP_S_MASK							0x0f000000
-#define    NV10TCL_TX_FORMAT_WRAP_S_REPEAT						0x01000000
-#define    NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT					0x02000000
-#define    NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE					0x03000000
-#define    NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER					0x04000000
-#define    NV10TCL_TX_FORMAT_WRAP_S_CLAMP						0x05000000
-#define   NV10TCL_TX_FORMAT_WRAP_T_SHIFT						28
-#define   NV10TCL_TX_FORMAT_WRAP_T_MASK							0xf0000000
-#define    NV10TCL_TX_FORMAT_WRAP_T_REPEAT						0x10000000
-#define    NV10TCL_TX_FORMAT_WRAP_T_MIRRORED_REPEAT					0x20000000
-#define    NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_EDGE					0x30000000
-#define    NV10TCL_TX_FORMAT_WRAP_T_CLAMP_TO_BORDER					0x40000000
-#define    NV10TCL_TX_FORMAT_WRAP_T_CLAMP						0x50000000
-#define  NV10TCL_TX_ENABLE(x)								(0x00000228+((x)*4))
-#define  NV10TCL_TX_ENABLE__SIZE							0x00000002
-#define   NV10TCL_TX_ENABLE_CULL_SHIFT							0
-#define   NV10TCL_TX_ENABLE_CULL_MASK							0x0000000f
-#define    NV10TCL_TX_ENABLE_CULL_DISABLED						0x00000000
-#define    NV10TCL_TX_ENABLE_CULL_TEST_ALL						0x00000003
-#define    NV10TCL_TX_ENABLE_CULL_TEST_ALPHA						0x00000004
-#define   NV10TCL_TX_ENABLE_ANISOTROPY_SHIFT						4
-#define   NV10TCL_TX_ENABLE_ANISOTROPY_MASK						0x00000030
-#define   NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT					14
-#define   NV10TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK						0x0003c000
-#define   NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT					26
-#define   NV10TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK						0x3c000000
-#define   NV10TCL_TX_ENABLE_ENABLE							(1 << 30)
-#define  NV10TCL_TX_NPOT_PITCH(x)							(0x00000230+((x)*4))
-#define  NV10TCL_TX_NPOT_PITCH__SIZE							0x00000002
-#define   NV10TCL_TX_NPOT_PITCH_PITCH_SHIFT						16
-#define   NV10TCL_TX_NPOT_PITCH_PITCH_MASK						0xffff0000
-#define  NV10TCL_TX_NPOT_SIZE(x)							(0x00000240+((x)*4))
-#define  NV10TCL_TX_NPOT_SIZE__SIZE							0x00000002
-#define   NV10TCL_TX_NPOT_SIZE_H_SHIFT							0
-#define   NV10TCL_TX_NPOT_SIZE_H_MASK							0x0000ffff
-#define   NV10TCL_TX_NPOT_SIZE_W_SHIFT							16
-#define   NV10TCL_TX_NPOT_SIZE_W_MASK							0xffff0000
-#define  NV10TCL_TX_FILTER(x)								(0x00000248+((x)*4))
-#define  NV10TCL_TX_FILTER__SIZE							0x00000002
-#define   NV10TCL_TX_FILTER_LOD_BIAS_SHIFT						8
-#define   NV10TCL_TX_FILTER_LOD_BIAS_MASK						0x00000f00
-#define   NV10TCL_TX_FILTER_MINIFY_SHIFT						24
-#define   NV10TCL_TX_FILTER_MINIFY_MASK							0x0f000000
-#define    NV10TCL_TX_FILTER_MINIFY_NEAREST						0x01000000
-#define    NV10TCL_TX_FILTER_MINIFY_LINEAR						0x02000000
-#define    NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST				0x03000000
-#define    NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST				0x04000000
-#define    NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR				0x05000000
-#define    NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR				0x06000000
-#define   NV10TCL_TX_FILTER_MAGNIFY_SHIFT						28
-#define   NV10TCL_TX_FILTER_MAGNIFY_MASK						0xf0000000
-#define    NV10TCL_TX_FILTER_MAGNIFY_NEAREST						0x10000000
-#define    NV10TCL_TX_FILTER_MAGNIFY_LINEAR						0x20000000
-#define  NV10TCL_TX_PALETTE_OFFSET(x)							(0x00000250+((x)*4))
-#define  NV10TCL_TX_PALETTE_OFFSET__SIZE						0x00000002
-#define  NV10TCL_RC_IN_ALPHA(x)								(0x00000260+((x)*4))
-#define  NV10TCL_RC_IN_ALPHA__SIZE							0x00000002
-#define   NV10TCL_RC_IN_ALPHA_D_INPUT_SHIFT						0
-#define   NV10TCL_RC_IN_ALPHA_D_INPUT_MASK						0x0000000f
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_FOG						0x00000003
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0						0x00000008
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1						0x00000009
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0						0x0000000c
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE1						0x0000000d
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F					0x0000000f
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2						0x0000000a
-#define    NV10TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3						0x0000000b
-#define   NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV10TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV10TCL_RC_IN_ALPHA_D_MAPPING_SHIFT						5
-#define   NV10TCL_RC_IN_ALPHA_D_MAPPING_MASK						0x000000e0
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT				0x00000020
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL				0x00000080
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE				0x000000a0
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY				0x000000c0
-#define    NV10TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV10TCL_RC_IN_ALPHA_C_INPUT_SHIFT						8
-#define   NV10TCL_RC_IN_ALPHA_C_INPUT_MASK						0x00000f00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_FOG						0x00000300
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0						0x00000800
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1						0x00000900
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0						0x00000c00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE1						0x00000d00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F					0x00000f00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2						0x00000a00
-#define    NV10TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3						0x00000b00
-#define   NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE						(1 << 12)
-#define    NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV10TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV10TCL_RC_IN_ALPHA_C_MAPPING_SHIFT						13
-#define   NV10TCL_RC_IN_ALPHA_C_MAPPING_MASK						0x0000e000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT				0x00002000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL				0x00008000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE				0x0000a000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY				0x0000c000
-#define    NV10TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV10TCL_RC_IN_ALPHA_B_INPUT_SHIFT						16
-#define   NV10TCL_RC_IN_ALPHA_B_INPUT_MASK						0x000f0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_FOG						0x00030000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0						0x00080000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1						0x00090000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0						0x000c0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE1						0x000d0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F					0x000f0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2						0x000a0000
-#define    NV10TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3						0x000b0000
-#define   NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE						(1 << 20)
-#define    NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV10TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV10TCL_RC_IN_ALPHA_B_MAPPING_SHIFT						21
-#define   NV10TCL_RC_IN_ALPHA_B_MAPPING_MASK						0x00e00000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT				0x00200000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL				0x00800000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE				0x00a00000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY				0x00c00000
-#define    NV10TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV10TCL_RC_IN_ALPHA_A_INPUT_SHIFT						24
-#define   NV10TCL_RC_IN_ALPHA_A_INPUT_MASK						0x0f000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_FOG						0x03000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0						0x08000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1						0x09000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0						0x0c000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE1						0x0d000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F					0x0f000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2						0x0a000000
-#define    NV10TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3						0x0b000000
-#define   NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE						(1 << 28)
-#define    NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV10TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV10TCL_RC_IN_ALPHA_A_MAPPING_SHIFT						29
-#define   NV10TCL_RC_IN_ALPHA_A_MAPPING_MASK						0xe0000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT				0x20000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL				0x80000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE				0xa0000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY				0xc0000000
-#define    NV10TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV10TCL_RC_IN_RGB(x)								(0x00000268+((x)*4))
-#define  NV10TCL_RC_IN_RGB__SIZE							0x00000002
-#define   NV10TCL_RC_IN_RGB_D_INPUT_SHIFT						0
-#define   NV10TCL_RC_IN_RGB_D_INPUT_MASK						0x0000000f
-#define    NV10TCL_RC_IN_RGB_D_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV10TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV10TCL_RC_IN_RGB_D_INPUT_FOG						0x00000003
-#define    NV10TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV10TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE0						0x00000008
-#define    NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE1						0x00000009
-#define    NV10TCL_RC_IN_RGB_D_INPUT_SPARE0						0x0000000c
-#define    NV10TCL_RC_IN_RGB_D_INPUT_SPARE1						0x0000000d
-#define    NV10TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV10TCL_RC_IN_RGB_D_INPUT_E_TIMES_F						0x0000000f
-#define    NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE2						0x0000000a
-#define    NV10TCL_RC_IN_RGB_D_INPUT_TEXTURE3						0x0000000b
-#define   NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV10TCL_RC_IN_RGB_D_MAPPING_SHIFT						5
-#define   NV10TCL_RC_IN_RGB_D_MAPPING_MASK						0x000000e0
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT					0x00000020
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL					0x00000080
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE					0x000000a0
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY					0x000000c0
-#define    NV10TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV10TCL_RC_IN_RGB_C_INPUT_SHIFT						8
-#define   NV10TCL_RC_IN_RGB_C_INPUT_MASK						0x00000f00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV10TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV10TCL_RC_IN_RGB_C_INPUT_FOG						0x00000300
-#define    NV10TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV10TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE0						0x00000800
-#define    NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE1						0x00000900
-#define    NV10TCL_RC_IN_RGB_C_INPUT_SPARE0						0x00000c00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_SPARE1						0x00000d00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_E_TIMES_F						0x00000f00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE2						0x00000a00
-#define    NV10TCL_RC_IN_RGB_C_INPUT_TEXTURE3						0x00000b00
-#define   NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE						(1 << 12)
-#define    NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV10TCL_RC_IN_RGB_C_MAPPING_SHIFT						13
-#define   NV10TCL_RC_IN_RGB_C_MAPPING_MASK						0x0000e000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV10TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV10TCL_RC_IN_RGB_B_INPUT_SHIFT						16
-#define   NV10TCL_RC_IN_RGB_B_INPUT_MASK						0x000f0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_FOG						0x00030000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE0						0x00080000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE1						0x00090000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_SPARE0						0x000c0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_SPARE1						0x000d0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_E_TIMES_F						0x000f0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE2						0x000a0000
-#define    NV10TCL_RC_IN_RGB_B_INPUT_TEXTURE3						0x000b0000
-#define   NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE						(1 << 20)
-#define    NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV10TCL_RC_IN_RGB_B_MAPPING_SHIFT						21
-#define   NV10TCL_RC_IN_RGB_B_MAPPING_MASK						0x00e00000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV10TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV10TCL_RC_IN_RGB_A_INPUT_SHIFT						24
-#define   NV10TCL_RC_IN_RGB_A_INPUT_MASK						0x0f000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_FOG						0x03000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE0						0x08000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE1						0x09000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_SPARE0						0x0c000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_SPARE1						0x0d000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_E_TIMES_F						0x0f000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE2						0x0a000000
-#define    NV10TCL_RC_IN_RGB_A_INPUT_TEXTURE3						0x0b000000
-#define   NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE						(1 << 28)
-#define    NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV10TCL_RC_IN_RGB_A_MAPPING_SHIFT						29
-#define   NV10TCL_RC_IN_RGB_A_MAPPING_MASK						0xe0000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV10TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV10TCL_RC_COLOR(x)								(0x00000270+((x)*4))
-#define  NV10TCL_RC_COLOR__SIZE								0x00000002
-#define   NV10TCL_RC_COLOR_B_SHIFT							0
-#define   NV10TCL_RC_COLOR_B_MASK							0x000000ff
-#define   NV10TCL_RC_COLOR_G_SHIFT							8
-#define   NV10TCL_RC_COLOR_G_MASK							0x0000ff00
-#define   NV10TCL_RC_COLOR_R_SHIFT							16
-#define   NV10TCL_RC_COLOR_R_MASK							0x00ff0000
-#define   NV10TCL_RC_COLOR_A_SHIFT							24
-#define   NV10TCL_RC_COLOR_A_MASK							0xff000000
-#define  NV10TCL_RC_OUT_ALPHA(x)							(0x00000278+((x)*4))
-#define  NV10TCL_RC_OUT_ALPHA__SIZE							0x00000002
-#define   NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT						0
-#define   NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK						0x0000000f
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0				0x00000001
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1				0x00000002
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG						0x00000003
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR					0x00000004
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR				0x00000005
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0					0x00000008
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1					0x00000009
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0					0x0000000c
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1					0x0000000d
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F					0x0000000f
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2					0x0000000a
-#define    NV10TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3					0x0000000b
-#define   NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT						4
-#define   NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK						0x000000f0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0				0x00000010
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1				0x00000020
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG						0x00000030
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR					0x00000040
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR				0x00000050
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0					0x00000080
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1					0x00000090
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0					0x000000c0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1					0x000000d0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000000e0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F					0x000000f0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2					0x000000a0
-#define    NV10TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3					0x000000b0
-#define   NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT						8
-#define   NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK						0x00000f00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0				0x00000100
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1				0x00000200
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG						0x00000300
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR				0x00000400
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR				0x00000500
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0					0x00000800
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1					0x00000900
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0					0x00000c00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1					0x00000d00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F					0x00000f00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2					0x00000a00
-#define    NV10TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3					0x00000b00
-#define   NV10TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT						(1 << 12)
-#define   NV10TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT						(1 << 13)
-#define   NV10TCL_RC_OUT_ALPHA_MUX_SUM							(1 << 14)
-#define   NV10TCL_RC_OUT_ALPHA_BIAS							(1 << 15)
-#define    NV10TCL_RC_OUT_ALPHA_BIAS_NONE						0x00000000
-#define    NV10TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF				0x00008000
-#define   NV10TCL_RC_OUT_ALPHA_SCALE_SHIFT						16
-#define   NV10TCL_RC_OUT_ALPHA_SCALE_MASK						0x00030000
-#define    NV10TCL_RC_OUT_ALPHA_SCALE_NONE						0x00000000
-#define    NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO					0x00010000
-#define    NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR					0x00020000
-#define    NV10TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF					0x00030000
-#define  NV10TCL_RC_OUT_RGB(x)								(0x00000280+((x)*4))
-#define  NV10TCL_RC_OUT_RGB__SIZE							0x00000002
-#define   NV10TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT						0
-#define   NV10TCL_RC_OUT_RGB_CD_OUTPUT_MASK						0x0000000f
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0					0x00000001
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1					0x00000002
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_FOG						0x00000003
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR					0x00000004
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR					0x00000005
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0					0x00000008
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1					0x00000009
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0						0x0000000c
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1						0x0000000d
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F					0x0000000f
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2					0x0000000a
-#define    NV10TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3					0x0000000b
-#define   NV10TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT						4
-#define   NV10TCL_RC_OUT_RGB_AB_OUTPUT_MASK						0x000000f0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0					0x00000010
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1					0x00000020
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_FOG						0x00000030
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR					0x00000040
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR					0x00000050
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0					0x00000080
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1					0x00000090
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0						0x000000c0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1						0x000000d0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000000e0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F					0x000000f0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2					0x000000a0
-#define    NV10TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3					0x000000b0
-#define   NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT						8
-#define   NV10TCL_RC_OUT_RGB_SUM_OUTPUT_MASK						0x00000f00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO						0x00000000
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0				0x00000100
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1				0x00000200
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_FOG						0x00000300
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR					0x00000400
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR				0x00000500
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0					0x00000800
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1					0x00000900
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0						0x00000c00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1						0x00000d00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F					0x00000f00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2					0x00000a00
-#define    NV10TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3					0x00000b00
-#define   NV10TCL_RC_OUT_RGB_CD_DOT_PRODUCT						(1 << 12)
-#define   NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT						(1 << 13)
-#define   NV10TCL_RC_OUT_RGB_MUX_SUM							(1 << 14)
-#define   NV10TCL_RC_OUT_RGB_BIAS							(1 << 15)
-#define    NV10TCL_RC_OUT_RGB_BIAS_NONE							0x00000000
-#define    NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF				0x00008000
-#define   NV10TCL_RC_OUT_RGB_SCALE_SHIFT						16
-#define   NV10TCL_RC_OUT_RGB_SCALE_MASK							0x00030000
-#define    NV10TCL_RC_OUT_RGB_SCALE_NONE						0x00000000
-#define    NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO					0x00010000
-#define    NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR					0x00020000
-#define    NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF					0x00030000
-#define   NV10TCL_RC_OUT_RGB_OPERATION_SHIFT						27
-#define   NV10TCL_RC_OUT_RGB_OPERATION_MASK						0x38000000
-#define  NV10TCL_RC_FINAL0								0x00000288
-#define   NV10TCL_RC_FINAL0_D_INPUT_SHIFT						0
-#define   NV10TCL_RC_FINAL0_D_INPUT_MASK						0x0000000f
-#define    NV10TCL_RC_FINAL0_D_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV10TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV10TCL_RC_FINAL0_D_INPUT_FOG						0x00000003
-#define    NV10TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV10TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV10TCL_RC_FINAL0_D_INPUT_TEXTURE0						0x00000008
-#define    NV10TCL_RC_FINAL0_D_INPUT_TEXTURE1						0x00000009
-#define    NV10TCL_RC_FINAL0_D_INPUT_SPARE0						0x0000000c
-#define    NV10TCL_RC_FINAL0_D_INPUT_SPARE1						0x0000000d
-#define    NV10TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV10TCL_RC_FINAL0_D_INPUT_E_TIMES_F						0x0000000f
-#define    NV10TCL_RC_FINAL0_D_INPUT_TEXTURE2						0x0000000a
-#define    NV10TCL_RC_FINAL0_D_INPUT_TEXTURE3						0x0000000b
-#define   NV10TCL_RC_FINAL0_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV10TCL_RC_FINAL0_D_MAPPING_SHIFT						5
-#define   NV10TCL_RC_FINAL0_D_MAPPING_MASK						0x000000e0
-#define    NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT					0x00000020
-#define    NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV10TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL					0x00000080
-#define    NV10TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE					0x000000a0
-#define    NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY					0x000000c0
-#define    NV10TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV10TCL_RC_FINAL0_C_INPUT_SHIFT						8
-#define   NV10TCL_RC_FINAL0_C_INPUT_MASK						0x00000f00
-#define    NV10TCL_RC_FINAL0_C_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV10TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV10TCL_RC_FINAL0_C_INPUT_FOG						0x00000300
-#define    NV10TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV10TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV10TCL_RC_FINAL0_C_INPUT_TEXTURE0						0x00000800
-#define    NV10TCL_RC_FINAL0_C_INPUT_TEXTURE1						0x00000900
-#define    NV10TCL_RC_FINAL0_C_INPUT_SPARE0						0x00000c00
-#define    NV10TCL_RC_FINAL0_C_INPUT_SPARE1						0x00000d00
-#define    NV10TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_FINAL0_C_INPUT_E_TIMES_F						0x00000f00
-#define    NV10TCL_RC_FINAL0_C_INPUT_TEXTURE2						0x00000a00
-#define    NV10TCL_RC_FINAL0_C_INPUT_TEXTURE3						0x00000b00
-#define   NV10TCL_RC_FINAL0_C_COMPONENT_USAGE						(1 << 12)
-#define    NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV10TCL_RC_FINAL0_C_MAPPING_SHIFT						13
-#define   NV10TCL_RC_FINAL0_C_MAPPING_MASK						0x0000e000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV10TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV10TCL_RC_FINAL0_B_INPUT_SHIFT						16
-#define   NV10TCL_RC_FINAL0_B_INPUT_MASK						0x000f0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV10TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV10TCL_RC_FINAL0_B_INPUT_FOG						0x00030000
-#define    NV10TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV10TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV10TCL_RC_FINAL0_B_INPUT_TEXTURE0						0x00080000
-#define    NV10TCL_RC_FINAL0_B_INPUT_TEXTURE1						0x00090000
-#define    NV10TCL_RC_FINAL0_B_INPUT_SPARE0						0x000c0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_SPARE1						0x000d0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_E_TIMES_F						0x000f0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_TEXTURE2						0x000a0000
-#define    NV10TCL_RC_FINAL0_B_INPUT_TEXTURE3						0x000b0000
-#define   NV10TCL_RC_FINAL0_B_COMPONENT_USAGE						(1 << 20)
-#define    NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV10TCL_RC_FINAL0_B_MAPPING_SHIFT						21
-#define   NV10TCL_RC_FINAL0_B_MAPPING_MASK						0x00e00000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV10TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV10TCL_RC_FINAL0_A_INPUT_SHIFT						24
-#define   NV10TCL_RC_FINAL0_A_INPUT_MASK						0x0f000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_FOG						0x03000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_TEXTURE0						0x08000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_TEXTURE1						0x09000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_SPARE0						0x0c000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_SPARE1						0x0d000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_E_TIMES_F						0x0f000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_TEXTURE2						0x0a000000
-#define    NV10TCL_RC_FINAL0_A_INPUT_TEXTURE3						0x0b000000
-#define   NV10TCL_RC_FINAL0_A_COMPONENT_USAGE						(1 << 28)
-#define    NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV10TCL_RC_FINAL0_A_MAPPING_SHIFT						29
-#define   NV10TCL_RC_FINAL0_A_MAPPING_MASK						0xe0000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV10TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV10TCL_RC_FINAL1								0x0000028c
-#define   NV10TCL_RC_FINAL1_COLOR_SUM_CLAMP						(1 <<  7)
-#define   NV10TCL_RC_FINAL1_G_INPUT_SHIFT						8
-#define   NV10TCL_RC_FINAL1_G_INPUT_MASK						0x00000f00
-#define    NV10TCL_RC_FINAL1_G_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV10TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV10TCL_RC_FINAL1_G_INPUT_FOG						0x00000300
-#define    NV10TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV10TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV10TCL_RC_FINAL1_G_INPUT_TEXTURE0						0x00000800
-#define    NV10TCL_RC_FINAL1_G_INPUT_TEXTURE1						0x00000900
-#define    NV10TCL_RC_FINAL1_G_INPUT_SPARE0						0x00000c00
-#define    NV10TCL_RC_FINAL1_G_INPUT_SPARE1						0x00000d00
-#define    NV10TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV10TCL_RC_FINAL1_G_INPUT_E_TIMES_F						0x00000f00
-#define    NV10TCL_RC_FINAL1_G_INPUT_TEXTURE2						0x00000a00
-#define    NV10TCL_RC_FINAL1_G_INPUT_TEXTURE3						0x00000b00
-#define   NV10TCL_RC_FINAL1_G_COMPONENT_USAGE						(1 << 12)
-#define    NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV10TCL_RC_FINAL1_G_MAPPING_SHIFT						13
-#define   NV10TCL_RC_FINAL1_G_MAPPING_MASK						0x0000e000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV10TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV10TCL_RC_FINAL1_F_INPUT_SHIFT						16
-#define   NV10TCL_RC_FINAL1_F_INPUT_MASK						0x000f0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV10TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV10TCL_RC_FINAL1_F_INPUT_FOG						0x00030000
-#define    NV10TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV10TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV10TCL_RC_FINAL1_F_INPUT_TEXTURE0						0x00080000
-#define    NV10TCL_RC_FINAL1_F_INPUT_TEXTURE1						0x00090000
-#define    NV10TCL_RC_FINAL1_F_INPUT_SPARE0						0x000c0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_SPARE1						0x000d0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_E_TIMES_F						0x000f0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_TEXTURE2						0x000a0000
-#define    NV10TCL_RC_FINAL1_F_INPUT_TEXTURE3						0x000b0000
-#define   NV10TCL_RC_FINAL1_F_COMPONENT_USAGE						(1 << 20)
-#define    NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV10TCL_RC_FINAL1_F_MAPPING_SHIFT						21
-#define   NV10TCL_RC_FINAL1_F_MAPPING_MASK						0x00e00000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV10TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV10TCL_RC_FINAL1_E_INPUT_SHIFT						24
-#define   NV10TCL_RC_FINAL1_E_INPUT_MASK						0x0f000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_ZERO						0x00000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_FOG						0x03000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_TEXTURE0						0x08000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_TEXTURE1						0x09000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_SPARE0						0x0c000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_SPARE1						0x0d000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_E_TIMES_F						0x0f000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_TEXTURE2						0x0a000000
-#define    NV10TCL_RC_FINAL1_E_INPUT_TEXTURE3						0x0b000000
-#define   NV10TCL_RC_FINAL1_E_COMPONENT_USAGE						(1 << 28)
-#define    NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB					0x00000000
-#define    NV10TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV10TCL_RC_FINAL1_E_MAPPING_SHIFT						29
-#define   NV10TCL_RC_FINAL1_E_MAPPING_MASK						0xe0000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV10TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV10TCL_LIGHT_MODEL								0x00000294
-#define   NV10TCL_LIGHT_MODEL_VERTEX_SPECULAR						(1 <<  0)
-#define   NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR						(1 <<  1)
-#define   NV10TCL_LIGHT_MODEL_LOCAL_VIEWER						(1 << 16)
-#define  NV10TCL_COLOR_MATERIAL								0x00000298
-#define   NV10TCL_COLOR_MATERIAL_EMISSION						(1 <<  0)
-#define   NV10TCL_COLOR_MATERIAL_AMBIENT						(1 <<  1)
-#define   NV10TCL_COLOR_MATERIAL_DIFFUSE						(1 <<  2)
-#define   NV10TCL_COLOR_MATERIAL_SPECULAR						(1 <<  3)
-#define  NV10TCL_FOG_MODE								0x0000029c
-#define   NV10TCL_FOG_MODE_LINEAR							0x00002601
-#define   NV10TCL_FOG_MODE_EXP								0x00000800
-#define   NV10TCL_FOG_MODE_EXP_ABS							0x00000802
-#define   NV10TCL_FOG_MODE_EXP2								0x00000803
-#define  NV10TCL_FOG_COORD								0x000002a0
-#define   NV10TCL_FOG_COORD_FOG								0x00000000
-#define   NV10TCL_FOG_COORD_DIST_RADIAL							0x00000001
-#define   NV10TCL_FOG_COORD_DIST_ORTHOGONAL						0x00000002
-#define   NV10TCL_FOG_COORD_DIST_ORTHOGONAL_ABS						0x00000003
-#define  NV10TCL_FOG_ENABLE								0x000002a4
-#define  NV10TCL_FOG_COLOR								0x000002a8
-#define   NV10TCL_FOG_COLOR_R_SHIFT							0
-#define   NV10TCL_FOG_COLOR_R_MASK							0x000000ff
-#define   NV10TCL_FOG_COLOR_G_SHIFT							8
-#define   NV10TCL_FOG_COLOR_G_MASK							0x0000ff00
-#define   NV10TCL_FOG_COLOR_B_SHIFT							16
-#define   NV10TCL_FOG_COLOR_B_MASK							0x00ff0000
-#define   NV10TCL_FOG_COLOR_A_SHIFT							24
-#define   NV10TCL_FOG_COLOR_A_MASK							0xff000000
-#define  NV10TCL_VIEWPORT_CLIP_MODE							0x000002b4
-#define  NV10TCL_VIEWPORT_CLIP_HORIZ(x)							(0x000002c0+((x)*4))
-#define  NV10TCL_VIEWPORT_CLIP_HORIZ__SIZE						0x00000008
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_SHIFT					0
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_L_MASK					0x000007ff
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE					(1 << 11)
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_SHIFT					16
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_R_MASK					0x07ff0000
-#define   NV10TCL_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE					(1 << 27)
-#define  NV10TCL_VIEWPORT_CLIP_VERT(x)							(0x000002e0+((x)*4))
-#define  NV10TCL_VIEWPORT_CLIP_VERT__SIZE						0x00000008
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_SHIFT					0
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_T_MASK					0x000007ff
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE					(1 << 11)
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_SHIFT					16
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_B_MASK					0x07ff0000
-#define   NV10TCL_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE					(1 << 27)
-#define  NV10TCL_ALPHA_FUNC_ENABLE							0x00000300
-#define  NV10TCL_BLEND_FUNC_ENABLE							0x00000304
-#define  NV10TCL_CULL_FACE_ENABLE							0x00000308
-#define  NV10TCL_DEPTH_TEST_ENABLE							0x0000030c
-#define  NV10TCL_DITHER_ENABLE								0x00000310
-#define  NV10TCL_LIGHTING_ENABLE							0x00000314
-#define  NV10TCL_POINT_PARAMETERS_ENABLE						0x00000318
-#define  NV10TCL_POINT_SMOOTH_ENABLE							0x0000031c
-#define  NV10TCL_LINE_SMOOTH_ENABLE							0x00000320
-#define  NV10TCL_POLYGON_SMOOTH_ENABLE							0x00000324
-#define  NV10TCL_VERTEX_WEIGHT_ENABLE							0x00000328
-#define  NV10TCL_STENCIL_ENABLE								0x0000032c
-#define  NV10TCL_POLYGON_OFFSET_POINT_ENABLE						0x00000330
-#define  NV10TCL_POLYGON_OFFSET_LINE_ENABLE						0x00000334
-#define  NV10TCL_POLYGON_OFFSET_FILL_ENABLE						0x00000338
-#define  NV10TCL_ALPHA_FUNC_FUNC							0x0000033c
-#define   NV10TCL_ALPHA_FUNC_FUNC_NEVER							0x00000200
-#define   NV10TCL_ALPHA_FUNC_FUNC_LESS							0x00000201
-#define   NV10TCL_ALPHA_FUNC_FUNC_EQUAL							0x00000202
-#define   NV10TCL_ALPHA_FUNC_FUNC_LEQUAL						0x00000203
-#define   NV10TCL_ALPHA_FUNC_FUNC_GREATER						0x00000204
-#define   NV10TCL_ALPHA_FUNC_FUNC_NOTEQUAL						0x00000205
-#define   NV10TCL_ALPHA_FUNC_FUNC_GEQUAL						0x00000206
-#define   NV10TCL_ALPHA_FUNC_FUNC_ALWAYS						0x00000207
-#define  NV10TCL_ALPHA_FUNC_REF								0x00000340
-#define  NV10TCL_BLEND_FUNC_SRC								0x00000344
-#define   NV10TCL_BLEND_FUNC_SRC_ZERO							0x00000000
-#define   NV10TCL_BLEND_FUNC_SRC_ONE							0x00000001
-#define   NV10TCL_BLEND_FUNC_SRC_SRC_COLOR						0x00000300
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR					0x00000301
-#define   NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA						0x00000302
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA					0x00000303
-#define   NV10TCL_BLEND_FUNC_SRC_DST_ALPHA						0x00000304
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA					0x00000305
-#define   NV10TCL_BLEND_FUNC_SRC_DST_COLOR						0x00000306
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR					0x00000307
-#define   NV10TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE					0x00000308
-#define   NV10TCL_BLEND_FUNC_SRC_CONSTANT_COLOR						0x00008001
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR				0x00008002
-#define   NV10TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA						0x00008003
-#define   NV10TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA				0x00008004
-#define  NV10TCL_BLEND_FUNC_DST								0x00000348
-#define   NV10TCL_BLEND_FUNC_DST_ZERO							0x00000000
-#define   NV10TCL_BLEND_FUNC_DST_ONE							0x00000001
-#define   NV10TCL_BLEND_FUNC_DST_SRC_COLOR						0x00000300
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR					0x00000301
-#define   NV10TCL_BLEND_FUNC_DST_SRC_ALPHA						0x00000302
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA					0x00000303
-#define   NV10TCL_BLEND_FUNC_DST_DST_ALPHA						0x00000304
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA					0x00000305
-#define   NV10TCL_BLEND_FUNC_DST_DST_COLOR						0x00000306
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR					0x00000307
-#define   NV10TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE					0x00000308
-#define   NV10TCL_BLEND_FUNC_DST_CONSTANT_COLOR						0x00008001
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR				0x00008002
-#define   NV10TCL_BLEND_FUNC_DST_CONSTANT_ALPHA						0x00008003
-#define   NV10TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA				0x00008004
-#define  NV10TCL_BLEND_COLOR								0x0000034c
-#define   NV10TCL_BLEND_COLOR_B_SHIFT							0
-#define   NV10TCL_BLEND_COLOR_B_MASK							0x000000ff
-#define   NV10TCL_BLEND_COLOR_G_SHIFT							8
-#define   NV10TCL_BLEND_COLOR_G_MASK							0x0000ff00
-#define   NV10TCL_BLEND_COLOR_R_SHIFT							16
-#define   NV10TCL_BLEND_COLOR_R_MASK							0x00ff0000
-#define   NV10TCL_BLEND_COLOR_A_SHIFT							24
-#define   NV10TCL_BLEND_COLOR_A_MASK							0xff000000
-#define  NV10TCL_BLEND_EQUATION								0x00000350
-#define   NV10TCL_BLEND_EQUATION_FUNC_ADD						0x00008006
-#define   NV10TCL_BLEND_EQUATION_MIN							0x00008007
-#define   NV10TCL_BLEND_EQUATION_MAX							0x00008008
-#define   NV10TCL_BLEND_EQUATION_FUNC_SUBTRACT						0x0000800a
-#define   NV10TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT					0x0000800b
-#define  NV10TCL_DEPTH_FUNC								0x00000354
-#define   NV10TCL_DEPTH_FUNC_NEVER							0x00000200
-#define   NV10TCL_DEPTH_FUNC_LESS							0x00000201
-#define   NV10TCL_DEPTH_FUNC_EQUAL							0x00000202
-#define   NV10TCL_DEPTH_FUNC_LEQUAL							0x00000203
-#define   NV10TCL_DEPTH_FUNC_GREATER							0x00000204
-#define   NV10TCL_DEPTH_FUNC_NOTEQUAL							0x00000205
-#define   NV10TCL_DEPTH_FUNC_GEQUAL							0x00000206
-#define   NV10TCL_DEPTH_FUNC_ALWAYS							0x00000207
-#define  NV10TCL_COLOR_MASK								0x00000358
-#define   NV10TCL_COLOR_MASK_B								(1 <<  0)
-#define   NV10TCL_COLOR_MASK_G								(1 <<  8)
-#define   NV10TCL_COLOR_MASK_R								(1 << 16)
-#define   NV10TCL_COLOR_MASK_A								(1 << 24)
-#define  NV10TCL_DEPTH_WRITE_ENABLE							0x0000035c
-#define  NV10TCL_STENCIL_MASK								0x00000360
-#define  NV10TCL_STENCIL_FUNC_FUNC							0x00000364
-#define   NV10TCL_STENCIL_FUNC_FUNC_NEVER						0x00000200
-#define   NV10TCL_STENCIL_FUNC_FUNC_LESS						0x00000201
-#define   NV10TCL_STENCIL_FUNC_FUNC_EQUAL						0x00000202
-#define   NV10TCL_STENCIL_FUNC_FUNC_LEQUAL						0x00000203
-#define   NV10TCL_STENCIL_FUNC_FUNC_GREATER						0x00000204
-#define   NV10TCL_STENCIL_FUNC_FUNC_NOTEQUAL						0x00000205
-#define   NV10TCL_STENCIL_FUNC_FUNC_GEQUAL						0x00000206
-#define   NV10TCL_STENCIL_FUNC_FUNC_ALWAYS						0x00000207
-#define  NV10TCL_STENCIL_FUNC_REF							0x00000368
-#define  NV10TCL_STENCIL_FUNC_MASK							0x0000036c
-#define  NV10TCL_STENCIL_OP_FAIL							0x00000370
-#define   NV10TCL_STENCIL_OP_FAIL_ZERO							0x00000000
-#define   NV10TCL_STENCIL_OP_FAIL_INVERT						0x0000150a
-#define   NV10TCL_STENCIL_OP_FAIL_KEEP							0x00001e00
-#define   NV10TCL_STENCIL_OP_FAIL_REPLACE						0x00001e01
-#define   NV10TCL_STENCIL_OP_FAIL_INCR							0x00001e02
-#define   NV10TCL_STENCIL_OP_FAIL_DECR							0x00001e03
-#define   NV10TCL_STENCIL_OP_FAIL_INCR_WRAP						0x00008507
-#define   NV10TCL_STENCIL_OP_FAIL_DECR_WRAP						0x00008508
-#define  NV10TCL_STENCIL_OP_ZFAIL							0x00000374
-#define   NV10TCL_STENCIL_OP_ZFAIL_ZERO							0x00000000
-#define   NV10TCL_STENCIL_OP_ZFAIL_INVERT						0x0000150a
-#define   NV10TCL_STENCIL_OP_ZFAIL_KEEP							0x00001e00
-#define   NV10TCL_STENCIL_OP_ZFAIL_REPLACE						0x00001e01
-#define   NV10TCL_STENCIL_OP_ZFAIL_INCR							0x00001e02
-#define   NV10TCL_STENCIL_OP_ZFAIL_DECR							0x00001e03
-#define   NV10TCL_STENCIL_OP_ZFAIL_INCR_WRAP						0x00008507
-#define   NV10TCL_STENCIL_OP_ZFAIL_DECR_WRAP						0x00008508
-#define  NV10TCL_STENCIL_OP_ZPASS							0x00000378
-#define   NV10TCL_STENCIL_OP_ZPASS_ZERO							0x00000000
-#define   NV10TCL_STENCIL_OP_ZPASS_INVERT						0x0000150a
-#define   NV10TCL_STENCIL_OP_ZPASS_KEEP							0x00001e00
-#define   NV10TCL_STENCIL_OP_ZPASS_REPLACE						0x00001e01
-#define   NV10TCL_STENCIL_OP_ZPASS_INCR							0x00001e02
-#define   NV10TCL_STENCIL_OP_ZPASS_DECR							0x00001e03
-#define   NV10TCL_STENCIL_OP_ZPASS_INCR_WRAP						0x00008507
-#define   NV10TCL_STENCIL_OP_ZPASS_DECR_WRAP						0x00008508
-#define  NV10TCL_SHADE_MODEL								0x0000037c
-#define   NV10TCL_SHADE_MODEL_FLAT							0x00001d00
-#define   NV10TCL_SHADE_MODEL_SMOOTH							0x00001d01
-#define  NV10TCL_LINE_WIDTH								0x00000380
-#define  NV10TCL_POLYGON_OFFSET_FACTOR							0x00000384
-#define  NV10TCL_POLYGON_OFFSET_UNITS							0x00000388
-#define  NV10TCL_POLYGON_MODE_FRONT							0x0000038c
-#define   NV10TCL_POLYGON_MODE_FRONT_POINT						0x00001b00
-#define   NV10TCL_POLYGON_MODE_FRONT_LINE						0x00001b01
-#define   NV10TCL_POLYGON_MODE_FRONT_FILL						0x00001b02
-#define  NV10TCL_POLYGON_MODE_BACK							0x00000390
-#define   NV10TCL_POLYGON_MODE_BACK_POINT						0x00001b00
-#define   NV10TCL_POLYGON_MODE_BACK_LINE						0x00001b01
-#define   NV10TCL_POLYGON_MODE_BACK_FILL						0x00001b02
-#define  NV10TCL_DEPTH_RANGE_NEAR							0x00000394
-#define  NV10TCL_DEPTH_RANGE_FAR							0x00000398
-#define  NV10TCL_CULL_FACE								0x0000039c
-#define   NV10TCL_CULL_FACE_FRONT							0x00000404
-#define   NV10TCL_CULL_FACE_BACK							0x00000405
-#define   NV10TCL_CULL_FACE_FRONT_AND_BACK						0x00000408
-#define  NV10TCL_FRONT_FACE								0x000003a0
-#define   NV10TCL_FRONT_FACE_CW								0x00000900
-#define   NV10TCL_FRONT_FACE_CCW							0x00000901
-#define  NV10TCL_NORMALIZE_ENABLE							0x000003a4
-#define  NV10TCL_MATERIAL_FACTOR_R							0x000003a8
-#define  NV10TCL_MATERIAL_FACTOR_G							0x000003ac
-#define  NV10TCL_MATERIAL_FACTOR_B							0x000003b0
-#define  NV10TCL_MATERIAL_FACTOR_A							0x000003b4
-#define  NV10TCL_SEPARATE_SPECULAR_ENABLE						0x000003b8
-#define  NV10TCL_ENABLED_LIGHTS								0x000003bc
-#define   NV10TCL_ENABLED_LIGHTS_0_SHIFT						0
-#define   NV10TCL_ENABLED_LIGHTS_0_MASK							0x00000003
-#define    NV10TCL_ENABLED_LIGHTS_0_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_0_NONPOSITIONAL					0x00000001
-#define    NV10TCL_ENABLED_LIGHTS_0_POSITIONAL						0x00000002
-#define    NV10TCL_ENABLED_LIGHTS_0_DIRECTIONAL						0x00000003
-#define   NV10TCL_ENABLED_LIGHTS_1_SHIFT						2
-#define   NV10TCL_ENABLED_LIGHTS_1_MASK							0x0000000c
-#define    NV10TCL_ENABLED_LIGHTS_1_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_1_NONPOSITIONAL					0x00000004
-#define    NV10TCL_ENABLED_LIGHTS_1_POSITIONAL						0x00000008
-#define    NV10TCL_ENABLED_LIGHTS_1_DIRECTIONAL						0x0000000c
-#define   NV10TCL_ENABLED_LIGHTS_2_SHIFT						4
-#define   NV10TCL_ENABLED_LIGHTS_2_MASK							0x00000030
-#define    NV10TCL_ENABLED_LIGHTS_2_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_2_NONPOSITIONAL					0x00000010
-#define    NV10TCL_ENABLED_LIGHTS_2_POSITIONAL						0x00000020
-#define    NV10TCL_ENABLED_LIGHTS_2_DIRECTIONAL						0x00000030
-#define   NV10TCL_ENABLED_LIGHTS_3_SHIFT						6
-#define   NV10TCL_ENABLED_LIGHTS_3_MASK							0x000000c0
-#define    NV10TCL_ENABLED_LIGHTS_3_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_3_NONPOSITIONAL					0x00000040
-#define    NV10TCL_ENABLED_LIGHTS_3_POSITIONAL						0x00000080
-#define    NV10TCL_ENABLED_LIGHTS_3_DIRECTIONAL						0x000000c0
-#define   NV10TCL_ENABLED_LIGHTS_4_SHIFT						8
-#define   NV10TCL_ENABLED_LIGHTS_4_MASK							0x00000300
-#define    NV10TCL_ENABLED_LIGHTS_4_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_4_NONPOSITIONAL					0x00000100
-#define    NV10TCL_ENABLED_LIGHTS_4_POSITIONAL						0x00000200
-#define    NV10TCL_ENABLED_LIGHTS_4_DIRECTIONAL						0x00000300
-#define   NV10TCL_ENABLED_LIGHTS_5_SHIFT						10
-#define   NV10TCL_ENABLED_LIGHTS_5_MASK							0x00000c00
-#define    NV10TCL_ENABLED_LIGHTS_5_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_5_NONPOSITIONAL					0x00000400
-#define    NV10TCL_ENABLED_LIGHTS_5_POSITIONAL						0x00000800
-#define    NV10TCL_ENABLED_LIGHTS_5_DIRECTIONAL						0x00000c00
-#define   NV10TCL_ENABLED_LIGHTS_6_SHIFT						12
-#define   NV10TCL_ENABLED_LIGHTS_6_MASK							0x00003000
-#define    NV10TCL_ENABLED_LIGHTS_6_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_6_NONPOSITIONAL					0x00001000
-#define    NV10TCL_ENABLED_LIGHTS_6_POSITIONAL						0x00002000
-#define    NV10TCL_ENABLED_LIGHTS_6_DIRECTIONAL						0x00003000
-#define   NV10TCL_ENABLED_LIGHTS_7_SHIFT						14
-#define   NV10TCL_ENABLED_LIGHTS_7_MASK							0x0000c000
-#define    NV10TCL_ENABLED_LIGHTS_7_DISABLED						0x00000000
-#define    NV10TCL_ENABLED_LIGHTS_7_NONPOSITIONAL					0x00004000
-#define    NV10TCL_ENABLED_LIGHTS_7_POSITIONAL						0x00008000
-#define    NV10TCL_ENABLED_LIGHTS_7_DIRECTIONAL						0x0000c000
-#define  NV10TCL_TX_GEN_MODE_S(x)							(0x000003c0+((x)*16))
-#define  NV10TCL_TX_GEN_MODE_S__SIZE							0x00000002
-#define   NV10TCL_TX_GEN_MODE_S_FALSE							0x00000000
-#define   NV10TCL_TX_GEN_MODE_S_EYE_LINEAR						0x00002400
-#define   NV10TCL_TX_GEN_MODE_S_OBJECT_LINEAR						0x00002401
-#define   NV10TCL_TX_GEN_MODE_S_SPHERE_MAP						0x00002402
-#define   NV10TCL_TX_GEN_MODE_S_NORMAL_MAP						0x00008511
-#define   NV10TCL_TX_GEN_MODE_S_REFLECTION_MAP						0x00008512
-#define  NV10TCL_TX_GEN_MODE_T(x)							(0x000003c4+((x)*16))
-#define  NV10TCL_TX_GEN_MODE_T__SIZE							0x00000002
-#define   NV10TCL_TX_GEN_MODE_T_FALSE							0x00000000
-#define   NV10TCL_TX_GEN_MODE_T_EYE_LINEAR						0x00002400
-#define   NV10TCL_TX_GEN_MODE_T_OBJECT_LINEAR						0x00002401
-#define   NV10TCL_TX_GEN_MODE_T_SPHERE_MAP						0x00002402
-#define   NV10TCL_TX_GEN_MODE_T_NORMAL_MAP						0x00008511
-#define   NV10TCL_TX_GEN_MODE_T_REFLECTION_MAP						0x00008512
-#define  NV10TCL_TX_GEN_MODE_R(x)							(0x000003c8+((x)*16))
-#define  NV10TCL_TX_GEN_MODE_R__SIZE							0x00000002
-#define   NV10TCL_TX_GEN_MODE_R_FALSE							0x00000000
-#define   NV10TCL_TX_GEN_MODE_R_EYE_LINEAR						0x00002400
-#define   NV10TCL_TX_GEN_MODE_R_OBJECT_LINEAR						0x00002401
-#define   NV10TCL_TX_GEN_MODE_R_SPHERE_MAP						0x00002402
-#define   NV10TCL_TX_GEN_MODE_R_NORMAL_MAP						0x00008511
-#define   NV10TCL_TX_GEN_MODE_R_REFLECTION_MAP						0x00008512
-#define  NV10TCL_TX_GEN_MODE_Q(x)							(0x000003cc+((x)*16))
-#define  NV10TCL_TX_GEN_MODE_Q__SIZE							0x00000002
-#define   NV10TCL_TX_GEN_MODE_Q_FALSE							0x00000000
-#define   NV10TCL_TX_GEN_MODE_Q_EYE_LINEAR						0x00002400
-#define   NV10TCL_TX_GEN_MODE_Q_OBJECT_LINEAR						0x00002401
-#define   NV10TCL_TX_GEN_MODE_Q_SPHERE_MAP						0x00002402
-#define   NV10TCL_TX_GEN_MODE_Q_NORMAL_MAP						0x00008511
-#define   NV10TCL_TX_GEN_MODE_Q_REFLECTION_MAP						0x00008512
-#define  NV10TCL_TX_MATRIX_ENABLE(x)							(0x000003e0+((x)*4))
-#define  NV10TCL_TX_MATRIX_ENABLE__SIZE							0x00000002
-#define  NV10TCL_VIEW_MATRIX_ENABLE							0x000003e8
-#define   NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW1						(1 <<  0)
-#define   NV10TCL_VIEW_MATRIX_ENABLE_MODELVIEW0						(1 <<  1)
-#define   NV10TCL_VIEW_MATRIX_ENABLE_PROJECTION						(1 <<  2)
-#define  NV10TCL_POINT_SIZE								0x000003ec
-#define  NV10TCL_MODELVIEW0_MATRIX(x)							(0x00000400+((x)*4))
-#define  NV10TCL_MODELVIEW0_MATRIX__SIZE						0x00000010
-#define  NV10TCL_MODELVIEW1_MATRIX(x)							(0x00000440+((x)*4))
-#define  NV10TCL_MODELVIEW1_MATRIX__SIZE						0x00000010
-#define  NV10TCL_INVERSE_MODELVIEW0_MATRIX(x)						(0x00000480+((x)*4))
-#define  NV10TCL_INVERSE_MODELVIEW0_MATRIX__SIZE					0x00000010
-#define  NV10TCL_INVERSE_MODELVIEW1_MATRIX(x)						(0x000004c0+((x)*4))
-#define  NV10TCL_INVERSE_MODELVIEW1_MATRIX__SIZE					0x00000010
-#define  NV10TCL_PROJECTION_MATRIX(x)							(0x00000500+((x)*4))
-#define  NV10TCL_PROJECTION_MATRIX__SIZE						0x00000010
-#define  NV10TCL_TX0_MATRIX(x)								(0x00000540+((x)*4))
-#define  NV10TCL_TX0_MATRIX__SIZE							0x00000010
-#define  NV10TCL_TX1_MATRIX(x)								(0x00000580+((x)*4))
-#define  NV10TCL_TX1_MATRIX__SIZE							0x00000010
-#define  NV10TCL_TX_GEN_COEFF_S_A(x)							(0x00000600+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_S_A__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_S_B(x)							(0x00000604+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_S_B__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_S_C(x)							(0x00000608+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_S_C__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_S_D(x)							(0x0000060c+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_S_D__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_T_A(x)							(0x00000610+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_T_A__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_T_B(x)							(0x00000614+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_T_B__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_T_C(x)							(0x00000618+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_T_C__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_T_D(x)							(0x0000061c+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_T_D__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_R_A(x)							(0x00000620+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_R_A__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_R_B(x)							(0x00000624+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_R_B__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_R_C(x)							(0x00000628+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_R_C__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_R_D(x)							(0x0000062c+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_R_D__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_Q_A(x)							(0x00000630+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_Q_A__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_Q_B(x)							(0x00000634+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_Q_B__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_Q_C(x)							(0x00000638+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_Q_C__SIZE							0x00000002
-#define  NV10TCL_TX_GEN_COEFF_Q_D(x)							(0x0000063c+((x)*64))
-#define  NV10TCL_TX_GEN_COEFF_Q_D__SIZE							0x00000002
-#define  NV10TCL_FOG_EQUATION_CONSTANT							0x00000680
-#define  NV10TCL_FOG_EQUATION_LINEAR							0x00000684
-#define  NV10TCL_FOG_EQUATION_QUADRATIC							0x00000688
-#define  NV10TCL_MATERIAL_SHININESS(x)							(0x000006a0+((x)*4))
-#define  NV10TCL_MATERIAL_SHININESS__SIZE						0x00000006
-#define  NV10TCL_LIGHT_MODEL_AMBIENT_R							0x000006c4
-#define  NV10TCL_LIGHT_MODEL_AMBIENT_G							0x000006c8
-#define  NV10TCL_LIGHT_MODEL_AMBIENT_B							0x000006cc
-#define  NV10TCL_VIEWPORT_TRANSLATE_X							0x000006e8
-#define  NV10TCL_VIEWPORT_TRANSLATE_Y							0x000006ec
-#define  NV10TCL_VIEWPORT_TRANSLATE_Z							0x000006f0
-#define  NV10TCL_VIEWPORT_TRANSLATE_W							0x000006f4
-#define  NV10TCL_POINT_PARAMETER(x)							(0x000006f8+((x)*4))
-#define  NV10TCL_POINT_PARAMETER__SIZE							0x00000008
-#define  NV10TCL_LIGHT_AMBIENT_R(x)							(0x00000800+((x)*128))
-#define  NV10TCL_LIGHT_AMBIENT_R__SIZE							0x00000008
-#define  NV10TCL_LIGHT_AMBIENT_G(x)							(0x00000804+((x)*128))
-#define  NV10TCL_LIGHT_AMBIENT_G__SIZE							0x00000008
-#define  NV10TCL_LIGHT_AMBIENT_B(x)							(0x00000808+((x)*128))
-#define  NV10TCL_LIGHT_AMBIENT_B__SIZE							0x00000008
-#define  NV10TCL_LIGHT_DIFFUSE_R(x)							(0x0000080c+((x)*128))
-#define  NV10TCL_LIGHT_DIFFUSE_R__SIZE							0x00000008
-#define  NV10TCL_LIGHT_DIFFUSE_G(x)							(0x00000810+((x)*128))
-#define  NV10TCL_LIGHT_DIFFUSE_G__SIZE							0x00000008
-#define  NV10TCL_LIGHT_DIFFUSE_B(x)							(0x00000814+((x)*128))
-#define  NV10TCL_LIGHT_DIFFUSE_B__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPECULAR_R(x)							(0x00000818+((x)*128))
-#define  NV10TCL_LIGHT_SPECULAR_R__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPECULAR_G(x)							(0x0000081c+((x)*128))
-#define  NV10TCL_LIGHT_SPECULAR_G__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPECULAR_B(x)							(0x00000820+((x)*128))
-#define  NV10TCL_LIGHT_SPECULAR_B__SIZE							0x00000008
-#define  NV10TCL_LIGHT_HALF_VECTOR_X(x)							(0x00000828+((x)*128))
-#define  NV10TCL_LIGHT_HALF_VECTOR_X__SIZE						0x00000008
-#define  NV10TCL_LIGHT_HALF_VECTOR_Y(x)							(0x0000082c+((x)*128))
-#define  NV10TCL_LIGHT_HALF_VECTOR_Y__SIZE						0x00000008
-#define  NV10TCL_LIGHT_HALF_VECTOR_Z(x)							(0x00000830+((x)*128))
-#define  NV10TCL_LIGHT_HALF_VECTOR_Z__SIZE						0x00000008
-#define  NV10TCL_LIGHT_DIRECTION_X(x)							(0x00000834+((x)*128))
-#define  NV10TCL_LIGHT_DIRECTION_X__SIZE						0x00000008
-#define  NV10TCL_LIGHT_DIRECTION_Y(x)							(0x00000838+((x)*128))
-#define  NV10TCL_LIGHT_DIRECTION_Y__SIZE						0x00000008
-#define  NV10TCL_LIGHT_DIRECTION_Z(x)							(0x0000083c+((x)*128))
-#define  NV10TCL_LIGHT_DIRECTION_Z__SIZE						0x00000008
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_A(x)							(0x00000840+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_A__SIZE						0x00000008
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_B(x)							(0x00000844+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_B__SIZE						0x00000008
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_C(x)							(0x00000848+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_C__SIZE						0x00000008
-#define  NV10TCL_LIGHT_SPOT_DIR_X(x)							(0x0000084c+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_DIR_X__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPOT_DIR_Y(x)							(0x00000850+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_DIR_Y__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPOT_DIR_Z(x)							(0x00000854+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_DIR_Z__SIZE							0x00000008
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_D(x)							(0x00000858+((x)*128))
-#define  NV10TCL_LIGHT_SPOT_CUTOFF_D__SIZE						0x00000008
-#define  NV10TCL_LIGHT_POSITION_X(x)							(0x0000085c+((x)*128))
-#define  NV10TCL_LIGHT_POSITION_X__SIZE							0x00000008
-#define  NV10TCL_LIGHT_POSITION_Y(x)							(0x00000860+((x)*128))
-#define  NV10TCL_LIGHT_POSITION_Y__SIZE							0x00000008
-#define  NV10TCL_LIGHT_POSITION_Z(x)							(0x00000864+((x)*128))
-#define  NV10TCL_LIGHT_POSITION_Z__SIZE							0x00000008
-#define  NV10TCL_LIGHT_ATTENUATION_CONSTANT(x)						(0x00000868+((x)*128))
-#define  NV10TCL_LIGHT_ATTENUATION_CONSTANT__SIZE					0x00000008
-#define  NV10TCL_LIGHT_ATTENUATION_LINEAR(x)						(0x0000086c+((x)*128))
-#define  NV10TCL_LIGHT_ATTENUATION_LINEAR__SIZE						0x00000008
-#define  NV10TCL_LIGHT_ATTENUATION_QUADRATIC(x)						(0x00000870+((x)*128))
-#define  NV10TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE					0x00000008
-#define  NV10TCL_VERTEX_POS_3F_X							0x00000c00
-#define  NV10TCL_VERTEX_POS_3F_Y							0x00000c04
-#define  NV10TCL_VERTEX_POS_3F_Z							0x00000c08
-#define  NV10TCL_VERTEX_POS_4F_X							0x00000c18
-#define  NV10TCL_VERTEX_POS_4F_Y							0x00000c1c
-#define  NV10TCL_VERTEX_POS_4F_Z							0x00000c20
-#define  NV10TCL_VERTEX_POS_4F_W							0x00000c24
-#define  NV10TCL_VERTEX_NOR_3F_X							0x00000c30
-#define  NV10TCL_VERTEX_NOR_3F_Y							0x00000c34
-#define  NV10TCL_VERTEX_NOR_3F_Z							0x00000c38
-#define  NV10TCL_VERTEX_NOR_3I_XY							0x00000c40
-#define   NV10TCL_VERTEX_NOR_3I_XY_X_SHIFT						0
-#define   NV10TCL_VERTEX_NOR_3I_XY_X_MASK						0x0000ffff
-#define   NV10TCL_VERTEX_NOR_3I_XY_Y_SHIFT						16
-#define   NV10TCL_VERTEX_NOR_3I_XY_Y_MASK						0xffff0000
-#define  NV10TCL_VERTEX_NOR_3I_Z							0x00000c44
-#define   NV10TCL_VERTEX_NOR_3I_Z_Z_SHIFT						0
-#define   NV10TCL_VERTEX_NOR_3I_Z_Z_MASK						0x0000ffff
-#define  NV10TCL_VERTEX_COL_4F_R							0x00000c50
-#define  NV10TCL_VERTEX_COL_4F_G							0x00000c54
-#define  NV10TCL_VERTEX_COL_4F_B							0x00000c58
-#define  NV10TCL_VERTEX_COL_4F_A							0x00000c5c
-#define  NV10TCL_VERTEX_COL_3F_R							0x00000c60
-#define  NV10TCL_VERTEX_COL_3F_G							0x00000c64
-#define  NV10TCL_VERTEX_COL_3F_B							0x00000c68
-#define  NV10TCL_VERTEX_COL_4I								0x00000c6c
-#define   NV10TCL_VERTEX_COL_4I_R_SHIFT							0
-#define   NV10TCL_VERTEX_COL_4I_R_MASK							0x000000ff
-#define   NV10TCL_VERTEX_COL_4I_G_SHIFT							8
-#define   NV10TCL_VERTEX_COL_4I_G_MASK							0x0000ff00
-#define   NV10TCL_VERTEX_COL_4I_B_SHIFT							16
-#define   NV10TCL_VERTEX_COL_4I_B_MASK							0x00ff0000
-#define   NV10TCL_VERTEX_COL_4I_A_SHIFT							24
-#define   NV10TCL_VERTEX_COL_4I_A_MASK							0xff000000
-#define  NV10TCL_VERTEX_COL2_3F_R							0x00000c80
-#define  NV10TCL_VERTEX_COL2_3F_G							0x00000c84
-#define  NV10TCL_VERTEX_COL2_3F_B							0x00000c88
-#define  NV10TCL_VERTEX_COL2_3I								0x00000c8c
-#define   NV10TCL_VERTEX_COL2_3I_R_SHIFT						0
-#define   NV10TCL_VERTEX_COL2_3I_R_MASK							0x000000ff
-#define   NV10TCL_VERTEX_COL2_3I_G_SHIFT						8
-#define   NV10TCL_VERTEX_COL2_3I_G_MASK							0x0000ff00
-#define   NV10TCL_VERTEX_COL2_3I_B_SHIFT						16
-#define   NV10TCL_VERTEX_COL2_3I_B_MASK							0x00ff0000
-#define  NV10TCL_VERTEX_TX0_2F_S							0x00000c90
-#define  NV10TCL_VERTEX_TX0_2F_T							0x00000c94
-#define  NV10TCL_VERTEX_TX0_2I								0x00000c98
-#define   NV10TCL_VERTEX_TX0_2I_S_SHIFT							0
-#define   NV10TCL_VERTEX_TX0_2I_S_MASK							0x0000ffff
-#define   NV10TCL_VERTEX_TX0_2I_T_SHIFT							16
-#define   NV10TCL_VERTEX_TX0_2I_T_MASK							0xffff0000
-#define  NV10TCL_VERTEX_TX0_4F_S							0x00000ca0
-#define  NV10TCL_VERTEX_TX0_4F_T							0x00000ca4
-#define  NV10TCL_VERTEX_TX0_4F_R							0x00000ca8
-#define  NV10TCL_VERTEX_TX0_4F_Q							0x00000cac
-#define  NV10TCL_VERTEX_TX0_4I_ST							0x00000cb0
-#define   NV10TCL_VERTEX_TX0_4I_ST_S_SHIFT						0
-#define   NV10TCL_VERTEX_TX0_4I_ST_S_MASK						0x0000ffff
-#define   NV10TCL_VERTEX_TX0_4I_ST_T_SHIFT						16
-#define   NV10TCL_VERTEX_TX0_4I_ST_T_MASK						0xffff0000
-#define  NV10TCL_VERTEX_TX0_4I_RQ							0x00000cb4
-#define   NV10TCL_VERTEX_TX0_4I_RQ_R_SHIFT						0
-#define   NV10TCL_VERTEX_TX0_4I_RQ_R_MASK						0x0000ffff
-#define   NV10TCL_VERTEX_TX0_4I_RQ_Q_SHIFT						16
-#define   NV10TCL_VERTEX_TX0_4I_RQ_Q_MASK						0xffff0000
-#define  NV10TCL_VERTEX_TX1_2F_S							0x00000cb8
-#define  NV10TCL_VERTEX_TX1_2F_T							0x00000cbc
-#define  NV10TCL_VERTEX_TX1_2I								0x00000cc0
-#define   NV10TCL_VERTEX_TX1_2I_S_SHIFT							0
-#define   NV10TCL_VERTEX_TX1_2I_S_MASK							0x0000ffff
-#define   NV10TCL_VERTEX_TX1_2I_T_SHIFT							16
-#define   NV10TCL_VERTEX_TX1_2I_T_MASK							0xffff0000
-#define  NV10TCL_VERTEX_TX1_4F_S							0x00000cc8
-#define  NV10TCL_VERTEX_TX1_4F_T							0x00000ccc
-#define  NV10TCL_VERTEX_TX1_4F_R							0x00000cd0
-#define  NV10TCL_VERTEX_TX1_4F_Q							0x00000cd4
-#define  NV10TCL_VERTEX_TX1_4I_ST							0x00000cd8
-#define   NV10TCL_VERTEX_TX1_4I_ST_S_SHIFT						0
-#define   NV10TCL_VERTEX_TX1_4I_ST_S_MASK						0x0000ffff
-#define   NV10TCL_VERTEX_TX1_4I_ST_T_SHIFT						16
-#define   NV10TCL_VERTEX_TX1_4I_ST_T_MASK						0xffff0000
-#define  NV10TCL_VERTEX_TX1_4I_RQ							0x00000cdc
-#define   NV10TCL_VERTEX_TX1_4I_RQ_R_SHIFT						0
-#define   NV10TCL_VERTEX_TX1_4I_RQ_R_MASK						0x0000ffff
-#define   NV10TCL_VERTEX_TX1_4I_RQ_Q_SHIFT						16
-#define   NV10TCL_VERTEX_TX1_4I_RQ_Q_MASK						0xffff0000
-#define  NV10TCL_VERTEX_FOG_1F								0x00000ce0
-#define  NV10TCL_VERTEX_WGH_1F								0x00000ce4
-#define  NV10TCL_EDGEFLAG_ENABLE							0x00000cec
-#define  NV10TCL_VERTEX_ARRAY_VALIDATE							0x00000cf0
-#define  NV10TCL_VTXBUF_ADDRESS(x)							(0x00000d00+((x)*8))
-#define  NV10TCL_VTXBUF_ADDRESS__SIZE							0x00000008
-#define  NV10TCL_VTXFMT(x)								(0x00000d04+((x)*8))
-#define  NV10TCL_VTXFMT__SIZE								0x00000008
-#define   NV10TCL_VTXFMT_TYPE_SHIFT							0
-#define   NV10TCL_VTXFMT_TYPE_MASK							0x0000000f
-#define    NV10TCL_VTXFMT_TYPE_BYTE_BGRA						0x00000000
-#define    NV10TCL_VTXFMT_TYPE_SHORT							0x00000001
-#define    NV10TCL_VTXFMT_TYPE_FLOAT							0x00000002
-#define    NV10TCL_VTXFMT_TYPE_BYTE_RGBA						0x00000004
-#define   NV10TCL_VTXFMT_FIELDS_SHIFT							4
-#define   NV10TCL_VTXFMT_FIELDS_MASK							0x000000f0
-#define   NV10TCL_VTXFMT_STRIDE_SHIFT							8
-#define   NV10TCL_VTXFMT_STRIDE_MASK							0x0000ff00
-#define   NV10TCL_VTXFMT_POS_HOMOGENEOUS						(1 << 24)
-#define  NV10TCL_VERTEX_BEGIN_END							0x00000dfc
-#define   NV10TCL_VERTEX_BEGIN_END_STOP							0x00000000
-#define   NV10TCL_VERTEX_BEGIN_END_POINTS						0x00000001
-#define   NV10TCL_VERTEX_BEGIN_END_LINES						0x00000002
-#define   NV10TCL_VERTEX_BEGIN_END_LINE_LOOP						0x00000003
-#define   NV10TCL_VERTEX_BEGIN_END_LINE_STRIP						0x00000004
-#define   NV10TCL_VERTEX_BEGIN_END_TRIANGLES						0x00000005
-#define   NV10TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP					0x00000006
-#define   NV10TCL_VERTEX_BEGIN_END_TRIANGLE_FAN						0x00000007
-#define   NV10TCL_VERTEX_BEGIN_END_QUADS						0x00000008
-#define   NV10TCL_VERTEX_BEGIN_END_QUAD_STRIP						0x00000009
-#define   NV10TCL_VERTEX_BEGIN_END_POLYGON						0x0000000a
-#define  NV10TCL_VB_ELEMENT_U16								0x00000e00
-#define   NV10TCL_VB_ELEMENT_U16_I0_SHIFT						0
-#define   NV10TCL_VB_ELEMENT_U16_I0_MASK						0x0000ffff
-#define   NV10TCL_VB_ELEMENT_U16_I1_SHIFT						16
-#define   NV10TCL_VB_ELEMENT_U16_I1_MASK						0xffff0000
-#define  NV10TCL_VB_ELEMENT_U32								0x00001100
-#define  NV10TCL_VERTEX_BUFFER_BEGIN_END						0x000013fc
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_STOP						0x00000000
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_POINTS					0x00000001
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_LINES						0x00000002
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_LOOP					0x00000003
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_LINE_STRIP					0x00000004
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLES					0x00000005
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_STRIP				0x00000006
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_TRIANGLE_FAN					0x00000007
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_QUADS						0x00000008
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_QUAD_STRIP					0x00000009
-#define   NV10TCL_VERTEX_BUFFER_BEGIN_END_POLYGON					0x0000000a
-#define  NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS						0x00001400
-#define   NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_SHIFT					0
-#define   NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_FIRST_MASK					0x0000ffff
-#define   NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_SHIFT					24
-#define   NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS_LAST_MASK					0xff000000
-#define  NV10TCL_VERTEX_ARRAY_DATA							0x00001800
-
-
-#define NV11TCL										0x00000096
-
-#define  NV11TCL_COLOR_LOGIC_OP_ENABLE							0x00000d40
-#define  NV11TCL_COLOR_LOGIC_OP_OP							0x00000d44
-#define   NV11TCL_COLOR_LOGIC_OP_OP_CLEAR						0x00001500
-#define   NV11TCL_COLOR_LOGIC_OP_OP_AND							0x00001501
-#define   NV11TCL_COLOR_LOGIC_OP_OP_AND_REVERSE						0x00001502
-#define   NV11TCL_COLOR_LOGIC_OP_OP_COPY						0x00001503
-#define   NV11TCL_COLOR_LOGIC_OP_OP_AND_INVERTED					0x00001504
-#define   NV11TCL_COLOR_LOGIC_OP_OP_NOOP						0x00001505
-#define   NV11TCL_COLOR_LOGIC_OP_OP_XOR							0x00001506
-#define   NV11TCL_COLOR_LOGIC_OP_OP_OR							0x00001507
-#define   NV11TCL_COLOR_LOGIC_OP_OP_NOR							0x00001508
-#define   NV11TCL_COLOR_LOGIC_OP_OP_EQUIV						0x00001509
-#define   NV11TCL_COLOR_LOGIC_OP_OP_INVERT						0x0000150a
-#define   NV11TCL_COLOR_LOGIC_OP_OP_OR_REVERSE						0x0000150b
-#define   NV11TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED					0x0000150c
-#define   NV11TCL_COLOR_LOGIC_OP_OP_OR_INVERTED						0x0000150d
-#define   NV11TCL_COLOR_LOGIC_OP_OP_NAND						0x0000150e
-#define   NV11TCL_COLOR_LOGIC_OP_OP_SET							0x0000150f
-
-
-#define NV17TCL										0x00000099
-
-#define  NV17TCL_DMA_IN_MEMORY4								0x000001ac
-#define  NV17TCL_DMA_IN_MEMORY5								0x000001b0
-#define  NV17TCL_COLOR_MASK_ENABLE							0x000002bc
-#define  NV17TCL_ZCLEAR_ENABLE								0x000003f8
-#define  NV17TCL_ZCLEAR_VALUE								0x000003fc
-#define   NV17TCL_ZCLEAR_VALUE_DEPTH_SHIFT						8
-#define   NV17TCL_ZCLEAR_VALUE_DEPTH_MASK						0xffffff00
-#define   NV17TCL_ZCLEAR_VALUE_SEQUENCE_SHIFT						0
-#define   NV17TCL_ZCLEAR_VALUE_SEQUENCE_MASK						0x000000ff
-#define  NV17TCL_LMA_DEPTH_BUFFER_PITCH							0x00000d5c
-#define  NV17TCL_LMA_DEPTH_BUFFER_OFFSET						0x00000d60
-#define  NV17TCL_LMA_DEPTH_FILL_VALUE							0x00000d68
-#define  NV17TCL_LMA_DEPTH_BUFFER_CLEAR							0x00000d6c
-#define  NV17TCL_LMA_DEPTH_WINDOW_X							0x00001638
-#define  NV17TCL_LMA_DEPTH_WINDOW_Y							0x0000163c
-#define  NV17TCL_LMA_DEPTH_WINDOW_Z							0x00001640
-#define  NV17TCL_LMA_DEPTH_WINDOW_W							0x00001644
-#define  NV17TCL_LMA_DEPTH_ENABLE							0x00001658
-
-
-#define NV03_CONTEXT_SURFACES_2D							0x00000058
-
-#define  NV03_CONTEXT_SURFACES_2D_SYNCHRONIZE						0x00000100
-#define  NV03_CONTEXT_SURFACES_2D_DMA_NOTIFY						0x00000180
-#define  NV03_CONTEXT_SURFACES_2D_DMA_SOURCE						0x00000184
-#define  NV03_CONTEXT_SURFACES_2D_DMA_DESTIN						0x00000188
-#define  NV03_CONTEXT_SURFACES_2D_COLOR_FORMAT						0x00000300
-#define  NV03_CONTEXT_SURFACES_2D_PITCH							0x00000304
-#define   NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_SHIFT					0
-#define   NV03_CONTEXT_SURFACES_2D_PITCH_SOURCE_MASK					0x0000ffff
-#define   NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_SHIFT					16
-#define   NV03_CONTEXT_SURFACES_2D_PITCH_DESTIN_MASK					0xffff0000
-#define  NV03_CONTEXT_SURFACES_2D_OFFSET_SOURCE						0x00000308
-#define  NV03_CONTEXT_SURFACES_2D_OFFSET_DESTIN						0x0000030c
-
-
-#define NV03_CONTEXT_SURFACES_3D							0x0000005a
-
-#define  NV03_CONTEXT_SURFACES_3D_SYNCHRONIZE						0x00000100
-#define  NV03_CONTEXT_SURFACES_3D_DMA_NOTIFY						0x00000180
-#define  NV03_CONTEXT_SURFACES_3D_DMA_SURFACE						0x00000184
-#define  NV03_CONTEXT_SURFACES_3D_PITCH							0x00000300
-#define  NV03_CONTEXT_SURFACES_3D_OFFSET_COLOR						0x00000304
-#define  NV03_CONTEXT_SURFACES_3D_OFFSET_ZETA						0x00000308
-
-
-#define NV04_INDEXED_IMAGE_FROM_CPU							0x00000060
-
-#define  NV04_INDEXED_IMAGE_FROM_CPU_NOP						0x00000100
-#define  NV04_INDEXED_IMAGE_FROM_CPU_NOTIFY						0x00000104
-#define  NV04_INDEXED_IMAGE_FROM_CPU_PATCH						0x0000010c
-#define  NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY						0x00000180
-#define  NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT						0x00000184
-#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY						0x00000188
-#define  NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE					0x0000018c
-#define  NV04_INDEXED_IMAGE_FROM_CPU_PATTERN						0x00000190
-#define  NV04_INDEXED_IMAGE_FROM_CPU_ROP						0x00000194
-#define  NV04_INDEXED_IMAGE_FROM_CPU_BETA1						0x00000198
-#define  NV04_INDEXED_IMAGE_FROM_CPU_BETA4						0x0000019c
-#define  NV04_INDEXED_IMAGE_FROM_CPU_SURFACE						0x000001a0
-#define  NV04_INDEXED_IMAGE_FROM_CPU_OPERATION						0x000003e4
-#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT					0x000003e8
-#define  NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT					0x000003ec
-#define  NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET						0x000003f0
-#define  NV04_INDEXED_IMAGE_FROM_CPU_POINT						0x000003f4
-#define  NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT						0x000003f8
-#define  NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN						0x000003fc
-#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR(x)						(0x00000400+((x)*4))
-#define  NV04_INDEXED_IMAGE_FROM_CPU_COLOR__SIZE					0x00000700
-
-
-#define NV05_INDEXED_IMAGE_FROM_CPU							0x00000064
-
-#define  NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION					0x000003e0
-
-
-#define NV03_CHANNEL_PIO								0x0000006a
-
-
-
-#define NV03_CHANNEL_DMA								0x0000006b
-
-
-
-#define NV04_BETA_SOLID									0x00000072
-
-#define  NV04_BETA_SOLID_NOP								0x00000100
-#define  NV04_BETA_SOLID_NOTIFY								0x00000104
-#define  NV04_BETA_SOLID_DMA_NOTIFY							0x00000180
-#define  NV04_BETA_SOLID_BETA_OUTPUT							0x00000200
-#define  NV04_BETA_SOLID_BETA_FACTOR							0x00000300
-
-
-#define NV10_TEXTURE_FROM_CPU								0x0000007b
-
-#define  NV10_TEXTURE_FROM_CPU_NOP							0x00000100
-#define  NV10_TEXTURE_FROM_CPU_NOTIFY							0x00000104
-#define  NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE						0x00000108
-#define  NV10_TEXTURE_FROM_CPU_PM_TRIGGER						0x00000140
-#define  NV10_TEXTURE_FROM_CPU_DMA_NOTIFY						0x00000180
-#define  NV10_TEXTURE_FROM_CPU_SURFACE							0x00000184
-#define  NV10_TEXTURE_FROM_CPU_COLOR_FORMAT						0x00000300
-#define  NV10_TEXTURE_FROM_CPU_POINT							0x00000304
-#define   NV10_TEXTURE_FROM_CPU_POINT_X_SHIFT						0
-#define   NV10_TEXTURE_FROM_CPU_POINT_X_MASK						0x0000ffff
-#define   NV10_TEXTURE_FROM_CPU_POINT_Y_SHIFT						16
-#define   NV10_TEXTURE_FROM_CPU_POINT_Y_MASK						0xffff0000
-#define  NV10_TEXTURE_FROM_CPU_SIZE							0x00000308
-#define   NV10_TEXTURE_FROM_CPU_SIZE_W_SHIFT						0
-#define   NV10_TEXTURE_FROM_CPU_SIZE_W_MASK						0x0000ffff
-#define   NV10_TEXTURE_FROM_CPU_SIZE_H_SHIFT						16
-#define   NV10_TEXTURE_FROM_CPU_SIZE_H_MASK						0xffff0000
-#define  NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL						0x0000030c
-#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_SHIFT					0
-#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X_MASK					0x0000ffff
-#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_SHIFT					16
-#define   NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W_MASK					0xffff0000
-#define  NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL						0x00000310
-#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_SHIFT					0
-#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y_MASK					0x0000ffff
-#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_SHIFT					16
-#define   NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H_MASK					0xffff0000
-#define  NV10_TEXTURE_FROM_CPU_COLOR(x)							(0x00000400+((x)*4))
-#define  NV10_TEXTURE_FROM_CPU_COLOR__SIZE						0x00000700
-
-
-#define NV30_TEXTURE_FROM_CPU								0x0000037b
-
-
-
-#define NV40_TEXTURE_FROM_CPU								0x0000307b
-
-
-
-#define NV10_VIDEO_DISPLAY								0x0000007c
-
-
-
-#define NV20TCL										0x00000097
-
-#define  NV20TCL_NOP									0x00000100
-#define  NV20TCL_NOTIFY									0x00000104
-#define  NV20TCL_DMA_NOTIFY								0x00000180
-#define  NV20TCL_DMA_TEXTURE0								0x00000184
-#define  NV20TCL_DMA_TEXTURE1								0x00000188
-#define  NV20TCL_DMA_COLOR								0x00000194
-#define  NV20TCL_DMA_ZETA								0x00000198
-#define  NV20TCL_DMA_VTXBUF0								0x0000019c
-#define  NV20TCL_DMA_VTXBUF1								0x000001a0
-#define  NV20TCL_DMA_FENCE								0x000001a4
-#define  NV20TCL_DMA_QUERY								0x000001a8
-#define  NV20TCL_RT_HORIZ								0x00000200
-#define   NV20TCL_RT_HORIZ_X_SHIFT							0
-#define   NV20TCL_RT_HORIZ_X_MASK							0x0000ffff
-#define   NV20TCL_RT_HORIZ_W_SHIFT							16
-#define   NV20TCL_RT_HORIZ_W_MASK							0xffff0000
-#define  NV20TCL_RT_VERT								0x00000204
-#define   NV20TCL_RT_VERT_Y_SHIFT							0
-#define   NV20TCL_RT_VERT_Y_MASK							0x0000ffff
-#define   NV20TCL_RT_VERT_H_SHIFT							16
-#define   NV20TCL_RT_VERT_H_MASK							0xffff0000
-#define  NV20TCL_RT_FORMAT								0x00000208
-#define   NV20TCL_RT_FORMAT_TYPE_SHIFT							8
-#define   NV20TCL_RT_FORMAT_TYPE_MASK							0x00000f00
-#define    NV20TCL_RT_FORMAT_TYPE_LINEAR						0x00000100
-#define    NV20TCL_RT_FORMAT_TYPE_SWIZZLED						0x00000200
-#define   NV20TCL_RT_FORMAT_COLOR_SHIFT							0
-#define   NV20TCL_RT_FORMAT_COLOR_MASK							0x0000001f
-#define    NV20TCL_RT_FORMAT_COLOR_R5G6B5						0x00000003
-#define    NV20TCL_RT_FORMAT_COLOR_X8R8G8B8						0x00000005
-#define    NV20TCL_RT_FORMAT_COLOR_A8R8G8B8						0x00000008
-#define    NV20TCL_RT_FORMAT_COLOR_B8							0x00000009
-#define    NV20TCL_RT_FORMAT_COLOR_UNKNOWN						0x0000000d
-#define    NV20TCL_RT_FORMAT_COLOR_X8B8G8R8						0x0000000f
-#define    NV20TCL_RT_FORMAT_COLOR_A8B8G8R8						0x00000010
-#define  NV20TCL_RT_PITCH								0x0000020c
-#define   NV20TCL_RT_PITCH_COLOR_PITCH_SHIFT						0
-#define   NV20TCL_RT_PITCH_COLOR_PITCH_MASK						0x0000ffff
-#define   NV20TCL_RT_PITCH_ZETA_PITCH_SHIFT						16
-#define   NV20TCL_RT_PITCH_ZETA_PITCH_MASK						0xffff0000
-#define  NV20TCL_COLOR_OFFSET								0x00000210
-#define  NV20TCL_ZETA_OFFSET								0x00000214
-#define  NV20TCL_RC_IN_ALPHA(x)								(0x00000260+((x)*4))
-#define  NV20TCL_RC_IN_ALPHA__SIZE							0x00000008
-#define   NV20TCL_RC_IN_ALPHA_D_INPUT_SHIFT						0
-#define   NV20TCL_RC_IN_ALPHA_D_INPUT_MASK						0x0000000f
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_FOG						0x00000003
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE0						0x00000008
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE1						0x00000009
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0						0x0000000c
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE1						0x0000000d
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_E_TIMES_F					0x0000000f
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE2						0x0000000a
-#define    NV20TCL_RC_IN_ALPHA_D_INPUT_TEXTURE3						0x0000000b
-#define   NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV20TCL_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV20TCL_RC_IN_ALPHA_D_MAPPING_SHIFT						5
-#define   NV20TCL_RC_IN_ALPHA_D_MAPPING_MASK						0x000000e0
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT				0x00000020
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL				0x00000080
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE				0x000000a0
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY				0x000000c0
-#define    NV20TCL_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV20TCL_RC_IN_ALPHA_C_INPUT_SHIFT						8
-#define   NV20TCL_RC_IN_ALPHA_C_INPUT_MASK						0x00000f00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_FOG						0x00000300
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE0						0x00000800
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE1						0x00000900
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0						0x00000c00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE1						0x00000d00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_E_TIMES_F					0x00000f00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE2						0x00000a00
-#define    NV20TCL_RC_IN_ALPHA_C_INPUT_TEXTURE3						0x00000b00
-#define   NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE						(1 << 12)
-#define    NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV20TCL_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV20TCL_RC_IN_ALPHA_C_MAPPING_SHIFT						13
-#define   NV20TCL_RC_IN_ALPHA_C_MAPPING_MASK						0x0000e000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT				0x00002000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL				0x00008000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE				0x0000a000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY				0x0000c000
-#define    NV20TCL_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV20TCL_RC_IN_ALPHA_B_INPUT_SHIFT						16
-#define   NV20TCL_RC_IN_ALPHA_B_INPUT_MASK						0x000f0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_FOG						0x00030000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE0						0x00080000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE1						0x00090000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0						0x000c0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE1						0x000d0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_E_TIMES_F					0x000f0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE2						0x000a0000
-#define    NV20TCL_RC_IN_ALPHA_B_INPUT_TEXTURE3						0x000b0000
-#define   NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE						(1 << 20)
-#define    NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV20TCL_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV20TCL_RC_IN_ALPHA_B_MAPPING_SHIFT						21
-#define   NV20TCL_RC_IN_ALPHA_B_MAPPING_MASK						0x00e00000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT				0x00200000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL				0x00800000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE				0x00a00000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY				0x00c00000
-#define    NV20TCL_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV20TCL_RC_IN_ALPHA_A_INPUT_SHIFT						24
-#define   NV20TCL_RC_IN_ALPHA_A_INPUT_MASK						0x0f000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_FOG						0x03000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE0						0x08000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE1						0x09000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0						0x0c000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE1						0x0d000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_E_TIMES_F					0x0f000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE2						0x0a000000
-#define    NV20TCL_RC_IN_ALPHA_A_INPUT_TEXTURE3						0x0b000000
-#define   NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE						(1 << 28)
-#define    NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE					0x00000000
-#define    NV20TCL_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV20TCL_RC_IN_ALPHA_A_MAPPING_SHIFT						29
-#define   NV20TCL_RC_IN_ALPHA_A_MAPPING_MASK						0xe0000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT				0x20000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL				0x80000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE				0xa0000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY				0xc0000000
-#define    NV20TCL_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV20TCL_RC_FINAL0								0x00000288
-#define   NV20TCL_RC_FINAL0_D_INPUT_SHIFT						0
-#define   NV20TCL_RC_FINAL0_D_INPUT_MASK						0x0000000f
-#define    NV20TCL_RC_FINAL0_D_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV20TCL_RC_FINAL0_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV20TCL_RC_FINAL0_D_INPUT_FOG						0x00000003
-#define    NV20TCL_RC_FINAL0_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV20TCL_RC_FINAL0_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV20TCL_RC_FINAL0_D_INPUT_TEXTURE0						0x00000008
-#define    NV20TCL_RC_FINAL0_D_INPUT_TEXTURE1						0x00000009
-#define    NV20TCL_RC_FINAL0_D_INPUT_SPARE0						0x0000000c
-#define    NV20TCL_RC_FINAL0_D_INPUT_SPARE1						0x0000000d
-#define    NV20TCL_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV20TCL_RC_FINAL0_D_INPUT_E_TIMES_F						0x0000000f
-#define    NV20TCL_RC_FINAL0_D_INPUT_TEXTURE2						0x0000000a
-#define    NV20TCL_RC_FINAL0_D_INPUT_TEXTURE3						0x0000000b
-#define   NV20TCL_RC_FINAL0_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL0_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV20TCL_RC_FINAL0_D_MAPPING_SHIFT						5
-#define   NV20TCL_RC_FINAL0_D_MAPPING_MASK						0x000000e0
-#define    NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT					0x00000020
-#define    NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV20TCL_RC_FINAL0_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL					0x00000080
-#define    NV20TCL_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE					0x000000a0
-#define    NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY					0x000000c0
-#define    NV20TCL_RC_FINAL0_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV20TCL_RC_FINAL0_C_INPUT_SHIFT						8
-#define   NV20TCL_RC_FINAL0_C_INPUT_MASK						0x00000f00
-#define    NV20TCL_RC_FINAL0_C_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV20TCL_RC_FINAL0_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV20TCL_RC_FINAL0_C_INPUT_FOG						0x00000300
-#define    NV20TCL_RC_FINAL0_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV20TCL_RC_FINAL0_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV20TCL_RC_FINAL0_C_INPUT_TEXTURE0						0x00000800
-#define    NV20TCL_RC_FINAL0_C_INPUT_TEXTURE1						0x00000900
-#define    NV20TCL_RC_FINAL0_C_INPUT_SPARE0						0x00000c00
-#define    NV20TCL_RC_FINAL0_C_INPUT_SPARE1						0x00000d00
-#define    NV20TCL_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_FINAL0_C_INPUT_E_TIMES_F						0x00000f00
-#define    NV20TCL_RC_FINAL0_C_INPUT_TEXTURE2						0x00000a00
-#define    NV20TCL_RC_FINAL0_C_INPUT_TEXTURE3						0x00000b00
-#define   NV20TCL_RC_FINAL0_C_COMPONENT_USAGE						(1 << 12)
-#define    NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL0_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV20TCL_RC_FINAL0_C_MAPPING_SHIFT						13
-#define   NV20TCL_RC_FINAL0_C_MAPPING_MASK						0x0000e000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV20TCL_RC_FINAL0_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV20TCL_RC_FINAL0_B_INPUT_SHIFT						16
-#define   NV20TCL_RC_FINAL0_B_INPUT_MASK						0x000f0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV20TCL_RC_FINAL0_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV20TCL_RC_FINAL0_B_INPUT_FOG						0x00030000
-#define    NV20TCL_RC_FINAL0_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV20TCL_RC_FINAL0_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV20TCL_RC_FINAL0_B_INPUT_TEXTURE0						0x00080000
-#define    NV20TCL_RC_FINAL0_B_INPUT_TEXTURE1						0x00090000
-#define    NV20TCL_RC_FINAL0_B_INPUT_SPARE0						0x000c0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_SPARE1						0x000d0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_E_TIMES_F						0x000f0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_TEXTURE2						0x000a0000
-#define    NV20TCL_RC_FINAL0_B_INPUT_TEXTURE3						0x000b0000
-#define   NV20TCL_RC_FINAL0_B_COMPONENT_USAGE						(1 << 20)
-#define    NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL0_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV20TCL_RC_FINAL0_B_MAPPING_SHIFT						21
-#define   NV20TCL_RC_FINAL0_B_MAPPING_MASK						0x00e00000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV20TCL_RC_FINAL0_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV20TCL_RC_FINAL0_A_INPUT_SHIFT						24
-#define   NV20TCL_RC_FINAL0_A_INPUT_MASK						0x0f000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_FOG						0x03000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_TEXTURE0						0x08000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_TEXTURE1						0x09000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_SPARE0						0x0c000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_SPARE1						0x0d000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_E_TIMES_F						0x0f000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_TEXTURE2						0x0a000000
-#define    NV20TCL_RC_FINAL0_A_INPUT_TEXTURE3						0x0b000000
-#define   NV20TCL_RC_FINAL0_A_COMPONENT_USAGE						(1 << 28)
-#define    NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL0_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV20TCL_RC_FINAL0_A_MAPPING_SHIFT						29
-#define   NV20TCL_RC_FINAL0_A_MAPPING_MASK						0xe0000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV20TCL_RC_FINAL0_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV20TCL_RC_FINAL1								0x0000028c
-#define   NV20TCL_RC_FINAL1_COLOR_SUM_CLAMP						(1 <<  7)
-#define   NV20TCL_RC_FINAL1_G_INPUT_SHIFT						8
-#define   NV20TCL_RC_FINAL1_G_INPUT_MASK						0x00000f00
-#define    NV20TCL_RC_FINAL1_G_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV20TCL_RC_FINAL1_G_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV20TCL_RC_FINAL1_G_INPUT_FOG						0x00000300
-#define    NV20TCL_RC_FINAL1_G_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV20TCL_RC_FINAL1_G_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV20TCL_RC_FINAL1_G_INPUT_TEXTURE0						0x00000800
-#define    NV20TCL_RC_FINAL1_G_INPUT_TEXTURE1						0x00000900
-#define    NV20TCL_RC_FINAL1_G_INPUT_SPARE0						0x00000c00
-#define    NV20TCL_RC_FINAL1_G_INPUT_SPARE1						0x00000d00
-#define    NV20TCL_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_FINAL1_G_INPUT_E_TIMES_F						0x00000f00
-#define    NV20TCL_RC_FINAL1_G_INPUT_TEXTURE2						0x00000a00
-#define    NV20TCL_RC_FINAL1_G_INPUT_TEXTURE3						0x00000b00
-#define   NV20TCL_RC_FINAL1_G_COMPONENT_USAGE						(1 << 12)
-#define    NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL1_G_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV20TCL_RC_FINAL1_G_MAPPING_SHIFT						13
-#define   NV20TCL_RC_FINAL1_G_MAPPING_MASK						0x0000e000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV20TCL_RC_FINAL1_G_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV20TCL_RC_FINAL1_F_INPUT_SHIFT						16
-#define   NV20TCL_RC_FINAL1_F_INPUT_MASK						0x000f0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV20TCL_RC_FINAL1_F_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV20TCL_RC_FINAL1_F_INPUT_FOG						0x00030000
-#define    NV20TCL_RC_FINAL1_F_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV20TCL_RC_FINAL1_F_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV20TCL_RC_FINAL1_F_INPUT_TEXTURE0						0x00080000
-#define    NV20TCL_RC_FINAL1_F_INPUT_TEXTURE1						0x00090000
-#define    NV20TCL_RC_FINAL1_F_INPUT_SPARE0						0x000c0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_SPARE1						0x000d0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_E_TIMES_F						0x000f0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_TEXTURE2						0x000a0000
-#define    NV20TCL_RC_FINAL1_F_INPUT_TEXTURE3						0x000b0000
-#define   NV20TCL_RC_FINAL1_F_COMPONENT_USAGE						(1 << 20)
-#define    NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL1_F_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV20TCL_RC_FINAL1_F_MAPPING_SHIFT						21
-#define   NV20TCL_RC_FINAL1_F_MAPPING_MASK						0x00e00000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV20TCL_RC_FINAL1_F_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV20TCL_RC_FINAL1_E_INPUT_SHIFT						24
-#define   NV20TCL_RC_FINAL1_E_INPUT_MASK						0x0f000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_FOG						0x03000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_TEXTURE0						0x08000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_TEXTURE1						0x09000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_SPARE0						0x0c000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_SPARE1						0x0d000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_E_TIMES_F						0x0f000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_TEXTURE2						0x0a000000
-#define    NV20TCL_RC_FINAL1_E_INPUT_TEXTURE3						0x0b000000
-#define   NV20TCL_RC_FINAL1_E_COMPONENT_USAGE						(1 << 28)
-#define    NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_FINAL1_E_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV20TCL_RC_FINAL1_E_MAPPING_SHIFT						29
-#define   NV20TCL_RC_FINAL1_E_MAPPING_MASK						0xe0000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV20TCL_RC_FINAL1_E_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV20TCL_LIGHT_MODEL								0x00000294
-#define   NV20TCL_LIGHT_MODEL_VIEWER_SHIFT						16
-#define   NV20TCL_LIGHT_MODEL_VIEWER_MASK						0x00030000
-#define    NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL						0x00020000
-#define    NV20TCL_LIGHT_MODEL_VIEWER_LOCAL						0x00030000
-#define   NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR						(1 <<  0)
-#define  NV20TCL_COLOR_MATERIAL								0x00000298
-#define   NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_SHIFT					0
-#define   NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_MASK					0x00000003
-#define    NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL1					0x00000001
-#define    NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL2					0x00000002
-#define   NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_SHIFT					2
-#define   NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_MASK					0x0000000c
-#define    NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL1					0x00000004
-#define    NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL2					0x00000008
-#define   NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_SHIFT					4
-#define   NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_MASK					0x00000030
-#define    NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL1					0x00000010
-#define    NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL2					0x00000020
-#define   NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_SHIFT					6
-#define   NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_MASK					0x000000c0
-#define    NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL1					0x00000040
-#define    NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL2					0x00000080
-#define   NV20TCL_COLOR_MATERIAL_BACK_EMISSION_SHIFT					8
-#define   NV20TCL_COLOR_MATERIAL_BACK_EMISSION_MASK					0x00000300
-#define    NV20TCL_COLOR_MATERIAL_BACK_EMISSION_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL1					0x00000100
-#define    NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL2					0x00000200
-#define   NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_SHIFT					10
-#define   NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_MASK					0x00000c00
-#define    NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL1					0x00000400
-#define    NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL2					0x00000800
-#define   NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_SHIFT					12
-#define   NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_MASK					0x00003000
-#define    NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL1					0x00001000
-#define    NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL2					0x00002000
-#define   NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_SHIFT					14
-#define   NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_MASK					0x0000c000
-#define    NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_OFF					0x00000000
-#define    NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL1					0x00004000
-#define    NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL2					0x00008000
-#define  NV20TCL_FOG_MODE								0x0000029c
-#define   NV20TCL_FOG_MODE_LINEAR_UNSIGNED						0x00000804
-#define   NV20TCL_FOG_MODE_LINEAR_SIGNED						0x00002601
-#define   NV20TCL_FOG_MODE_EXP_UNSIGNED							0x00000802
-#define   NV20TCL_FOG_MODE_EXP_SIGNED							0x00000800
-#define   NV20TCL_FOG_MODE_EXP2_UNSIGNED						0x00000803
-#define   NV20TCL_FOG_MODE_EXP2_SIGNED							0x00000801
-#define  NV20TCL_FOG_COORD								0x000002a0
-#define   NV20TCL_FOG_COORD_DIST_RADIAL							0x00000001
-#define   NV20TCL_FOG_COORD_DIST_ORTHOGONAL						0x00000002
-#define   NV20TCL_FOG_COORD_DIST_ORTHOGONAL_ABS						0x00000003
-#define   NV20TCL_FOG_COORD_FOG								0x00000006
-#define  NV20TCL_FOG_ENABLE								0x000002a4
-#define  NV20TCL_FOG_COLOR								0x000002a8
-#define   NV20TCL_FOG_COLOR_R_SHIFT							0
-#define   NV20TCL_FOG_COLOR_R_MASK							0x000000ff
-#define   NV20TCL_FOG_COLOR_G_SHIFT							8
-#define   NV20TCL_FOG_COLOR_G_MASK							0x0000ff00
-#define   NV20TCL_FOG_COLOR_B_SHIFT							16
-#define   NV20TCL_FOG_COLOR_B_MASK							0x00ff0000
-#define   NV20TCL_FOG_COLOR_A_SHIFT							24
-#define   NV20TCL_FOG_COLOR_A_MASK							0xff000000
-#define  NV20TCL_VIEWPORT_CLIP_MODE							0x000002b4
-#define  NV20TCL_VIEWPORT_CLIP_HORIZ(x)							(0x000002c0+((x)*4))
-#define  NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE						0x00000008
-#define  NV20TCL_VIEWPORT_CLIP_VERT(x)							(0x000002e0+((x)*4))
-#define  NV20TCL_VIEWPORT_CLIP_VERT__SIZE						0x00000008
-#define  NV20TCL_ALPHA_FUNC_ENABLE							0x00000300
-#define  NV20TCL_BLEND_FUNC_ENABLE							0x00000304
-#define  NV20TCL_CULL_FACE_ENABLE							0x00000308
-#define  NV20TCL_DEPTH_TEST_ENABLE							0x0000030c
-#define  NV20TCL_DITHER_ENABLE								0x00000310
-#define  NV20TCL_LIGHTING_ENABLE							0x00000314
-#define  NV20TCL_POINT_PARAMETERS_ENABLE						0x00000318
-#define  NV20TCL_POINT_SMOOTH_ENABLE							0x0000031c
-#define  NV20TCL_LINE_SMOOTH_ENABLE							0x00000320
-#define  NV20TCL_POLYGON_SMOOTH_ENABLE							0x00000324
-#define  NV20TCL_STENCIL_ENABLE								0x0000032c
-#define  NV20TCL_POLYGON_OFFSET_POINT_ENABLE						0x00000330
-#define  NV20TCL_POLYGON_OFFSET_LINE_ENABLE						0x00000334
-#define  NV20TCL_POLYGON_OFFSET_FILL_ENABLE						0x00000338
-#define  NV20TCL_ALPHA_FUNC_FUNC							0x0000033c
-#define   NV20TCL_ALPHA_FUNC_FUNC_NEVER							0x00000200
-#define   NV20TCL_ALPHA_FUNC_FUNC_LESS							0x00000201
-#define   NV20TCL_ALPHA_FUNC_FUNC_EQUAL							0x00000202
-#define   NV20TCL_ALPHA_FUNC_FUNC_LEQUAL						0x00000203
-#define   NV20TCL_ALPHA_FUNC_FUNC_GREATER						0x00000204
-#define   NV20TCL_ALPHA_FUNC_FUNC_NOTEQUAL						0x00000205
-#define   NV20TCL_ALPHA_FUNC_FUNC_GEQUAL						0x00000206
-#define   NV20TCL_ALPHA_FUNC_FUNC_ALWAYS						0x00000207
-#define  NV20TCL_ALPHA_FUNC_REF								0x00000340
-#define  NV20TCL_BLEND_FUNC_SRC								0x00000344
-#define   NV20TCL_BLEND_FUNC_SRC_ZERO							0x00000000
-#define   NV20TCL_BLEND_FUNC_SRC_ONE							0x00000001
-#define   NV20TCL_BLEND_FUNC_SRC_SRC_COLOR						0x00000300
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR					0x00000301
-#define   NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA						0x00000302
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA					0x00000303
-#define   NV20TCL_BLEND_FUNC_SRC_DST_ALPHA						0x00000304
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA					0x00000305
-#define   NV20TCL_BLEND_FUNC_SRC_DST_COLOR						0x00000306
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR					0x00000307
-#define   NV20TCL_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE					0x00000308
-#define   NV20TCL_BLEND_FUNC_SRC_CONSTANT_COLOR						0x00008001
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR				0x00008002
-#define   NV20TCL_BLEND_FUNC_SRC_CONSTANT_ALPHA						0x00008003
-#define   NV20TCL_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA				0x00008004
-#define  NV20TCL_BLEND_FUNC_DST								0x00000348
-#define   NV20TCL_BLEND_FUNC_DST_ZERO							0x00000000
-#define   NV20TCL_BLEND_FUNC_DST_ONE							0x00000001
-#define   NV20TCL_BLEND_FUNC_DST_SRC_COLOR						0x00000300
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR					0x00000301
-#define   NV20TCL_BLEND_FUNC_DST_SRC_ALPHA						0x00000302
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA					0x00000303
-#define   NV20TCL_BLEND_FUNC_DST_DST_ALPHA						0x00000304
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA					0x00000305
-#define   NV20TCL_BLEND_FUNC_DST_DST_COLOR						0x00000306
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR					0x00000307
-#define   NV20TCL_BLEND_FUNC_DST_SRC_ALPHA_SATURATE					0x00000308
-#define   NV20TCL_BLEND_FUNC_DST_CONSTANT_COLOR						0x00008001
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR				0x00008002
-#define   NV20TCL_BLEND_FUNC_DST_CONSTANT_ALPHA						0x00008003
-#define   NV20TCL_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA				0x00008004
-#define  NV20TCL_BLEND_COLOR								0x0000034c
-#define   NV20TCL_BLEND_COLOR_B_SHIFT							0
-#define   NV20TCL_BLEND_COLOR_B_MASK							0x000000ff
-#define   NV20TCL_BLEND_COLOR_G_SHIFT							8
-#define   NV20TCL_BLEND_COLOR_G_MASK							0x0000ff00
-#define   NV20TCL_BLEND_COLOR_R_SHIFT							16
-#define   NV20TCL_BLEND_COLOR_R_MASK							0x00ff0000
-#define   NV20TCL_BLEND_COLOR_A_SHIFT							24
-#define   NV20TCL_BLEND_COLOR_A_MASK							0xff000000
-#define  NV20TCL_BLEND_EQUATION								0x00000350
-#define   NV20TCL_BLEND_EQUATION_FUNC_ADD						0x00008006
-#define   NV20TCL_BLEND_EQUATION_MIN							0x00008007
-#define   NV20TCL_BLEND_EQUATION_MAX							0x00008008
-#define   NV20TCL_BLEND_EQUATION_FUNC_SUBTRACT						0x0000800a
-#define   NV20TCL_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT					0x0000800b
-#define  NV20TCL_DEPTH_FUNC								0x00000354
-#define   NV20TCL_DEPTH_FUNC_NEVER							0x00000200
-#define   NV20TCL_DEPTH_FUNC_LESS							0x00000201
-#define   NV20TCL_DEPTH_FUNC_EQUAL							0x00000202
-#define   NV20TCL_DEPTH_FUNC_LEQUAL							0x00000203
-#define   NV20TCL_DEPTH_FUNC_GREATER							0x00000204
-#define   NV20TCL_DEPTH_FUNC_NOTEQUAL							0x00000205
-#define   NV20TCL_DEPTH_FUNC_GEQUAL							0x00000206
-#define   NV20TCL_DEPTH_FUNC_ALWAYS							0x00000207
-#define  NV20TCL_COLOR_MASK								0x00000358
-#define   NV20TCL_COLOR_MASK_B								(1 <<  0)
-#define   NV20TCL_COLOR_MASK_G								(1 <<  8)
-#define   NV20TCL_COLOR_MASK_R								(1 << 16)
-#define   NV20TCL_COLOR_MASK_A								(1 << 24)
-#define  NV20TCL_DEPTH_WRITE_ENABLE							0x0000035c
-#define  NV20TCL_STENCIL_MASK								0x00000360
-#define  NV20TCL_STENCIL_FUNC_FUNC							0x00000364
-#define   NV20TCL_STENCIL_FUNC_FUNC_NEVER						0x00000200
-#define   NV20TCL_STENCIL_FUNC_FUNC_LESS						0x00000201
-#define   NV20TCL_STENCIL_FUNC_FUNC_EQUAL						0x00000202
-#define   NV20TCL_STENCIL_FUNC_FUNC_LEQUAL						0x00000203
-#define   NV20TCL_STENCIL_FUNC_FUNC_GREATER						0x00000204
-#define   NV20TCL_STENCIL_FUNC_FUNC_NOTEQUAL						0x00000205
-#define   NV20TCL_STENCIL_FUNC_FUNC_GEQUAL						0x00000206
-#define   NV20TCL_STENCIL_FUNC_FUNC_ALWAYS						0x00000207
-#define  NV20TCL_STENCIL_FUNC_REF							0x00000368
-#define  NV20TCL_STENCIL_FUNC_MASK							0x0000036c
-#define  NV20TCL_STENCIL_OP_FAIL							0x00000370
-#define   NV20TCL_STENCIL_OP_FAIL_ZERO							0x00000000
-#define   NV20TCL_STENCIL_OP_FAIL_INVERT						0x0000150a
-#define   NV20TCL_STENCIL_OP_FAIL_KEEP							0x00001e00
-#define   NV20TCL_STENCIL_OP_FAIL_REPLACE						0x00001e01
-#define   NV20TCL_STENCIL_OP_FAIL_INCR							0x00001e02
-#define   NV20TCL_STENCIL_OP_FAIL_DECR							0x00001e03
-#define   NV20TCL_STENCIL_OP_FAIL_INCR_WRAP						0x00008507
-#define   NV20TCL_STENCIL_OP_FAIL_DECR_WRAP						0x00008508
-#define  NV20TCL_STENCIL_OP_ZFAIL							0x00000374
-#define   NV20TCL_STENCIL_OP_ZFAIL_ZERO							0x00000000
-#define   NV20TCL_STENCIL_OP_ZFAIL_INVERT						0x0000150a
-#define   NV20TCL_STENCIL_OP_ZFAIL_KEEP							0x00001e00
-#define   NV20TCL_STENCIL_OP_ZFAIL_REPLACE						0x00001e01
-#define   NV20TCL_STENCIL_OP_ZFAIL_INCR							0x00001e02
-#define   NV20TCL_STENCIL_OP_ZFAIL_DECR							0x00001e03
-#define   NV20TCL_STENCIL_OP_ZFAIL_INCR_WRAP						0x00008507
-#define   NV20TCL_STENCIL_OP_ZFAIL_DECR_WRAP						0x00008508
-#define  NV20TCL_STENCIL_OP_ZPASS							0x00000378
-#define   NV20TCL_STENCIL_OP_ZPASS_ZERO							0x00000000
-#define   NV20TCL_STENCIL_OP_ZPASS_INVERT						0x0000150a
-#define   NV20TCL_STENCIL_OP_ZPASS_KEEP							0x00001e00
-#define   NV20TCL_STENCIL_OP_ZPASS_REPLACE						0x00001e01
-#define   NV20TCL_STENCIL_OP_ZPASS_INCR							0x00001e02
-#define   NV20TCL_STENCIL_OP_ZPASS_DECR							0x00001e03
-#define   NV20TCL_STENCIL_OP_ZPASS_INCR_WRAP						0x00008507
-#define   NV20TCL_STENCIL_OP_ZPASS_DECR_WRAP						0x00008508
-#define  NV20TCL_SHADE_MODEL								0x0000037c
-#define   NV20TCL_SHADE_MODEL_FLAT							0x00001d00
-#define   NV20TCL_SHADE_MODEL_SMOOTH							0x00001d01
-#define  NV20TCL_LINE_WIDTH								0x00000380
-#define  NV20TCL_POLYGON_OFFSET_FACTOR							0x00000384
-#define  NV20TCL_POLYGON_OFFSET_UNITS							0x00000388
-#define  NV20TCL_POLYGON_MODE_FRONT							0x0000038c
-#define   NV20TCL_POLYGON_MODE_FRONT_POINT						0x00001b00
-#define   NV20TCL_POLYGON_MODE_FRONT_LINE						0x00001b01
-#define   NV20TCL_POLYGON_MODE_FRONT_FILL						0x00001b02
-#define  NV20TCL_POLYGON_MODE_BACK							0x00000390
-#define   NV20TCL_POLYGON_MODE_BACK_POINT						0x00001b00
-#define   NV20TCL_POLYGON_MODE_BACK_LINE						0x00001b01
-#define   NV20TCL_POLYGON_MODE_BACK_FILL						0x00001b02
-#define  NV20TCL_DEPTH_RANGE_NEAR							0x00000394
-#define  NV20TCL_DEPTH_RANGE_FAR							0x00000398
-#define  NV20TCL_CULL_FACE								0x0000039c
-#define   NV20TCL_CULL_FACE_FRONT							0x00000404
-#define   NV20TCL_CULL_FACE_BACK							0x00000405
-#define   NV20TCL_CULL_FACE_FRONT_AND_BACK						0x00000408
-#define  NV20TCL_FRONT_FACE								0x000003a0
-#define   NV20TCL_FRONT_FACE_CW								0x00000900
-#define   NV20TCL_FRONT_FACE_CCW							0x00000901
-#define  NV20TCL_NORMALIZE_ENABLE							0x000003a4
-#define  NV20TCL_MATERIAL_FACTOR_FRONT_R						0x000003a8
-#define  NV20TCL_MATERIAL_FACTOR_FRONT_G						0x000003ac
-#define  NV20TCL_MATERIAL_FACTOR_FRONT_B						0x000003b0
-#define  NV20TCL_MATERIAL_FACTOR_FRONT_A						0x000003b4
-#define  NV20TCL_SEPARATE_SPECULAR_ENABLE						0x000003b8
-#define  NV20TCL_ENABLED_LIGHTS								0x000003bc
-#define   NV20TCL_ENABLED_LIGHTS_0_SHIFT						0
-#define   NV20TCL_ENABLED_LIGHTS_0_MASK							0x00000003
-#define    NV20TCL_ENABLED_LIGHTS_0_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_0_NONPOSITIONAL					0x00000001
-#define    NV20TCL_ENABLED_LIGHTS_0_POSITIONAL						0x00000002
-#define    NV20TCL_ENABLED_LIGHTS_0_DIRECTIONAL						0x00000003
-#define   NV20TCL_ENABLED_LIGHTS_1_SHIFT						2
-#define   NV20TCL_ENABLED_LIGHTS_1_MASK							0x0000000c
-#define    NV20TCL_ENABLED_LIGHTS_1_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_1_NONPOSITIONAL					0x00000004
-#define    NV20TCL_ENABLED_LIGHTS_1_POSITIONAL						0x00000008
-#define    NV20TCL_ENABLED_LIGHTS_1_DIRECTIONAL						0x0000000c
-#define   NV20TCL_ENABLED_LIGHTS_2_SHIFT						4
-#define   NV20TCL_ENABLED_LIGHTS_2_MASK							0x00000030
-#define    NV20TCL_ENABLED_LIGHTS_2_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_2_NONPOSITIONAL					0x00000010
-#define    NV20TCL_ENABLED_LIGHTS_2_POSITIONAL						0x00000020
-#define    NV20TCL_ENABLED_LIGHTS_2_DIRECTIONAL						0x00000030
-#define   NV20TCL_ENABLED_LIGHTS_3_SHIFT						6
-#define   NV20TCL_ENABLED_LIGHTS_3_MASK							0x000000c0
-#define    NV20TCL_ENABLED_LIGHTS_3_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_3_NONPOSITIONAL					0x00000040
-#define    NV20TCL_ENABLED_LIGHTS_3_POSITIONAL						0x00000080
-#define    NV20TCL_ENABLED_LIGHTS_3_DIRECTIONAL						0x000000c0
-#define   NV20TCL_ENABLED_LIGHTS_4_SHIFT						8
-#define   NV20TCL_ENABLED_LIGHTS_4_MASK							0x00000300
-#define    NV20TCL_ENABLED_LIGHTS_4_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_4_NONPOSITIONAL					0x00000100
-#define    NV20TCL_ENABLED_LIGHTS_4_POSITIONAL						0x00000200
-#define    NV20TCL_ENABLED_LIGHTS_4_DIRECTIONAL						0x00000300
-#define   NV20TCL_ENABLED_LIGHTS_5_SHIFT						10
-#define   NV20TCL_ENABLED_LIGHTS_5_MASK							0x00000c00
-#define    NV20TCL_ENABLED_LIGHTS_5_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_5_NONPOSITIONAL					0x00000400
-#define    NV20TCL_ENABLED_LIGHTS_5_POSITIONAL						0x00000800
-#define    NV20TCL_ENABLED_LIGHTS_5_DIRECTIONAL						0x00000c00
-#define   NV20TCL_ENABLED_LIGHTS_6_SHIFT						12
-#define   NV20TCL_ENABLED_LIGHTS_6_MASK							0x00003000
-#define    NV20TCL_ENABLED_LIGHTS_6_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_6_NONPOSITIONAL					0x00001000
-#define    NV20TCL_ENABLED_LIGHTS_6_POSITIONAL						0x00002000
-#define    NV20TCL_ENABLED_LIGHTS_6_DIRECTIONAL						0x00003000
-#define   NV20TCL_ENABLED_LIGHTS_7_SHIFT						14
-#define   NV20TCL_ENABLED_LIGHTS_7_MASK							0x0000c000
-#define    NV20TCL_ENABLED_LIGHTS_7_DISABLED						0x00000000
-#define    NV20TCL_ENABLED_LIGHTS_7_NONPOSITIONAL					0x00004000
-#define    NV20TCL_ENABLED_LIGHTS_7_POSITIONAL						0x00008000
-#define    NV20TCL_ENABLED_LIGHTS_7_DIRECTIONAL						0x0000c000
-#define  NV20TCL_TX_GEN_MODE_S(x)							(0x000003c0+((x)*16))
-#define  NV20TCL_TX_GEN_MODE_S__SIZE							0x00000004
-#define   NV20TCL_TX_GEN_MODE_S_FALSE							0x00000000
-#define   NV20TCL_TX_GEN_MODE_S_EYE_LINEAR						0x00002400
-#define   NV20TCL_TX_GEN_MODE_S_OBJECT_LINEAR						0x00002401
-#define   NV20TCL_TX_GEN_MODE_S_SPHERE_MAP						0x00002402
-#define   NV20TCL_TX_GEN_MODE_S_NORMAL_MAP						0x00008511
-#define   NV20TCL_TX_GEN_MODE_S_REFLECTION_MAP						0x00008512
-#define  NV20TCL_TX_GEN_MODE_T(x)							(0x000003c4+((x)*16))
-#define  NV20TCL_TX_GEN_MODE_T__SIZE							0x00000004
-#define   NV20TCL_TX_GEN_MODE_T_FALSE							0x00000000
-#define   NV20TCL_TX_GEN_MODE_T_EYE_LINEAR						0x00002400
-#define   NV20TCL_TX_GEN_MODE_T_OBJECT_LINEAR						0x00002401
-#define   NV20TCL_TX_GEN_MODE_T_SPHERE_MAP						0x00002402
-#define   NV20TCL_TX_GEN_MODE_T_NORMAL_MAP						0x00008511
-#define   NV20TCL_TX_GEN_MODE_T_REFLECTION_MAP						0x00008512
-#define  NV20TCL_TX_GEN_MODE_R(x)							(0x000003c8+((x)*16))
-#define  NV20TCL_TX_GEN_MODE_R__SIZE							0x00000004
-#define   NV20TCL_TX_GEN_MODE_R_FALSE							0x00000000
-#define   NV20TCL_TX_GEN_MODE_R_EYE_LINEAR						0x00002400
-#define   NV20TCL_TX_GEN_MODE_R_OBJECT_LINEAR						0x00002401
-#define   NV20TCL_TX_GEN_MODE_R_SPHERE_MAP						0x00002402
-#define   NV20TCL_TX_GEN_MODE_R_NORMAL_MAP						0x00008511
-#define   NV20TCL_TX_GEN_MODE_R_REFLECTION_MAP						0x00008512
-#define  NV20TCL_TX_GEN_MODE_Q(x)							(0x000003cc+((x)*16))
-#define  NV20TCL_TX_GEN_MODE_Q__SIZE							0x00000004
-#define   NV20TCL_TX_GEN_MODE_Q_FALSE							0x00000000
-#define   NV20TCL_TX_GEN_MODE_Q_EYE_LINEAR						0x00002400
-#define   NV20TCL_TX_GEN_MODE_Q_OBJECT_LINEAR						0x00002401
-#define   NV20TCL_TX_GEN_MODE_Q_SPHERE_MAP						0x00002402
-#define   NV20TCL_TX_GEN_MODE_Q_NORMAL_MAP						0x00008511
-#define   NV20TCL_TX_GEN_MODE_Q_REFLECTION_MAP						0x00008512
-#define  NV20TCL_TX_MATRIX_ENABLE(x)							(0x00000420+((x)*4))
-#define  NV20TCL_TX_MATRIX_ENABLE__SIZE							0x00000004
-#define  NV20TCL_POINT_SIZE								0x0000043c
-#define  NV20TCL_MODELVIEW0_MATRIX(x)							(0x00000480+((x)*4))
-#define  NV20TCL_MODELVIEW0_MATRIX__SIZE						0x00000010
-#define  NV20TCL_MODELVIEW1_MATRIX(x)							(0x000004c0+((x)*4))
-#define  NV20TCL_MODELVIEW1_MATRIX__SIZE						0x00000010
-#define  NV20TCL_MODELVIEW2_MATRIX(x)							(0x00000500+((x)*4))
-#define  NV20TCL_MODELVIEW2_MATRIX__SIZE						0x00000010
-#define  NV20TCL_MODELVIEW3_MATRIX(x)							(0x00000540+((x)*4))
-#define  NV20TCL_MODELVIEW3_MATRIX__SIZE						0x00000010
-#define  NV20TCL_INVERSE_MODELVIEW0_MATRIX(x)						(0x00000580+((x)*4))
-#define  NV20TCL_INVERSE_MODELVIEW0_MATRIX__SIZE					0x00000010
-#define  NV20TCL_INVERSE_MODELVIEW1_MATRIX(x)						(0x000005c0+((x)*4))
-#define  NV20TCL_INVERSE_MODELVIEW1_MATRIX__SIZE					0x00000010
-#define  NV20TCL_INVERSE_MODELVIEW2_MATRIX(x)						(0x00000600+((x)*4))
-#define  NV20TCL_INVERSE_MODELVIEW2_MATRIX__SIZE					0x00000010
-#define  NV20TCL_INVERSE_MODELVIEW3_MATRIX(x)						(0x00000640+((x)*4))
-#define  NV20TCL_INVERSE_MODELVIEW3_MATRIX__SIZE					0x00000010
-#define  NV20TCL_PROJECTION_MATRIX(x)							(0x00000680+((x)*4))
-#define  NV20TCL_PROJECTION_MATRIX__SIZE						0x00000010
-#define  NV20TCL_TX0_MATRIX(x)								(0x000006c0+((x)*4))
-#define  NV20TCL_TX0_MATRIX__SIZE							0x00000010
-#define  NV20TCL_TX1_MATRIX(x)								(0x00000700+((x)*4))
-#define  NV20TCL_TX1_MATRIX__SIZE							0x00000010
-#define  NV20TCL_TX2_MATRIX(x)								(0x00000740+((x)*4))
-#define  NV20TCL_TX2_MATRIX__SIZE							0x00000010
-#define  NV20TCL_TX3_MATRIX(x)								(0x00000780+((x)*4))
-#define  NV20TCL_TX3_MATRIX__SIZE							0x00000010
-#define  NV20TCL_TX_GEN_COEFF_S_A(x)							(0x00000840+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_S_A__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_S_B(x)							(0x00000844+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_S_B__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_S_C(x)							(0x00000848+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_S_C__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_S_D(x)							(0x0000084c+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_S_D__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_T_A(x)							(0x00000850+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_T_A__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_T_B(x)							(0x00000854+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_T_B__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_T_C(x)							(0x00000858+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_T_C__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_T_D(x)							(0x0000085c+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_T_D__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_R_A(x)							(0x00000860+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_R_A__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_R_B(x)							(0x00000864+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_R_B__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_R_C(x)							(0x00000868+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_R_C__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_R_D(x)							(0x0000086c+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_R_D__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_Q_A(x)							(0x00000870+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_Q_A__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_Q_B(x)							(0x00000874+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_Q_B__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_Q_C(x)							(0x00000878+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_Q_C__SIZE							0x00000004
-#define  NV20TCL_TX_GEN_COEFF_Q_D(x)							(0x0000087c+((x)*64))
-#define  NV20TCL_TX_GEN_COEFF_Q_D__SIZE							0x00000004
-#define  NV20TCL_FOG_EQUATION_CONSTANT							0x000009c0
-#define  NV20TCL_FOG_EQUATION_LINEAR							0x000009c4
-#define  NV20TCL_FOG_EQUATION_QUADRATIC							0x000009c8
-#define  NV20TCL_FRONT_MATERIAL_SHININESS(x)						(0x000009e0+((x)*4))
-#define  NV20TCL_FRONT_MATERIAL_SHININESS__SIZE						0x00000006
-#define  NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R						0x00000a10
-#define  NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_G						0x00000a14
-#define  NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_B						0x00000a18
-#define  NV20TCL_VIEWPORT_TRANSLATE_X							0x00000a20
-#define  NV20TCL_VIEWPORT_TRANSLATE_Y							0x00000a24
-#define  NV20TCL_VIEWPORT_TRANSLATE_Z							0x00000a28
-#define  NV20TCL_VIEWPORT_TRANSLATE_W							0x00000a2c
-#define  NV20TCL_POINT_PARAMETER(x)							(0x00000a30+((x)*4))
-#define  NV20TCL_POINT_PARAMETER__SIZE							0x00000008
-#define  NV20TCL_RC_CONSTANT_COLOR0(x)							(0x00000a60+((x)*4))
-#define  NV20TCL_RC_CONSTANT_COLOR0__SIZE						0x00000008
-#define   NV20TCL_RC_CONSTANT_COLOR0_B_SHIFT						0
-#define   NV20TCL_RC_CONSTANT_COLOR0_B_MASK						0x000000ff
-#define   NV20TCL_RC_CONSTANT_COLOR0_G_SHIFT						8
-#define   NV20TCL_RC_CONSTANT_COLOR0_G_MASK						0x0000ff00
-#define   NV20TCL_RC_CONSTANT_COLOR0_R_SHIFT						16
-#define   NV20TCL_RC_CONSTANT_COLOR0_R_MASK						0x00ff0000
-#define   NV20TCL_RC_CONSTANT_COLOR0_A_SHIFT						24
-#define   NV20TCL_RC_CONSTANT_COLOR0_A_MASK						0xff000000
-#define  NV20TCL_RC_CONSTANT_COLOR1(x)							(0x00000a80+((x)*4))
-#define  NV20TCL_RC_CONSTANT_COLOR1__SIZE						0x00000008
-#define   NV20TCL_RC_CONSTANT_COLOR1_B_SHIFT						0
-#define   NV20TCL_RC_CONSTANT_COLOR1_B_MASK						0x000000ff
-#define   NV20TCL_RC_CONSTANT_COLOR1_G_SHIFT						8
-#define   NV20TCL_RC_CONSTANT_COLOR1_G_MASK						0x0000ff00
-#define   NV20TCL_RC_CONSTANT_COLOR1_R_SHIFT						16
-#define   NV20TCL_RC_CONSTANT_COLOR1_R_MASK						0x00ff0000
-#define   NV20TCL_RC_CONSTANT_COLOR1_A_SHIFT						24
-#define   NV20TCL_RC_CONSTANT_COLOR1_A_MASK						0xff000000
-#define  NV20TCL_RC_OUT_ALPHA(x)							(0x00000aa0+((x)*4))
-#define  NV20TCL_RC_OUT_ALPHA__SIZE							0x00000008
-#define   NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SHIFT						0
-#define   NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_MASK						0x0000000f
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0				0x00000001
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1				0x00000002
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_FOG						0x00000003
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR					0x00000004
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR				0x00000005
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0					0x00000008
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1					0x00000009
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0					0x0000000c
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE1					0x0000000d
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F					0x0000000f
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2					0x0000000a
-#define    NV20TCL_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3					0x0000000b
-#define   NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SHIFT						4
-#define   NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_MASK						0x000000f0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0				0x00000010
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1				0x00000020
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_FOG						0x00000030
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR					0x00000040
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR				0x00000050
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0					0x00000080
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1					0x00000090
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0					0x000000c0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE1					0x000000d0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000000e0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F					0x000000f0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2					0x000000a0
-#define    NV20TCL_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3					0x000000b0
-#define   NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SHIFT						8
-#define   NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_MASK						0x00000f00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0				0x00000100
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1				0x00000200
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_FOG						0x00000300
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR				0x00000400
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR				0x00000500
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0					0x00000800
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1					0x00000900
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0					0x00000c00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1					0x00000d00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F					0x00000f00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2					0x00000a00
-#define    NV20TCL_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3					0x00000b00
-#define   NV20TCL_RC_OUT_ALPHA_CD_DOT_PRODUCT						(1 << 12)
-#define   NV20TCL_RC_OUT_ALPHA_AB_DOT_PRODUCT						(1 << 13)
-#define   NV20TCL_RC_OUT_ALPHA_MUX_SUM							(1 << 14)
-#define   NV20TCL_RC_OUT_ALPHA_BIAS							(1 << 15)
-#define    NV20TCL_RC_OUT_ALPHA_BIAS_NONE						0x00000000
-#define    NV20TCL_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF				0x00008000
-#define   NV20TCL_RC_OUT_ALPHA_SCALE_SHIFT						16
-#define   NV20TCL_RC_OUT_ALPHA_SCALE_MASK						0x00030000
-#define    NV20TCL_RC_OUT_ALPHA_SCALE_NONE						0x00000000
-#define    NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO					0x00010000
-#define    NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR					0x00020000
-#define    NV20TCL_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF					0x00030000
-#define  NV20TCL_RC_IN_RGB(x)								(0x00000ac0+((x)*4))
-#define  NV20TCL_RC_IN_RGB__SIZE							0x00000008
-#define   NV20TCL_RC_IN_RGB_D_INPUT_SHIFT						0
-#define   NV20TCL_RC_IN_RGB_D_INPUT_MASK						0x0000000f
-#define    NV20TCL_RC_IN_RGB_D_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0					0x00000001
-#define    NV20TCL_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1					0x00000002
-#define    NV20TCL_RC_IN_RGB_D_INPUT_FOG						0x00000003
-#define    NV20TCL_RC_IN_RGB_D_INPUT_PRIMARY_COLOR					0x00000004
-#define    NV20TCL_RC_IN_RGB_D_INPUT_SECONDARY_COLOR					0x00000005
-#define    NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE0						0x00000008
-#define    NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE1						0x00000009
-#define    NV20TCL_RC_IN_RGB_D_INPUT_SPARE0						0x0000000c
-#define    NV20TCL_RC_IN_RGB_D_INPUT_SPARE1						0x0000000d
-#define    NV20TCL_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV20TCL_RC_IN_RGB_D_INPUT_E_TIMES_F						0x0000000f
-#define    NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE2						0x0000000a
-#define    NV20TCL_RC_IN_RGB_D_INPUT_TEXTURE3						0x0000000b
-#define   NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE						(1 <<  4)
-#define    NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA					0x00000010
-#define   NV20TCL_RC_IN_RGB_D_MAPPING_SHIFT						5
-#define   NV20TCL_RC_IN_RGB_D_MAPPING_MASK						0x000000e0
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT					0x00000020
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL					0x00000040
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE					0x00000060
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL					0x00000080
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE					0x000000a0
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY					0x000000c0
-#define    NV20TCL_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE					0x000000e0
-#define   NV20TCL_RC_IN_RGB_C_INPUT_SHIFT						8
-#define   NV20TCL_RC_IN_RGB_C_INPUT_MASK						0x00000f00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0					0x00000100
-#define    NV20TCL_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1					0x00000200
-#define    NV20TCL_RC_IN_RGB_C_INPUT_FOG						0x00000300
-#define    NV20TCL_RC_IN_RGB_C_INPUT_PRIMARY_COLOR					0x00000400
-#define    NV20TCL_RC_IN_RGB_C_INPUT_SECONDARY_COLOR					0x00000500
-#define    NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE0						0x00000800
-#define    NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE1						0x00000900
-#define    NV20TCL_RC_IN_RGB_C_INPUT_SPARE0						0x00000c00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_SPARE1						0x00000d00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_E_TIMES_F						0x00000f00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE2						0x00000a00
-#define    NV20TCL_RC_IN_RGB_C_INPUT_TEXTURE3						0x00000b00
-#define   NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE						(1 << 12)
-#define    NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA					0x00001000
-#define   NV20TCL_RC_IN_RGB_C_MAPPING_SHIFT						13
-#define   NV20TCL_RC_IN_RGB_C_MAPPING_MASK						0x0000e000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT					0x00002000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL					0x00004000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE					0x00006000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL					0x00008000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE					0x0000a000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY					0x0000c000
-#define    NV20TCL_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE					0x0000e000
-#define   NV20TCL_RC_IN_RGB_B_INPUT_SHIFT						16
-#define   NV20TCL_RC_IN_RGB_B_INPUT_MASK						0x000f0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0					0x00010000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1					0x00020000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_FOG						0x00030000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_PRIMARY_COLOR					0x00040000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_SECONDARY_COLOR					0x00050000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE0						0x00080000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE1						0x00090000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_SPARE0						0x000c0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_SPARE1						0x000d0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000e0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_E_TIMES_F						0x000f0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE2						0x000a0000
-#define    NV20TCL_RC_IN_RGB_B_INPUT_TEXTURE3						0x000b0000
-#define   NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE						(1 << 20)
-#define    NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA					0x00100000
-#define   NV20TCL_RC_IN_RGB_B_MAPPING_SHIFT						21
-#define   NV20TCL_RC_IN_RGB_B_MAPPING_MASK						0x00e00000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT					0x00200000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL					0x00400000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE					0x00600000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL					0x00800000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE					0x00a00000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY					0x00c00000
-#define    NV20TCL_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE					0x00e00000
-#define   NV20TCL_RC_IN_RGB_A_INPUT_SHIFT						24
-#define   NV20TCL_RC_IN_RGB_A_INPUT_MASK						0x0f000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_ZERO						0x00000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0					0x01000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1					0x02000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_FOG						0x03000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_PRIMARY_COLOR					0x04000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_SECONDARY_COLOR					0x05000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE0						0x08000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE1						0x09000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_SPARE0						0x0c000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_SPARE1						0x0d000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0e000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_E_TIMES_F						0x0f000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE2						0x0a000000
-#define    NV20TCL_RC_IN_RGB_A_INPUT_TEXTURE3						0x0b000000
-#define   NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE						(1 << 28)
-#define    NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_RGB					0x00000000
-#define    NV20TCL_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA					0x10000000
-#define   NV20TCL_RC_IN_RGB_A_MAPPING_SHIFT						29
-#define   NV20TCL_RC_IN_RGB_A_MAPPING_MASK						0xe0000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY				0x00000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT					0x20000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL					0x40000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE					0x60000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL					0x80000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE					0xa0000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY					0xc0000000
-#define    NV20TCL_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE					0xe0000000
-#define  NV20TCL_VIEWPORT_SCALE_X							0x00000af0
-#define  NV20TCL_VIEWPORT_SCALE_Y							0x00000af4
-#define  NV20TCL_VIEWPORT_SCALE_Z							0x00000af8
-#define  NV20TCL_VIEWPORT_SCALE_W							0x00000afc
-#define  NV20TCL_VP_UPLOAD_INST(x)							(0x00000b00+((x)*4))
-#define  NV20TCL_VP_UPLOAD_INST__SIZE							0x00000004
-#define  NV20TCL_VP_UPLOAD_CONST(x)							(0x00000b80+((x)*4))
-#define  NV20TCL_VP_UPLOAD_CONST__SIZE							0x00000004
-#define  NV20TCL_LIGHT_BACK_AMBIENT_R(x)						(0x00000c00+((x)*64))
-#define  NV20TCL_LIGHT_BACK_AMBIENT_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_AMBIENT_G(x)						(0x00000c04+((x)*64))
-#define  NV20TCL_LIGHT_BACK_AMBIENT_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_AMBIENT_B(x)						(0x00000c08+((x)*64))
-#define  NV20TCL_LIGHT_BACK_AMBIENT_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_R(x)						(0x00000c0c+((x)*64))
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_G(x)						(0x00000c10+((x)*64))
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_B(x)						(0x00000c14+((x)*64))
-#define  NV20TCL_LIGHT_BACK_DIFFUSE_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_SPECULAR_R(x)						(0x00000c18+((x)*64))
-#define  NV20TCL_LIGHT_BACK_SPECULAR_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_SPECULAR_G(x)						(0x00000c1c+((x)*64))
-#define  NV20TCL_LIGHT_BACK_SPECULAR_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_BACK_SPECULAR_B(x)						(0x00000c20+((x)*64))
-#define  NV20TCL_LIGHT_BACK_SPECULAR_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_R(x)						(0x00001000+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_G(x)						(0x00001004+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_B(x)						(0x00001008+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_AMBIENT_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_R(x)						(0x0000100c+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_G(x)						(0x00001010+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_B(x)						(0x00001014+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_DIFFUSE_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_R(x)						(0x00001018+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_R__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_G(x)						(0x0000101c+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_G__SIZE						0x00000008
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_B(x)						(0x00001020+((x)*128))
-#define  NV20TCL_LIGHT_FRONT_SPECULAR_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_HALF_VECTOR_X(x)							(0x00001028+((x)*128))
-#define  NV20TCL_LIGHT_HALF_VECTOR_X__SIZE						0x00000008
-#define  NV20TCL_LIGHT_HALF_VECTOR_Y(x)							(0x0000102c+((x)*128))
-#define  NV20TCL_LIGHT_HALF_VECTOR_Y__SIZE						0x00000008
-#define  NV20TCL_LIGHT_HALF_VECTOR_Z(x)							(0x00001030+((x)*128))
-#define  NV20TCL_LIGHT_HALF_VECTOR_Z__SIZE						0x00000008
-#define  NV20TCL_LIGHT_DIRECTION_X(x)							(0x00001034+((x)*128))
-#define  NV20TCL_LIGHT_DIRECTION_X__SIZE						0x00000008
-#define  NV20TCL_LIGHT_DIRECTION_Y(x)							(0x00001038+((x)*128))
-#define  NV20TCL_LIGHT_DIRECTION_Y__SIZE						0x00000008
-#define  NV20TCL_LIGHT_DIRECTION_Z(x)							(0x0000103c+((x)*128))
-#define  NV20TCL_LIGHT_DIRECTION_Z__SIZE						0x00000008
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_A(x)							(0x00001040+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_A__SIZE						0x00000008
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_B(x)							(0x00001044+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_B__SIZE						0x00000008
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_C(x)							(0x00001048+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_C__SIZE						0x00000008
-#define  NV20TCL_LIGHT_SPOT_DIR_X(x)							(0x0000104c+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_DIR_X__SIZE							0x00000008
-#define  NV20TCL_LIGHT_SPOT_DIR_Y(x)							(0x00001050+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_DIR_Y__SIZE							0x00000008
-#define  NV20TCL_LIGHT_SPOT_DIR_Z(x)							(0x00001054+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_DIR_Z__SIZE							0x00000008
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_D(x)							(0x00001058+((x)*128))
-#define  NV20TCL_LIGHT_SPOT_CUTOFF_D__SIZE						0x00000008
-#define  NV20TCL_LIGHT_POSITION_X(x)							(0x0000105c+((x)*128))
-#define  NV20TCL_LIGHT_POSITION_X__SIZE							0x00000008
-#define  NV20TCL_LIGHT_POSITION_Y(x)							(0x00001060+((x)*128))
-#define  NV20TCL_LIGHT_POSITION_Y__SIZE							0x00000008
-#define  NV20TCL_LIGHT_POSITION_Z(x)							(0x00001064+((x)*128))
-#define  NV20TCL_LIGHT_POSITION_Z__SIZE							0x00000008
-#define  NV20TCL_LIGHT_ATTENUATION_CONSTANT(x)						(0x00001068+((x)*128))
-#define  NV20TCL_LIGHT_ATTENUATION_CONSTANT__SIZE					0x00000008
-#define  NV20TCL_LIGHT_ATTENUATION_LINEAR(x)						(0x0000106c+((x)*128))
-#define  NV20TCL_LIGHT_ATTENUATION_LINEAR__SIZE						0x00000008
-#define  NV20TCL_LIGHT_ATTENUATION_QUADRATIC(x)						(0x00001070+((x)*128))
-#define  NV20TCL_LIGHT_ATTENUATION_QUADRATIC__SIZE					0x00000008
-#define  NV20TCL_POLYGON_STIPPLE_ENABLE							0x0000147c
-#define  NV20TCL_POLYGON_STIPPLE_PATTERN(x)						(0x00001480+((x)*4))
-#define  NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE						0x00000020
-#define  NV20TCL_VERTEX_POS_3F_X							0x00001500
-#define  NV20TCL_VERTEX_POS_3F_Y							0x00001504
-#define  NV20TCL_VERTEX_POS_3F_Z							0x00001508
-#define  NV20TCL_VERTEX_POS_4F_X							0x00001518
-#define  NV20TCL_VERTEX_POS_4F_Y							0x0000151c
-#define  NV20TCL_VERTEX_POS_4F_Z							0x00001520
-#define  NV20TCL_VERTEX_POS_3I_XY							0x00001528
-#define   NV20TCL_VERTEX_POS_3I_XY_X_SHIFT						0
-#define   NV20TCL_VERTEX_POS_3I_XY_X_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_POS_3I_XY_Y_SHIFT						16
-#define   NV20TCL_VERTEX_POS_3I_XY_Y_MASK						0xffff0000
-#define  NV20TCL_VERTEX_POS_3I_Z							0x0000152c
-#define   NV20TCL_VERTEX_POS_3I_Z_Z_SHIFT						0
-#define   NV20TCL_VERTEX_POS_3I_Z_Z_MASK						0x0000ffff
-#define  NV20TCL_VERTEX_NOR_3F_X							0x00001530
-#define  NV20TCL_VERTEX_NOR_3F_Y							0x00001534
-#define  NV20TCL_VERTEX_NOR_3F_Z							0x00001538
-#define  NV20TCL_VERTEX_NOR_3I_XY							0x00001540
-#define   NV20TCL_VERTEX_NOR_3I_XY_X_SHIFT						0
-#define   NV20TCL_VERTEX_NOR_3I_XY_X_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_NOR_3I_XY_Y_SHIFT						16
-#define   NV20TCL_VERTEX_NOR_3I_XY_Y_MASK						0xffff0000
-#define  NV20TCL_VERTEX_NOR_3I_Z							0x00001544
-#define   NV20TCL_VERTEX_NOR_3I_Z_Z_SHIFT						0
-#define   NV20TCL_VERTEX_NOR_3I_Z_Z_MASK						0x0000ffff
-#define  NV20TCL_VERTEX_COL_4F_X							0x00001550
-#define  NV20TCL_VERTEX_COL_4F_Y							0x00001554
-#define  NV20TCL_VERTEX_COL_4F_Z							0x00001558
-#define  NV20TCL_VERTEX_COL_4F_W							0x0000155c
-#define  NV20TCL_VERTEX_COL_3F_X							0x00001560
-#define  NV20TCL_VERTEX_COL_3F_Y							0x00001564
-#define  NV20TCL_VERTEX_COL_3F_Z							0x00001568
-#define  NV20TCL_VERTEX_COL_4I								0x0000156c
-#define   NV20TCL_VERTEX_COL_4I_R_SHIFT							0
-#define   NV20TCL_VERTEX_COL_4I_R_MASK							0x000000ff
-#define   NV20TCL_VERTEX_COL_4I_G_SHIFT							8
-#define   NV20TCL_VERTEX_COL_4I_G_MASK							0x0000ff00
-#define   NV20TCL_VERTEX_COL_4I_B_SHIFT							16
-#define   NV20TCL_VERTEX_COL_4I_B_MASK							0x00ff0000
-#define   NV20TCL_VERTEX_COL_4I_A_SHIFT							24
-#define   NV20TCL_VERTEX_COL_4I_A_MASK							0xff000000
-#define  NV20TCL_VERTEX_COL2_3F_X							0x00001580
-#define  NV20TCL_VERTEX_COL2_3F_Y							0x00001584
-#define  NV20TCL_VERTEX_COL2_3F_Z							0x00001588
-#define  NV20TCL_VERTEX_COL2_4I								0x0000158c
-#define   NV20TCL_VERTEX_COL2_4I_R_SHIFT						0
-#define   NV20TCL_VERTEX_COL2_4I_R_MASK							0x000000ff
-#define   NV20TCL_VERTEX_COL2_4I_G_SHIFT						8
-#define   NV20TCL_VERTEX_COL2_4I_G_MASK							0x0000ff00
-#define   NV20TCL_VERTEX_COL2_4I_B_SHIFT						16
-#define   NV20TCL_VERTEX_COL2_4I_B_MASK							0x00ff0000
-#define   NV20TCL_VERTEX_COL2_4I_A_SHIFT						24
-#define   NV20TCL_VERTEX_COL2_4I_A_MASK							0xff000000
-#define  NV20TCL_VERTEX_TX0_2F_S							0x00001590
-#define  NV20TCL_VERTEX_TX0_2F_T							0x00001594
-#define  NV20TCL_VERTEX_TX0_2I								0x00001598
-#define   NV20TCL_VERTEX_TX0_2I_S_SHIFT							0
-#define   NV20TCL_VERTEX_TX0_2I_S_MASK							0x0000ffff
-#define   NV20TCL_VERTEX_TX0_2I_T_SHIFT							16
-#define   NV20TCL_VERTEX_TX0_2I_T_MASK							0xffff0000
-#define  NV20TCL_VERTEX_TX0_4F_S							0x000015a0
-#define  NV20TCL_VERTEX_TX0_4F_T							0x000015a4
-#define  NV20TCL_VERTEX_TX0_4F_R							0x000015a8
-#define  NV20TCL_VERTEX_TX0_4F_Q							0x000015ac
-#define  NV20TCL_VERTEX_TX0_4I_ST							0x000015b0
-#define   NV20TCL_VERTEX_TX0_4I_ST_S_SHIFT						0
-#define   NV20TCL_VERTEX_TX0_4I_ST_S_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX0_4I_ST_T_SHIFT						16
-#define   NV20TCL_VERTEX_TX0_4I_ST_T_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX0_4I_RQ							0x000015b4
-#define   NV20TCL_VERTEX_TX0_4I_RQ_R_SHIFT						0
-#define   NV20TCL_VERTEX_TX0_4I_RQ_R_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX0_4I_RQ_Q_SHIFT						16
-#define   NV20TCL_VERTEX_TX0_4I_RQ_Q_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX1_2F_S							0x000015b8
-#define  NV20TCL_VERTEX_TX1_2F_T							0x000015bc
-#define  NV20TCL_VERTEX_TX1_2I								0x000015c0
-#define   NV20TCL_VERTEX_TX1_2I_S_SHIFT							0
-#define   NV20TCL_VERTEX_TX1_2I_S_MASK							0x0000ffff
-#define   NV20TCL_VERTEX_TX1_2I_T_SHIFT							16
-#define   NV20TCL_VERTEX_TX1_2I_T_MASK							0xffff0000
-#define  NV20TCL_VERTEX_TX1_4F_S							0x000015c8
-#define  NV20TCL_VERTEX_TX1_4F_T							0x000015cc
-#define  NV20TCL_VERTEX_TX1_4F_R							0x000015d0
-#define  NV20TCL_VERTEX_TX1_4F_Q							0x000015d4
-#define  NV20TCL_VERTEX_TX1_4I_ST							0x000015d8
-#define   NV20TCL_VERTEX_TX1_4I_ST_S_SHIFT						0
-#define   NV20TCL_VERTEX_TX1_4I_ST_S_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX1_4I_ST_T_SHIFT						16
-#define   NV20TCL_VERTEX_TX1_4I_ST_T_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX1_4I_RQ							0x000015dc
-#define   NV20TCL_VERTEX_TX1_4I_RQ_R_SHIFT						0
-#define   NV20TCL_VERTEX_TX1_4I_RQ_R_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX1_4I_RQ_Q_SHIFT						16
-#define   NV20TCL_VERTEX_TX1_4I_RQ_Q_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX2_2F_S							0x000015e0
-#define  NV20TCL_VERTEX_TX2_2F_T							0x000015e4
-#define  NV20TCL_VERTEX_TX2_2I								0x000015e8
-#define   NV20TCL_VERTEX_TX2_2I_S_SHIFT							0
-#define   NV20TCL_VERTEX_TX2_2I_S_MASK							0x0000ffff
-#define   NV20TCL_VERTEX_TX2_2I_T_SHIFT							16
-#define   NV20TCL_VERTEX_TX2_2I_T_MASK							0xffff0000
-#define  NV20TCL_VERTEX_TX2_4F_S							0x000015f0
-#define  NV20TCL_VERTEX_TX2_4F_T							0x000015f4
-#define  NV20TCL_VERTEX_TX2_4F_R							0x000015f8
-#define  NV20TCL_VERTEX_TX2_4F_Q							0x000015fc
-#define  NV20TCL_VERTEX_TX2_4I_ST							0x00001600
-#define   NV20TCL_VERTEX_TX2_4I_ST_S_SHIFT						0
-#define   NV20TCL_VERTEX_TX2_4I_ST_S_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX2_4I_ST_T_SHIFT						16
-#define   NV20TCL_VERTEX_TX2_4I_ST_T_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX2_4I_RQ							0x00001604
-#define   NV20TCL_VERTEX_TX2_4I_RQ_R_SHIFT						0
-#define   NV20TCL_VERTEX_TX2_4I_RQ_R_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX2_4I_RQ_Q_SHIFT						16
-#define   NV20TCL_VERTEX_TX2_4I_RQ_Q_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX3_2F_S							0x00001608
-#define  NV20TCL_VERTEX_TX3_2F_T							0x0000160c
-#define  NV20TCL_VERTEX_TX3_2I								0x00001610
-#define   NV20TCL_VERTEX_TX3_2I_S_SHIFT							0
-#define   NV20TCL_VERTEX_TX3_2I_S_MASK							0x0000ffff
-#define   NV20TCL_VERTEX_TX3_2I_T_SHIFT							16
-#define   NV20TCL_VERTEX_TX3_2I_T_MASK							0xffff0000
-#define  NV20TCL_VERTEX_TX3_4F_S							0x00001620
-#define  NV20TCL_VERTEX_TX3_4F_T							0x00001624
-#define  NV20TCL_VERTEX_TX3_4F_R							0x00001628
-#define  NV20TCL_VERTEX_TX3_4F_Q							0x0000162c
-#define  NV20TCL_VERTEX_TX3_4I_ST							0x00001630
-#define   NV20TCL_VERTEX_TX3_4I_ST_S_SHIFT						0
-#define   NV20TCL_VERTEX_TX3_4I_ST_S_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX3_4I_ST_T_SHIFT						16
-#define   NV20TCL_VERTEX_TX3_4I_ST_T_MASK						0xffff0000
-#define  NV20TCL_VERTEX_TX3_4I_RQ							0x00001634
-#define   NV20TCL_VERTEX_TX3_4I_RQ_R_SHIFT						0
-#define   NV20TCL_VERTEX_TX3_4I_RQ_R_MASK						0x0000ffff
-#define   NV20TCL_VERTEX_TX3_4I_RQ_Q_SHIFT						16
-#define   NV20TCL_VERTEX_TX3_4I_RQ_Q_MASK						0xffff0000
-#define  NV20TCL_VERTEX_FOG_1F								0x00001698
-#define  NV20TCL_EDGEFLAG_ENABLE							0x000016bc
-#define  NV20TCL_VTX_CACHE_INVALIDATE							0x00001710
-#define  NV20TCL_VTXBUF_ADDRESS(x)							(0x00001720+((x)*4))
-#define  NV20TCL_VTXBUF_ADDRESS__SIZE							0x00000010
-#define   NV20TCL_VTXBUF_ADDRESS_DMA1							(1 << 31)
-#define   NV20TCL_VTXBUF_ADDRESS_OFFSET_SHIFT						0
-#define   NV20TCL_VTXBUF_ADDRESS_OFFSET_MASK						0x0fffffff
-#define  NV20TCL_VTXFMT(x)								(0x00001760+((x)*4))
-#define  NV20TCL_VTXFMT__SIZE								0x00000010
-#define   NV20TCL_VTXFMT_TYPE_SHIFT							0
-#define   NV20TCL_VTXFMT_TYPE_MASK							0x0000000f
-#define    NV20TCL_VTXFMT_TYPE_FLOAT							0x00000002
-#define    NV20TCL_VTXFMT_TYPE_UBYTE							0x00000004
-#define    NV20TCL_VTXFMT_TYPE_USHORT							0x00000005
-#define   NV20TCL_VTXFMT_SIZE_SHIFT							4
-#define   NV20TCL_VTXFMT_SIZE_MASK							0x000000f0
-#define   NV20TCL_VTXFMT_STRIDE_SHIFT							8
-#define   NV20TCL_VTXFMT_STRIDE_MASK							0x0000ff00
-#define  NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R						0x000017a0
-#define  NV20TCL_LIGHT_MODEL_BACK_AMBIENT_G						0x000017a4
-#define  NV20TCL_LIGHT_MODEL_BACK_AMBIENT_B						0x000017a8
-#define  NV20TCL_MATERIAL_FACTOR_BACK_A							0x000017ac
-#define  NV20TCL_MATERIAL_FACTOR_BACK_R							0x000017b0
-#define  NV20TCL_MATERIAL_FACTOR_BACK_G							0x000017b4
-#define  NV20TCL_MATERIAL_FACTOR_BACK_B							0x000017b8
-#define  NV20TCL_COLOR_LOGIC_OP_ENABLE							0x000017bc
-#define  NV20TCL_COLOR_LOGIC_OP_OP							0x000017c0
-#define   NV20TCL_COLOR_LOGIC_OP_OP_CLEAR						0x00001500
-#define   NV20TCL_COLOR_LOGIC_OP_OP_AND							0x00001501
-#define   NV20TCL_COLOR_LOGIC_OP_OP_AND_REVERSE						0x00001502
-#define   NV20TCL_COLOR_LOGIC_OP_OP_COPY						0x00001503
-#define   NV20TCL_COLOR_LOGIC_OP_OP_AND_INVERTED					0x00001504
-#define   NV20TCL_COLOR_LOGIC_OP_OP_NOOP						0x00001505
-#define   NV20TCL_COLOR_LOGIC_OP_OP_XOR							0x00001506
-#define   NV20TCL_COLOR_LOGIC_OP_OP_OR							0x00001507
-#define   NV20TCL_COLOR_LOGIC_OP_OP_NOR							0x00001508
-#define   NV20TCL_COLOR_LOGIC_OP_OP_EQUIV						0x00001509
-#define   NV20TCL_COLOR_LOGIC_OP_OP_INVERT						0x0000150a
-#define   NV20TCL_COLOR_LOGIC_OP_OP_OR_REVERSE						0x0000150b
-#define   NV20TCL_COLOR_LOGIC_OP_OP_COPY_INVERTED					0x0000150c
-#define   NV20TCL_COLOR_LOGIC_OP_OP_OR_INVERTED						0x0000150d
-#define   NV20TCL_COLOR_LOGIC_OP_OP_NAND						0x0000150e
-#define   NV20TCL_COLOR_LOGIC_OP_OP_SET							0x0000150f
-#define  NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE						0x000017c4
-#define  NV20TCL_TX_SHADER_CULL_MODE							0x000017f8
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX0_S						(1 <<  0)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_S_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_S_LESS					0x00000001
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX0_T						(1 <<  1)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_T_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_T_LESS					0x00000002
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX0_R						(1 <<  2)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_R_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_R_LESS					0x00000004
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX0_Q						(1 <<  3)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX0_Q_LESS					0x00000008
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX1_S						(1 <<  4)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_S_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_S_LESS					0x00000010
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX1_T						(1 <<  5)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_T_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_T_LESS					0x00000020
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX1_R						(1 <<  6)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_R_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_R_LESS					0x00000040
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX1_Q						(1 <<  7)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX1_Q_LESS					0x00000080
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX2_S						(1 <<  8)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_S_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_S_LESS					0x00000100
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX2_T						(1 <<  9)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_T_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_T_LESS					0x00000200
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX2_R						(1 << 10)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_R_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_R_LESS					0x00000400
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX2_Q						(1 << 11)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX2_Q_LESS					0x00000800
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX3_S						(1 << 12)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_S_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_S_LESS					0x00001000
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX3_T						(1 << 13)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_T_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_T_LESS					0x00002000
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX3_R						(1 << 14)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_R_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_R_LESS					0x00004000
-#define   NV20TCL_TX_SHADER_CULL_MODE_TX3_Q						(1 << 15)
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_GEQUAL					0x00000000
-#define    NV20TCL_TX_SHADER_CULL_MODE_TX3_Q_LESS					0x00008000
-#define  NV20TCL_VERTEX_BEGIN_END							0x000017fc
-#define   NV20TCL_VERTEX_BEGIN_END_STOP							0x00000000
-#define   NV20TCL_VERTEX_BEGIN_END_POINTS						0x00000001
-#define   NV20TCL_VERTEX_BEGIN_END_LINES						0x00000002
-#define   NV20TCL_VERTEX_BEGIN_END_LINE_LOOP						0x00000003
-#define   NV20TCL_VERTEX_BEGIN_END_LINE_STRIP						0x00000004
-#define   NV20TCL_VERTEX_BEGIN_END_TRIANGLES						0x00000005
-#define   NV20TCL_VERTEX_BEGIN_END_TRIANGLE_STRIP					0x00000006
-#define   NV20TCL_VERTEX_BEGIN_END_TRIANGLE_FAN						0x00000007
-#define   NV20TCL_VERTEX_BEGIN_END_QUADS						0x00000008
-#define   NV20TCL_VERTEX_BEGIN_END_QUAD_STRIP						0x00000009
-#define   NV20TCL_VERTEX_BEGIN_END_POLYGON						0x0000000a
-#define  NV20TCL_VB_ELEMENT_U16								0x00001800
-#define   NV20TCL_VB_ELEMENT_U16_I0_SHIFT						0
-#define   NV20TCL_VB_ELEMENT_U16_I0_MASK						0x0000ffff
-#define   NV20TCL_VB_ELEMENT_U16_I1_SHIFT						16
-#define   NV20TCL_VB_ELEMENT_U16_I1_MASK						0xffff0000
-#define  NV20TCL_VB_ELEMENT_U32								0x00001808
-#define  NV20TCL_VB_VERTEX_BATCH							0x00001810
-#define   NV20TCL_VB_VERTEX_BATCH_OFFSET_SHIFT						0
-#define   NV20TCL_VB_VERTEX_BATCH_OFFSET_MASK						0x00ffffff
-#define   NV20TCL_VB_VERTEX_BATCH_COUNT_SHIFT						24
-#define   NV20TCL_VB_VERTEX_BATCH_COUNT_MASK						0xff000000
-#define  NV20TCL_VERTEX_DATA								0x00001818
-#define  NV20TCL_TX_SHADER_CONST_EYE_X							0x0000181c
-#define  NV20TCL_TX_SHADER_CONST_EYE_Y							0x00001820
-#define  NV20TCL_TX_SHADER_CONST_EYE_Z							0x00001824
-#define  NV20TCL_VTX_ATTR_4F_X(x)							(0x00001a00+((x)*16))
-#define  NV20TCL_VTX_ATTR_4F_X__SIZE							0x00000010
-#define  NV20TCL_VTX_ATTR_4F_Y(x)							(0x00001a04+((x)*16))
-#define  NV20TCL_VTX_ATTR_4F_Y__SIZE							0x00000010
-#define  NV20TCL_VTX_ATTR_4F_Z(x)							(0x00001a08+((x)*16))
-#define  NV20TCL_VTX_ATTR_4F_Z__SIZE							0x00000010
-#define  NV20TCL_VTX_ATTR_4F_W(x)							(0x00001a0c+((x)*16))
-#define  NV20TCL_VTX_ATTR_4F_W__SIZE							0x00000010
-#define  NV20TCL_TX_OFFSET(x)								(0x00001b00+((x)*64))
-#define  NV20TCL_TX_OFFSET__SIZE							0x00000004
-#define  NV20TCL_TX_FORMAT(x)								(0x00001b04+((x)*64))
-#define  NV20TCL_TX_FORMAT__SIZE							0x00000004
-#define   NV20TCL_TX_FORMAT_DMA0							(1 <<  0)
-#define   NV20TCL_TX_FORMAT_DMA1							(1 <<  1)
-#define   NV20TCL_TX_FORMAT_CUBIC							(1 <<  2)
-#define   NV20TCL_TX_FORMAT_NO_BORDER							(1 <<  3)
-#define   NV20TCL_TX_FORMAT_DIMS_SHIFT							4
-#define   NV20TCL_TX_FORMAT_DIMS_MASK							0x000000f0
-#define    NV20TCL_TX_FORMAT_DIMS_1D							0x00000010
-#define    NV20TCL_TX_FORMAT_DIMS_2D							0x00000020
-#define    NV20TCL_TX_FORMAT_DIMS_3D							0x00000030
-#define   NV20TCL_TX_FORMAT_FORMAT_SHIFT						8
-#define   NV20TCL_TX_FORMAT_FORMAT_MASK							0x0000ff00
-#define    NV20TCL_TX_FORMAT_FORMAT_L8							0x00000000
-#define    NV20TCL_TX_FORMAT_FORMAT_A8							0x00000100
-#define    NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5						0x00000200
-#define    NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4						0x00000400
-#define    NV20TCL_TX_FORMAT_FORMAT_R5G6B5						0x00000500
-#define    NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8						0x00000600
-#define    NV20TCL_TX_FORMAT_FORMAT_X8R8G8B8						0x00000700
-#define    NV20TCL_TX_FORMAT_FORMAT_INDEX8						0x00000b00
-#define    NV20TCL_TX_FORMAT_FORMAT_DXT1						0x00000c00
-#define    NV20TCL_TX_FORMAT_FORMAT_DXT3						0x00000e00
-#define    NV20TCL_TX_FORMAT_FORMAT_DXT5						0x00000f00
-#define    NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT					0x00001000
-#define    NV20TCL_TX_FORMAT_FORMAT_R5G6B5_RECT						0x00001100
-#define    NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT					0x00001200
-#define    NV20TCL_TX_FORMAT_FORMAT_L8_RECT						0x00001300
-#define    NV20TCL_TX_FORMAT_FORMAT_DSDT8_RECT						0x00001700
-#define    NV20TCL_TX_FORMAT_FORMAT_A8L8						0x00001a00
-#define    NV20TCL_TX_FORMAT_FORMAT_A8_RECT						0x00001b00
-#define    NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT					0x00001d00
-#define    NV20TCL_TX_FORMAT_FORMAT_R8G8B8_RECT						0x00001e00
-#define    NV20TCL_TX_FORMAT_FORMAT_A8L8_RECT						0x00002000
-#define    NV20TCL_TX_FORMAT_FORMAT_DSDT8						0x00002800
-#define    NV20TCL_TX_FORMAT_FORMAT_HILO16						0x00003300
-#define    NV20TCL_TX_FORMAT_FORMAT_HILO16_RECT						0x00003600
-#define    NV20TCL_TX_FORMAT_FORMAT_HILO8						0x00004400
-#define    NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8					0x00004500
-#define    NV20TCL_TX_FORMAT_FORMAT_HILO8_RECT						0x00004600
-#define    NV20TCL_TX_FORMAT_FORMAT_SIGNED_HILO8_RECT					0x00004700
-#define    NV20TCL_TX_FORMAT_FORMAT_A16							0x00003200
-#define    NV20TCL_TX_FORMAT_FORMAT_A16_RECT						0x00003500
-#define    NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA16_NV					0x00004a00
-#define    NV20TCL_TX_FORMAT_FORMAT_FLOAT_RGBA32_NV					0x00004b00
-#define    NV20TCL_TX_FORMAT_FORMAT_FLOAT_R32_NV					0x00004c00
-#define   NV20TCL_TX_FORMAT_MIPMAP							(1 << 19)
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_U_SHIFT						20
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_U_MASK						0x00f00000
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_V_SHIFT						24
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_V_MASK						0x0f000000
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_W_SHIFT						28
-#define   NV20TCL_TX_FORMAT_BASE_SIZE_W_MASK						0xf0000000
-#define  NV20TCL_TX_WRAP(x)								(0x00001b08+((x)*64))
-#define  NV20TCL_TX_WRAP__SIZE								0x00000004
-#define   NV20TCL_TX_WRAP_S_SHIFT							0
-#define   NV20TCL_TX_WRAP_S_MASK							0x000000ff
-#define    NV20TCL_TX_WRAP_S_REPEAT							0x00000001
-#define    NV20TCL_TX_WRAP_S_MIRRORED_REPEAT						0x00000002
-#define    NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE						0x00000003
-#define    NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER						0x00000004
-#define    NV20TCL_TX_WRAP_S_CLAMP							0x00000005
-#define   NV20TCL_TX_WRAP_T_SHIFT							8
-#define   NV20TCL_TX_WRAP_T_MASK							0x00000f00
-#define    NV20TCL_TX_WRAP_T_REPEAT							0x00000100
-#define    NV20TCL_TX_WRAP_T_MIRRORED_REPEAT						0x00000200
-#define    NV20TCL_TX_WRAP_T_CLAMP_TO_EDGE						0x00000300
-#define    NV20TCL_TX_WRAP_T_CLAMP_TO_BORDER						0x00000400
-#define    NV20TCL_TX_WRAP_T_CLAMP							0x00000500
-#define   NV20TCL_TX_WRAP_R_SHIFT							16
-#define   NV20TCL_TX_WRAP_R_MASK							0x000f0000
-#define    NV20TCL_TX_WRAP_R_REPEAT							0x00010000
-#define    NV20TCL_TX_WRAP_R_MIRRORED_REPEAT						0x00020000
-#define    NV20TCL_TX_WRAP_R_CLAMP_TO_EDGE						0x00030000
-#define    NV20TCL_TX_WRAP_R_CLAMP_TO_BORDER						0x00040000
-#define    NV20TCL_TX_WRAP_R_CLAMP							0x00050000
-#define  NV20TCL_TX_ENABLE(x)								(0x00001b0c+((x)*64))
-#define  NV20TCL_TX_ENABLE__SIZE							0x00000004
-#define   NV20TCL_TX_ENABLE_ANISO_SHIFT							4
-#define   NV20TCL_TX_ENABLE_ANISO_MASK							0x00000030
-#define    NV20TCL_TX_ENABLE_ANISO_NONE							0x00000000
-#define    NV20TCL_TX_ENABLE_ANISO_2X							0x00000010
-#define    NV20TCL_TX_ENABLE_ANISO_4X							0x00000020
-#define    NV20TCL_TX_ENABLE_ANISO_8X							0x00000030
-#define   NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT					14
-#define   NV20TCL_TX_ENABLE_MIPMAP_MAX_LOD_MASK						0x0003c000
-#define   NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT					26
-#define   NV20TCL_TX_ENABLE_MIPMAP_MIN_LOD_MASK						0x3c000000
-#define   NV20TCL_TX_ENABLE_ENABLE							(1 << 30)
-#define  NV20TCL_TX_NPOT_PITCH(x)							(0x00001b10+((x)*64))
-#define  NV20TCL_TX_NPOT_PITCH__SIZE							0x00000004
-#define   NV20TCL_TX_NPOT_PITCH_PITCH_SHIFT						16
-#define   NV20TCL_TX_NPOT_PITCH_PITCH_MASK						0xffff0000
-#define  NV20TCL_TX_FILTER(x)								(0x00001b14+((x)*64))
-#define  NV20TCL_TX_FILTER__SIZE							0x00000004
-#define   NV20TCL_TX_FILTER_LOD_BIAS_SHIFT						8
-#define   NV20TCL_TX_FILTER_LOD_BIAS_MASK						0x00000f00
-#define   NV20TCL_TX_FILTER_MINIFY_SHIFT						16
-#define   NV20TCL_TX_FILTER_MINIFY_MASK							0x000f0000
-#define    NV20TCL_TX_FILTER_MINIFY_NEAREST						0x00010000
-#define    NV20TCL_TX_FILTER_MINIFY_LINEAR						0x00020000
-#define    NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST				0x00030000
-#define    NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST				0x00040000
-#define    NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR				0x00050000
-#define    NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR				0x00060000
-#define   NV20TCL_TX_FILTER_MAGNIFY_SHIFT						24
-#define   NV20TCL_TX_FILTER_MAGNIFY_MASK						0x0f000000
-#define    NV20TCL_TX_FILTER_MAGNIFY_NEAREST						0x01000000
-#define    NV20TCL_TX_FILTER_MAGNIFY_LINEAR						0x02000000
-#define  NV20TCL_TX_NPOT_SIZE(x)							(0x00001b1c+((x)*64))
-#define  NV20TCL_TX_NPOT_SIZE__SIZE							0x00000004
-#define   NV20TCL_TX_NPOT_SIZE_H_SHIFT							0
-#define   NV20TCL_TX_NPOT_SIZE_H_MASK							0x0000ffff
-#define   NV20TCL_TX_NPOT_SIZE_W_SHIFT							16
-#define   NV20TCL_TX_NPOT_SIZE_W_MASK							0xffff0000
-#define  NV20TCL_TX_PALETTE_OFFSET(x)							(0x00001b20+((x)*64))
-#define  NV20TCL_TX_PALETTE_OFFSET__SIZE						0x00000004
-#define  NV20TCL_TX_BORDER_COLOR(x)							(0x00001b24+((x)*64))
-#define  NV20TCL_TX_BORDER_COLOR__SIZE							0x00000004
-#define   NV20TCL_TX_BORDER_COLOR_B_SHIFT						0
-#define   NV20TCL_TX_BORDER_COLOR_B_MASK						0x000000ff
-#define   NV20TCL_TX_BORDER_COLOR_G_SHIFT						8
-#define   NV20TCL_TX_BORDER_COLOR_G_MASK						0x0000ff00
-#define   NV20TCL_TX_BORDER_COLOR_R_SHIFT						16
-#define   NV20TCL_TX_BORDER_COLOR_R_MASK						0x00ff0000
-#define   NV20TCL_TX_BORDER_COLOR_A_SHIFT						24
-#define   NV20TCL_TX_BORDER_COLOR_A_MASK						0xff000000
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX00(x)						(0x00001b28+((x)*64))
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX00__SIZE					0x00000004
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX01(x)						(0x00001b2c+((x)*64))
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX01__SIZE					0x00000004
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX11(x)						(0x00001b30+((x)*64))
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX11__SIZE					0x00000004
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX10(x)						(0x00001b34+((x)*64))
-#define  NV20TCL_TX_SHADER_OFFSET_MATRIX10__SIZE					0x00000004
-#define  NV20TCL_DEPTH_UNK17D8								0x00001d78
-#define   NV20TCL_DEPTH_UNK17D8_CLAMP_SHIFT						4
-#define   NV20TCL_DEPTH_UNK17D8_CLAMP_MASK						0x000000f0
-#define  NV20TCL_MULTISAMPLE_CONTROL							0x00001d7c
-#define  NV20TCL_CLEAR_DEPTH_VALUE							0x00001d8c
-#define  NV20TCL_CLEAR_VALUE								0x00001d90
-#define  NV20TCL_CLEAR_BUFFERS								0x00001d94
-#define   NV20TCL_CLEAR_BUFFERS_COLOR_A							(1 <<  7)
-#define   NV20TCL_CLEAR_BUFFERS_COLOR_B							(1 <<  6)
-#define   NV20TCL_CLEAR_BUFFERS_COLOR_G							(1 <<  5)
-#define   NV20TCL_CLEAR_BUFFERS_COLOR_R							(1 <<  4)
-#define   NV20TCL_CLEAR_BUFFERS_STENCIL							(1 <<  1)
-#define   NV20TCL_CLEAR_BUFFERS_DEPTH							(1 <<  0)
-#define  NV20TCL_RC_COLOR0								0x00001e20
-#define   NV20TCL_RC_COLOR0_B_SHIFT							0
-#define   NV20TCL_RC_COLOR0_B_MASK							0x000000ff
-#define   NV20TCL_RC_COLOR0_G_SHIFT							8
-#define   NV20TCL_RC_COLOR0_G_MASK							0x0000ff00
-#define   NV20TCL_RC_COLOR0_R_SHIFT							16
-#define   NV20TCL_RC_COLOR0_R_MASK							0x00ff0000
-#define   NV20TCL_RC_COLOR0_A_SHIFT							24
-#define   NV20TCL_RC_COLOR0_A_MASK							0xff000000
-#define  NV20TCL_RC_COLOR1								0x00001e24
-#define   NV20TCL_RC_COLOR1_B_SHIFT							0
-#define   NV20TCL_RC_COLOR1_B_MASK							0x000000ff
-#define   NV20TCL_RC_COLOR1_G_SHIFT							8
-#define   NV20TCL_RC_COLOR1_G_MASK							0x0000ff00
-#define   NV20TCL_RC_COLOR1_R_SHIFT							16
-#define   NV20TCL_RC_COLOR1_R_MASK							0x00ff0000
-#define   NV20TCL_RC_COLOR1_A_SHIFT							24
-#define   NV20TCL_RC_COLOR1_A_MASK							0xff000000
-#define  NV20TCL_BACK_MATERIAL_SHININESS(x)						(0x00001e28+((x)*4))
-#define  NV20TCL_BACK_MATERIAL_SHININESS__SIZE						0x00000006
-#define  NV20TCL_RC_OUT_RGB(x)								(0x00001e40+((x)*4))
-#define  NV20TCL_RC_OUT_RGB__SIZE							0x00000008
-#define   NV20TCL_RC_OUT_RGB_CD_OUTPUT_SHIFT						0
-#define   NV20TCL_RC_OUT_RGB_CD_OUTPUT_MASK						0x0000000f
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0					0x00000001
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1					0x00000002
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_FOG						0x00000003
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR					0x00000004
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR					0x00000005
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE0					0x00000008
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE1					0x00000009
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0						0x0000000c
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE1						0x0000000d
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x0000000e
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F					0x0000000f
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE2					0x0000000a
-#define    NV20TCL_RC_OUT_RGB_CD_OUTPUT_TEXTURE3					0x0000000b
-#define   NV20TCL_RC_OUT_RGB_AB_OUTPUT_SHIFT						4
-#define   NV20TCL_RC_OUT_RGB_AB_OUTPUT_MASK						0x000000f0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0					0x00000010
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1					0x00000020
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_FOG						0x00000030
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR					0x00000040
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR					0x00000050
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE0					0x00000080
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE1					0x00000090
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0						0x000000c0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE1						0x000000d0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x000000e0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F					0x000000f0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE2					0x000000a0
-#define    NV20TCL_RC_OUT_RGB_AB_OUTPUT_TEXTURE3					0x000000b0
-#define   NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SHIFT						8
-#define   NV20TCL_RC_OUT_RGB_SUM_OUTPUT_MASK						0x00000f00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_ZERO						0x00000000
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0				0x00000100
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1				0x00000200
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_FOG						0x00000300
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR					0x00000400
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR				0x00000500
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0					0x00000800
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1					0x00000900
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0						0x00000c00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE1						0x00000d00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR			0x00000e00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F					0x00000f00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2					0x00000a00
-#define    NV20TCL_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3					0x00000b00
-#define   NV20TCL_RC_OUT_RGB_CD_DOT_PRODUCT						(1 << 12)
-#define   NV20TCL_RC_OUT_RGB_AB_DOT_PRODUCT						(1 << 13)
-#define   NV20TCL_RC_OUT_RGB_MUX_SUM							(1 << 14)
-#define   NV20TCL_RC_OUT_RGB_BIAS							(1 << 15)
-#define    NV20TCL_RC_OUT_RGB_BIAS_NONE							0x00000000
-#define    NV20TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF				0x00008000
-#define   NV20TCL_RC_OUT_RGB_SCALE_SHIFT						16
-#define   NV20TCL_RC_OUT_RGB_SCALE_MASK							0x00030000
-#define    NV20TCL_RC_OUT_RGB_SCALE_NONE						0x00000000
-#define    NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO					0x00010000
-#define    NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR					0x00020000
-#define    NV20TCL_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF					0x00030000
-#define  NV20TCL_RC_ENABLE								0x00001e60
-#define   NV20TCL_RC_ENABLE_NUM_COMBINERS_SHIFT						0
-#define   NV20TCL_RC_ENABLE_NUM_COMBINERS_MASK						0x0000000f
-#define  NV20TCL_TX_RCOMP								0x00001e6c
-#define   NV20TCL_TX_RCOMP_NEVER							0x00000000
-#define   NV20TCL_TX_RCOMP_GREATER							0x00000001
-#define   NV20TCL_TX_RCOMP_EQUAL							0x00000002
-#define   NV20TCL_TX_RCOMP_GEQUAL							0x00000003
-#define   NV20TCL_TX_RCOMP_LESS								0x00000004
-#define   NV20TCL_TX_RCOMP_NOTEQUAL							0x00000005
-#define   NV20TCL_TX_RCOMP_LEQUAL							0x00000006
-#define   NV20TCL_TX_RCOMP_ALWAYS							0x00000007
-#define  NV20TCL_TX_SHADER_OP								0x00001e70
-#define   NV20TCL_TX_SHADER_OP_TX0_SHIFT						0
-#define   NV20TCL_TX_SHADER_OP_TX0_MASK							0x0000001f
-#define    NV20TCL_TX_SHADER_OP_TX0_NONE						0x00000000
-#define    NV20TCL_TX_SHADER_OP_TX0_TEXTURE_2D						0x00000001
-#define    NV20TCL_TX_SHADER_OP_TX0_PASS_THROUGH					0x00000004
-#define    NV20TCL_TX_SHADER_OP_TX0_CULL_FRAGMENT					0x00000005
-#define    NV20TCL_TX_SHADER_OP_TX0_OFFSET_TEXTURE_2D					0x00000006
-#define    NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_TEXTURE_2D				0x00000009
-#define    NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT_DEPTH_REPLACE				0x0000000a
-#define    NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_AR_TEXTURE_2D				0x0000000f
-#define    NV20TCL_TX_SHADER_OP_TX0_DEPENDANT_GB_TEXTURE_2D				0x00000010
-#define    NV20TCL_TX_SHADER_OP_TX0_DOT_PRODUCT						0x00000011
-#define   NV20TCL_TX_SHADER_OP_TX1_SHIFT						5
-#define   NV20TCL_TX_SHADER_OP_TX1_MASK							0x000003e0
-#define    NV20TCL_TX_SHADER_OP_TX1_NONE						0x00000000
-#define    NV20TCL_TX_SHADER_OP_TX1_TEXTURE_2D						0x00000020
-#define    NV20TCL_TX_SHADER_OP_TX1_PASS_THROUGH					0x00000080
-#define    NV20TCL_TX_SHADER_OP_TX1_CULL_FRAGMENT					0x000000a0
-#define    NV20TCL_TX_SHADER_OP_TX1_OFFSET_TEXTURE_2D					0x000000c0
-#define    NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_TEXTURE_2D				0x00000120
-#define    NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT_DEPTH_REPLACE				0x00000140
-#define    NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_AR_TEXTURE_2D				0x000001e0
-#define    NV20TCL_TX_SHADER_OP_TX1_DEPENDANT_GB_TEXTURE_2D				0x00000200
-#define    NV20TCL_TX_SHADER_OP_TX1_DOT_PRODUCT						0x00000220
-#define   NV20TCL_TX_SHADER_OP_TX2_SHIFT						10
-#define   NV20TCL_TX_SHADER_OP_TX2_MASK							0x00007c00
-#define    NV20TCL_TX_SHADER_OP_TX2_NONE						0x00000000
-#define    NV20TCL_TX_SHADER_OP_TX2_TEXTURE_2D						0x00000400
-#define    NV20TCL_TX_SHADER_OP_TX2_PASS_THROUGH					0x00001000
-#define    NV20TCL_TX_SHADER_OP_TX2_CULL_FRAGMENT					0x00001400
-#define    NV20TCL_TX_SHADER_OP_TX2_OFFSET_TEXTURE_2D					0x00001800
-#define    NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_TEXTURE_2D				0x00002400
-#define    NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT_DEPTH_REPLACE				0x00002800
-#define    NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_AR_TEXTURE_2D				0x00003c00
-#define    NV20TCL_TX_SHADER_OP_TX2_DEPENDANT_GB_TEXTURE_2D				0x00004000
-#define    NV20TCL_TX_SHADER_OP_TX2_DOT_PRODUCT						0x00004400
-#define   NV20TCL_TX_SHADER_OP_TX3_SHIFT						15
-#define   NV20TCL_TX_SHADER_OP_TX3_MASK							0x000f8000
-#define    NV20TCL_TX_SHADER_OP_TX3_NONE						0x00000000
-#define    NV20TCL_TX_SHADER_OP_TX3_TEXTURE_2D						0x00008000
-#define    NV20TCL_TX_SHADER_OP_TX3_PASS_THROUGH					0x00020000
-#define    NV20TCL_TX_SHADER_OP_TX3_CULL_FRAGMENT					0x00028000
-#define    NV20TCL_TX_SHADER_OP_TX3_OFFSET_TEXTURE_2D					0x00030000
-#define    NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_TEXTURE_2D				0x00048000
-#define    NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT_DEPTH_REPLACE				0x00050000
-#define    NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_AR_TEXTURE_2D				0x00078000
-#define    NV20TCL_TX_SHADER_OP_TX3_DEPENDANT_GB_TEXTURE_2D				0x00080000
-#define    NV20TCL_TX_SHADER_OP_TX3_DOT_PRODUCT						0x00088000
-#define  NV20TCL_TX_SHADER_DOTMAPPING							0x00001e74
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX0_SHIFT					0
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX0_MASK						0x0000000f
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX1_SHIFT					4
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX1_MASK						0x000000f0
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX2_SHIFT					8
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX2_MASK						0x00000f00
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX3_SHIFT					12
-#define   NV20TCL_TX_SHADER_DOTMAPPING_TX3_MASK						0x0000f000
-#define  NV20TCL_TX_SHADER_PREVIOUS							0x00001e78
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX0_SHIFT						8
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX0_MASK						0x00000f00
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX1_SHIFT						12
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX1_MASK						0x0000f000
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX2_SHIFT						16
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX2_MASK						0x00030000
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX3_SHIFT						20
-#define   NV20TCL_TX_SHADER_PREVIOUS_TX3_MASK						0x00300000
-#define  NV20TCL_ENGINE									0x00001e94
-#define   NV20TCL_ENGINE_VP								(1 <<  1)
-#define   NV20TCL_ENGINE_FIXED								(1 <<  2)
-#define  NV20TCL_VP_UPLOAD_FROM_ID							0x00001e9c
-#define  NV20TCL_VP_START_FROM_ID							0x00001ea0
-#define  NV20TCL_VP_UPLOAD_CONST_ID							0x00001ea4
-
-
-#define NV25TCL										0x00000597
-
-#define  NV25TCL_DMA_IN_MEMORY4								0x0000019c
-#define  NV25TCL_DMA_IN_MEMORY5								0x000001a0
-#define  NV25TCL_DMA_IN_MEMORY8								0x000001ac
-#define  NV25TCL_DMA_IN_MEMORY9								0x000001b0
-#define  NV25TCL_HIERZ_PITCH								0x0000022c
-#define  NV25TCL_HIERZ_OFFSET								0x00000230
-
-#endif /* NOUVEAU_REG_H */
-
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index f80aaedb25..53a121420d 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -314,7 +314,7 @@ nouveau_context_make_current(__DRIcontext *dri_ctx, __DRIdrawable *dri_draw,
 GLboolean
 nouveau_context_unbind(__DRIcontext *dri_ctx)
 {
-	/* Unset current context and dispath table */
+	/* Unset current context and dispatch table */
 	_mesa_make_current(NULL, NULL, NULL);
 
 	return GL_TRUE;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 060c2c5bcc..2480b1ea50 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -603,11 +603,12 @@ nouveau_set_texbuffer(__DRIcontext *dri_ctx,
 	nouveau_update_renderbuffers(dri_ctx, draw);
 	nouveau_surface_ref(&to_nouveau_renderbuffer(rb)->surface, s);
 
+        s->format = get_texbuffer_format(rb, format);
+
 	/* Update the image fields. */
 	_mesa_init_teximage_fields(ctx, target, ti, s->width, s->height,
-				   1, 0, s->cpp);
+				   1, 0, s->cpp, s->format);
 	ti->RowStride = s->pitch / s->cpp;
-	ti->TexFormat = s->format = get_texbuffer_format(rb, format);
 
 	/* Try to validate it. */
 	if (!validate_teximage(ctx, t, 0, 0, 0, 0, s->width, s->height, 1))
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_util.h b/src/mesa/drivers/dri/nouveau/nouveau_util.h
index 8df8867d14..6d01934dad 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_util.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_util.h
@@ -164,6 +164,12 @@ get_viewport_translate(struct gl_context *ctx, float a[4])
 }
 
 static inline void
+OUT_RINGb(struct nouveau_channel *chan, GLboolean x)
+{
+	OUT_RING(chan, x ? 1 : 0);
+}
+
+static inline void
 OUT_RINGm(struct nouveau_channel *chan, float m[16])
 {
 	int i, j;
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
index 7a0eb9fc23..d8b331cca7 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
@@ -150,7 +150,6 @@ vbo_emit_attr(struct gl_context *ctx, const struct gl_client_array **arrays,
 			render->map[render->attr_count++] = attr;
 			render->vertex_size += 4 * info->imm_fields;
 		}
-
 	}
 }
 
diff --git a/src/mesa/drivers/dri/nouveau/nv01_2d.xml.h b/src/mesa/drivers/dri/nouveau/nv01_2d.xml.h
new file mode 100644
index 0000000000..3390da089b
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv01_2d.xml.h
@@ -0,0 +1,1343 @@
+#ifndef NV01_2D_XML
+#define NV01_2D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv01_2d.xml    (  33509 bytes, from 2010-11-13 23:32:57)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+
+#define NV01_CONTEXT_BETA1_DMA_NOTIFY				0x00000180
+
+#define NV01_CONTEXT_BETA1_BETA_1D31				0x00000300
+
+
+#define NV04_BETA_SOLID_DMA_NOTIFY				0x00000180
+
+#define NV04_BETA_SOLID_BETA_FACTOR				0x00000300
+
+
+#define NV01_CONTEXT_COLOR_KEY_DMA_NOTIFY			0x00000180
+
+#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT			0x00000300
+#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A16R5G6B5		0x00000001
+#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_X16A1R5G5B5		0x00000002
+#define NV01_CONTEXT_COLOR_KEY_COLOR_FORMAT_A8R8G8B8		0x00000003
+
+#define NV01_CONTEXT_COLOR_KEY_COLOR				0x00000304
+
+
+#define NV01_CONTEXT_PATTERN_DMA_NOTIFY				0x00000180
+
+#define NV01_CONTEXT_PATTERN_COLOR_FORMAT			0x00000300
+
+#define NV01_CONTEXT_PATTERN_MONOCHROME_FORMAT			0x00000304
+
+#define NV01_CONTEXT_PATTERN_SHAPE				0x00000308
+
+#define NV01_CONTEXT_PATTERN_COLOR(i0)			       (0x00000310 + 0x4*(i0))
+#define NV01_CONTEXT_PATTERN_COLOR__ESIZE			0x00000004
+#define NV01_CONTEXT_PATTERN_COLOR__LEN				0x00000002
+
+#define NV01_CONTEXT_PATTERN_PATTERN(i0)		       (0x00000318 + 0x4*(i0))
+#define NV01_CONTEXT_PATTERN_PATTERN__ESIZE			0x00000004
+#define NV01_CONTEXT_PATTERN_PATTERN__LEN			0x00000002
+
+
+#define NV01_CONTEXT_CLIP_RECTANGLE_DMA_NOTIFY			0x00000180
+
+#define NV01_CONTEXT_CLIP_RECTANGLE_POINT			0x00000300
+#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__MASK		0x0000ffff
+#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_X__SHIFT		0
+#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__MASK		0xffff0000
+#define NV01_CONTEXT_CLIP_RECTANGLE_POINT_Y__SHIFT		16
+
+#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE			0x00000304
+#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__MASK		0x0000ffff
+#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_W__SHIFT		0
+#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__MASK		0xffff0000
+#define NV01_CONTEXT_CLIP_RECTANGLE_SIZE_H__SHIFT		16
+
+
+#define NV04_CONTEXT_SURFACES_2D_DMA_NOTIFY			0x00000180
+
+#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE		0x00000184
+
+#define NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_DESTIN		0x00000188
+
+
+#define NV50_CONTEXT_SURFACES_2D_SRC_LINEAR			0x00000200
+
+#define NV50_CONTEXT_SURFACES_2D_SRC_TILE_MODE			0x00000204
+
+#define NV50_CONTEXT_SURFACES_2D_SRC_WIDTH			0x00000208
+
+#define NV50_CONTEXT_SURFACES_2D_SRC_HEIGHT			0x0000020c
+
+#define NV50_CONTEXT_SURFACES_2D_UNK0210			0x00000210
+
+#define NV50_CONTEXT_SURFACES_2D_UNK0214			0x00000214
+
+#define NV50_CONTEXT_SURFACES_2D_DST_LINEAR			0x00000218
+
+#define NV50_CONTEXT_SURFACES_2D_DST_TILE_MODE			0x0000021c
+
+#define NV50_CONTEXT_SURFACES_2D_DST_WIDTH			0x00000220
+
+#define NV50_CONTEXT_SURFACES_2D_DST_HEIGHT			0x00000224
+
+#define NV50_CONTEXT_SURFACES_2D_UNK0228			0x00000228
+
+#define NV50_CONTEXT_SURFACES_2D_UNK022C			0x0000022c
+
+#define NV50_CONTEXT_SURFACES_2D_OFFSET_SOURCE_HIGH		0x00000230
+
+#define NV50_CONTEXT_SURFACES_2D_OFFSET_DESTIN_HIGH		0x00000234
+
+#define NV04_CONTEXT_SURFACES_2D_FORMAT				0x00000300
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y8			0x00000001
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_Z1R5G5B5	0x00000002
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1R5G5B5_X1R5G5B5	0x00000003
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5			0x00000004
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y16			0x00000005
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_Z8R8G8B8	0x00000006
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X8R8G8B8_X8R8G8B8	0x00000007
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_Z1A7R8G8B8	0x00000008
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_X1A7R8G8B8_X1A7R8G8B8	0x00000009
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8		0x0000000a
+#define NV04_CONTEXT_SURFACES_2D_FORMAT_Y32			0x0000000b
+
+#define NV04_CONTEXT_SURFACES_2D_PITCH				0x00000304
+#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__MASK		0x0000ffff
+#define NV04_CONTEXT_SURFACES_2D_PITCH_SOURCE__SHIFT		0
+#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__MASK		0xffff0000
+#define NV04_CONTEXT_SURFACES_2D_PITCH_DESTIN__SHIFT		16
+
+#define NV04_CONTEXT_SURFACES_2D_OFFSET_SOURCE			0x00000308
+
+#define NV04_CONTEXT_SURFACES_2D_OFFSET_DESTIN			0x0000030c
+
+
+#define NV04_SWIZZLED_SURFACE_DMA_NOTIFY			0x00000180
+
+#define NV04_SWIZZLED_SURFACE_DMA_IMAGE				0x00000184
+
+#define NV04_SWIZZLED_SURFACE_FORMAT				0x00000300
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__MASK		0x000000ff
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR__SHIFT		0
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y8			0x00000001
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5	0x00000002
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1R5G5B5_X1R5G5B5	0x00000003
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_R5G6B5		0x00000004
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y16			0x00000005
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8	0x00000006
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X8R8G8B8_X8R8G8B8	0x00000007
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8	0x00000008
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8	0x00000009
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_A8R8G8B8		0x0000000a
+#define NV04_SWIZZLED_SURFACE_FORMAT_COLOR_Y32			0x0000000b
+#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__MASK		0x00ff0000
+#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U__SHIFT		16
+#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__MASK		0xff000000
+#define NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V__SHIFT		24
+
+#define NV04_SWIZZLED_SURFACE_OFFSET				0x00000304
+
+
+#define NV03_CONTEXT_ROP_DMA_NOTIFY				0x00000180
+
+#define NV03_CONTEXT_ROP_ROP					0x00000300
+
+
+#define NV04_IMAGE_PATTERN_DMA_NOTIFY				0x00000180
+
+#define NV04_IMAGE_PATTERN_COLOR_FORMAT				0x00000300
+#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A16R5G6B5		0x00000001
+#define NV04_IMAGE_PATTERN_COLOR_FORMAT_X16A1R5G5B5		0x00000002
+#define NV04_IMAGE_PATTERN_COLOR_FORMAT_A8R8G8B8		0x00000003
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT			0x00000304
+#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_CGA6		0x00000001
+#define NV04_IMAGE_PATTERN_MONOCHROME_FORMAT_LE			0x00000002
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE			0x00000308
+#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_8X8			0x00000000
+#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_64X1		0x00000001
+#define NV04_IMAGE_PATTERN_MONOCHROME_SHAPE_1X64		0x00000002
+
+#define NV04_IMAGE_PATTERN_PATTERN_SELECT			0x0000030c
+#define NV04_IMAGE_PATTERN_PATTERN_SELECT_MONO			0x00000001
+#define NV04_IMAGE_PATTERN_PATTERN_SELECT_COLOR			0x00000002
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR0			0x00000310
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_COLOR1			0x00000314
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN0			0x00000318
+
+#define NV04_IMAGE_PATTERN_MONOCHROME_PATTERN1			0x0000031c
+
+#define NV04_IMAGE_PATTERN_PATTERN_Y8(i0)		       (0x00000400 + 0x4*(i0))
+#define NV04_IMAGE_PATTERN_PATTERN_Y8__ESIZE			0x00000004
+#define NV04_IMAGE_PATTERN_PATTERN_Y8__LEN			0x00000010
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__MASK			0x000000ff
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y0__SHIFT			0
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__MASK			0x0000ff00
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y1__SHIFT			8
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__MASK			0x00ff0000
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y2__SHIFT			16
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__MASK			0xff000000
+#define NV04_IMAGE_PATTERN_PATTERN_Y8_Y3__SHIFT			24
+
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5(i0)		       (0x00000500 + 0x4*(i0))
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__ESIZE		0x00000004
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5__LEN			0x00000020
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__MASK		0x0000001f
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B0__SHIFT		0
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__MASK		0x000007e0
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G0__SHIFT		5
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__MASK		0x0000f800
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R0__SHIFT		11
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__MASK		0x001f0000
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_B1__SHIFT		16
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__MASK		0x07e00000
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_G1__SHIFT		21
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__MASK		0xf8000000
+#define NV04_IMAGE_PATTERN_PATTERN_R5G6B5_R1__SHIFT		27
+
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5(i0)		       (0x00000600 + 0x4*(i0))
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__ESIZE		0x00000004
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5__LEN		0x00000020
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__MASK		0x0000001f
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B0__SHIFT		0
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__MASK		0x000003e0
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G0__SHIFT		5
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__MASK		0x00007c00
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R0__SHIFT		10
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__MASK		0x001f0000
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_B1__SHIFT		16
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__MASK		0x03e00000
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_G1__SHIFT		21
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__MASK		0x7c000000
+#define NV04_IMAGE_PATTERN_PATTERN_X1R5G5B5_R1__SHIFT		26
+
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8(i0)		       (0x00000700 + 0x4*(i0))
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__ESIZE		0x00000004
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8__LEN		0x00000040
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__MASK		0x000000ff
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_B__SHIFT		0
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__MASK		0x0000ff00
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_G__SHIFT		8
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__MASK		0x00ff0000
+#define NV04_IMAGE_PATTERN_PATTERN_X8R8G8B8_R__SHIFT		16
+
+
+#define NV01_RENDER_SOLID_LINE_PATCH				0x0000010c
+
+#define NV01_RENDER_SOLID_LINE_DMA_NOTIFY			0x00000180
+
+#define NV01_RENDER_SOLID_LINE_CLIP_RECTANGLE			0x00000184
+
+#define NV01_RENDER_SOLID_LINE_PATTERN				0x00000188
+
+#define NV04_RENDER_SOLID_LINE_PATTERN				0x00000188
+
+#define NV01_RENDER_SOLID_LINE_ROP				0x0000018c
+
+#define NV01_RENDER_SOLID_LINE_BETA1				0x00000190
+
+#define NV01_RENDER_SOLID_LINE_SURFACE_DST			0x00000194
+
+
+#define NV04_RENDER_SOLID_LINE_BETA4				0x00000194
+
+#define NV04_RENDER_SOLID_LINE_SURFACE				0x00000198
+
+#define NV01_RENDER_SOLID_LINE_OPERATION			0x000002fc
+#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_AND		0x00000000
+#define NV01_RENDER_SOLID_LINE_OPERATION_ROP_AND		0x00000001
+#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_AND		0x00000002
+#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY		0x00000003
+#define NV01_RENDER_SOLID_LINE_OPERATION_SRCCOPY_PREMULT	0x00000004
+#define NV01_RENDER_SOLID_LINE_OPERATION_BLEND_PREMULT		0x00000005
+
+#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT			0x00000300
+#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A16R5G6B5		0x00000001
+#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_X16A1R5G5B5		0x00000002
+#define NV01_RENDER_SOLID_LINE_COLOR_FORMAT_A8R8G8B8		0x00000003
+
+#define NV01_RENDER_SOLID_LINE_COLOR				0x00000304
+
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0(i0)		       (0x00000400 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0__ESIZE		0x00000008
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0__LEN			0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__MASK		0x0000ffff
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0_X__SHIFT		0
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__MASK		0xffff0000
+#define NV01_RENDER_SOLID_LINE_LINE_POINT0_Y__SHIFT		16
+
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1(i0)		       (0x00000404 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1__ESIZE		0x00000008
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1__LEN			0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__MASK		0x0000ffff
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1_X__SHIFT		0
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__MASK		0xffff0000
+#define NV01_RENDER_SOLID_LINE_LINE_POINT1_Y__SHIFT		16
+
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X(i0)	       (0x00000480 + 0x10*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__ESIZE		0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_X__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y(i0)	       (0x00000484 + 0x10*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__ESIZE		0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT0_Y__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X(i0)	       (0x00000488 + 0x10*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__ESIZE		0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_X__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y(i0)	       (0x0000048c + 0x10*(i0))
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__ESIZE		0x00000010
+#define NV01_RENDER_SOLID_LINE_LINE32_POINT1_Y__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_POLYLINE(i0)		       (0x00000500 + 0x4*(i0))
+#define NV01_RENDER_SOLID_LINE_POLYLINE__ESIZE			0x00000004
+#define NV01_RENDER_SOLID_LINE_POLYLINE__LEN			0x00000020
+#define NV01_RENDER_SOLID_LINE_POLYLINE_X__MASK			0x0000ffff
+#define NV01_RENDER_SOLID_LINE_POLYLINE_X__SHIFT		0
+#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__MASK			0xffff0000
+#define NV01_RENDER_SOLID_LINE_POLYLINE_Y__SHIFT		16
+
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X(i0)	       (0x00000580 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_X__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y(i0)	       (0x00000584 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_LINE_POLYLINE32_POINT_Y__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR(i0)	       (0x00000600 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__ESIZE		0x00000008
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_COLOR__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT(i0)	       (0x00000604 + 0x8*(i0))
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__ESIZE		0x00000008
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT__LEN		0x00000010
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__MASK		0x0000ffff
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_X__SHIFT		0
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__MASK		0xffff0000
+#define NV01_RENDER_SOLID_LINE_CPOLYLINE_POINT_Y__SHIFT		16
+
+
+#define NV01_RENDER_SOLID_TRIANGLE_PATCH			0x0000010c
+
+#define NV01_RENDER_SOLID_TRIANGLE_DMA_NOTIFY			0x00000180
+
+#define NV01_RENDER_SOLID_TRIANGLE_CLIP_RECTANGLE		0x00000184
+
+#define NV01_RENDER_SOLID_TRIANGLE_PATTERN			0x00000188
+
+#define NV04_RENDER_SOLID_TRIANGLE_PATTERN			0x00000188
+
+#define NV01_RENDER_SOLID_TRIANGLE_ROP				0x0000018c
+
+#define NV01_RENDER_SOLID_TRIANGLE_BETA1			0x00000190
+
+#define NV01_RENDER_SOLID_TRIANGLE_SURFACE_DST			0x00000194
+
+
+#define NV04_RENDER_SOLID_TRIANGLE_BETA4			0x00000194
+
+#define NV04_RENDER_SOLID_TRIANGLE_SURFACE			0x00000198
+
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION			0x000002fc
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_AND	0x00000000
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_ROP_AND		0x00000001
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_AND		0x00000002
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY		0x00000003
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_SRCCOPY_PREMULT	0x00000004
+#define NV01_RENDER_SOLID_TRIANGLE_OPERATION_BLEND_PREMULT	0x00000005
+
+#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT			0x00000300
+#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A16R5G6B5	0x00000001
+#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_X16A1R5G5B5	0x00000002
+#define NV01_RENDER_SOLID_TRIANGLE_COLOR_FORMAT_A8R8G8B8	0x00000003
+
+#define NV01_RENDER_SOLID_TRIANGLE_COLOR			0x00000304
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0		0x00000310
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT0_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1		0x00000314
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT1_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2		0x00000318
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE_POINT2_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_X		0x00000320
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT0_Y		0x00000324
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_X		0x00000328
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT1_Y		0x0000032c
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_X		0x00000330
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIANGLE32_POINT2_Y		0x00000334
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH(i0)		       (0x00000400 + 0x4*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__ESIZE		0x00000004
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH__LEN			0x00000020
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__MASK		0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_X__SHIFT		0
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__MASK		0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH_Y__SHIFT		16
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X(i0)       (0x00000480 + 0x8*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_X__LEN	0x00000010
+
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y(i0)       (0x00000484 + 0x8*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_TRIMESH32_POINT_Y__LEN	0x00000010
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR(i0)	       (0x00000500 + 0x10*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__ESIZE	0x00000010
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_COLOR__LEN		0x00000008
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0(i0)	       (0x00000504 + 0x10*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__ESIZE	0x00000010
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0__LEN	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT0_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1(i0)	       (0x00000508 + 0x10*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__ESIZE	0x00000010
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1__LEN	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT1_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2(i0)	       (0x0000050c + 0x10*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__ESIZE	0x00000010
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2__LEN	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIANGLE_POINT2_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR(i0)	       (0x00000580 + 0x8*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_COLOR__LEN		0x00000010
+
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT(i0)	       (0x00000584 + 0x8*(i0))
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT__LEN		0x00000010
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_X__SHIFT	0
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_TRIANGLE_CTRIMESH_POINT_Y__SHIFT	16
+
+
+#define NV01_RENDER_SOLID_RECTANGLE_PATCH			0x0000010c
+
+#define NV01_RENDER_SOLID_RECTANGLE_DMA_NOTIFY			0x00000180
+
+#define NV01_RENDER_SOLID_RECTANGLE_CLIP_RECTANGLE		0x00000184
+
+#define NV01_RENDER_SOLID_RECTANGLE_PATTERN			0x00000188
+
+#define NV04_RENDER_SOLID_RECTANGLE_PATTERN			0x00000188
+
+#define NV01_RENDER_SOLID_RECTANGLE_ROP				0x0000018c
+
+#define NV01_RENDER_SOLID_RECTANGLE_BETA1			0x00000190
+
+#define NV01_RENDER_SOLID_RECTANGLE_SURFACE_DST			0x00000194
+
+
+#define NV04_RENDER_SOLID_RECTANGLE_BETA4			0x00000194
+
+#define NV04_RENDER_SOLID_RECTANGLE_SURFACE			0x00000198
+
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION			0x000002fc
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_AND	0x00000000
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_ROP_AND		0x00000001
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_AND		0x00000002
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY		0x00000003
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_SRCCOPY_PREMULT	0x00000004
+#define NV01_RENDER_SOLID_RECTANGLE_OPERATION_BLEND_PREMULT	0x00000005
+
+#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT		0x00000300
+#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A16R5G6B5	0x00000001
+#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_X16A1R5G5B5	0x00000002
+#define NV01_RENDER_SOLID_RECTANGLE_COLOR_FORMAT_A8R8G8B8	0x00000003
+
+#define NV01_RENDER_SOLID_RECTANGLE_COLOR			0x00000304
+
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT(i0)	       (0x00000400 + 0x8*(i0))
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT__LEN	0x00000010
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_X__SHIFT	0
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__MASK	0xffff0000
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_POINT_Y__SHIFT	16
+
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE(i0)	       (0x00000404 + 0x8*(i0))
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__ESIZE	0x00000008
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE__LEN		0x00000010
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__MASK	0x0000ffff
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_W__SHIFT	0
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__MASK	0xffff0000
+#define NV01_RENDER_SOLID_RECTANGLE_RECTANGLE_SIZE_H__SHIFT	16
+
+
+#define NV01_IMAGE_BLIT_PATCH					0x0000010c
+
+
+#define NV11_IMAGE_BLIT_WAIT_FOR_IDLE				0x00000108
+
+#define NV11_IMAGE_BLIT_FLIP_SET_READ				0x00000120
+
+#define NV11_IMAGE_BLIT_FLIP_SET_WRITE				0x00000124
+
+#define NV11_IMAGE_BLIT_FLIP_MAX				0x00000128
+
+#define NV11_IMAGE_BLIT_FLIP_INCR_WRITE				0x0000012c
+
+#define NV11_IMAGE_BLIT_FLIP_WAIT				0x00000130
+
+#define NV11_IMAGE_BLIT_FLIP_CRTC_INCR_READ			0x00000134
+
+#define NV01_IMAGE_BLIT_DMA_NOTIFY				0x00000180
+
+#define NV01_IMAGE_BLIT_COLOR_KEY				0x00000184
+
+#define NV04_IMAGE_BLIT_COLOR_KEY				0x00000184
+
+#define NV01_IMAGE_BLIT_CLIP_RECTANGLE				0x00000188
+
+#define NV01_IMAGE_BLIT_PATTERN					0x0000018c
+
+#define NV04_IMAGE_BLIT_PATTERN					0x0000018c
+
+#define NV01_IMAGE_BLIT_ROP					0x00000190
+
+#define NV01_IMAGE_BLIT_BETA1					0x00000194
+
+
+#define NV01_IMAGE_BLIT_SURFACE_SRC				0x00000198
+
+#define NV01_IMAGE_BLIT_SURFACE_DST				0x0000019c
+
+
+#define NV04_IMAGE_BLIT_BETA4					0x00000198
+
+#define NV04_IMAGE_BLIT_SURFACES				0x0000019c
+
+#define NV01_IMAGE_BLIT_OPERATION				0x000002fc
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_AND			0x00000000
+#define NV01_IMAGE_BLIT_OPERATION_ROP_AND			0x00000001
+#define NV01_IMAGE_BLIT_OPERATION_BLEND_AND			0x00000002
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY			0x00000003
+#define NV01_IMAGE_BLIT_OPERATION_SRCCOPY_PREMULT		0x00000004
+#define NV01_IMAGE_BLIT_OPERATION_BLEND_PREMULT			0x00000005
+
+#define NV01_IMAGE_BLIT_POINT_IN				0x00000300
+#define NV01_IMAGE_BLIT_POINT_IN_X__MASK			0x0000ffff
+#define NV01_IMAGE_BLIT_POINT_IN_X__SHIFT			0
+#define NV01_IMAGE_BLIT_POINT_IN_Y__MASK			0xffff0000
+#define NV01_IMAGE_BLIT_POINT_IN_Y__SHIFT			16
+
+#define NV01_IMAGE_BLIT_POINT_OUT				0x00000304
+#define NV01_IMAGE_BLIT_POINT_OUT_X__MASK			0x0000ffff
+#define NV01_IMAGE_BLIT_POINT_OUT_X__SHIFT			0
+#define NV01_IMAGE_BLIT_POINT_OUT_Y__MASK			0xffff0000
+#define NV01_IMAGE_BLIT_POINT_OUT_Y__SHIFT			16
+
+#define NV01_IMAGE_BLIT_SIZE					0x00000308
+#define NV01_IMAGE_BLIT_SIZE_W__MASK				0x0000ffff
+#define NV01_IMAGE_BLIT_SIZE_W__SHIFT				0
+#define NV01_IMAGE_BLIT_SIZE_H__MASK				0xffff0000
+#define NV01_IMAGE_BLIT_SIZE_H__SHIFT				16
+
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_PATCH			0x0000010c
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_NOTIFY			0x00000180
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_DMA_LUT			0x00000184
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_KEY			0x00000188
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_CLIP_RECTANGLE		0x0000018c
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_PATTERN			0x00000190
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_ROP				0x00000194
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_BETA1			0x00000198
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_BETA4			0x0000019c
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_SURFACE			0x000001a0
+
+#define NV05_INDEXED_IMAGE_FROM_CPU_SURFACE			0x000001a0
+
+#define NV05_INDEXED_IMAGE_FROM_CPU_COLOR_CONVERSION		0x000003e0
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_OPERATION			0x000003e4
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR_FORMAT		0x000003e8
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_INDEX_FORMAT		0x000003ec
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_LUT_OFFSET			0x000003f0
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_POINT			0x000003f4
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_OUT			0x000003f8
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_SIZE_IN			0x000003fc
+
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR(i0)		       (0x00000400 + 0x4*(i0))
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__ESIZE		0x00000004
+#define NV04_INDEXED_IMAGE_FROM_CPU_COLOR__LEN			0x00000700
+
+
+#define NV10_IMAGE_FROM_CPU_WAIT_FOR_IDLE			0x00000108
+
+#define NV01_IMAGE_FROM_CPU_PATCH				0x0000010c
+
+#define NV01_IMAGE_FROM_CPU_DMA_NOTIFY				0x00000180
+
+#define NV01_IMAGE_FROM_CPU_COLOR_KEY				0x00000184
+
+#define NV04_IMAGE_FROM_CPU_COLOR_KEY				0x00000184
+
+#define NV01_IMAGE_FROM_CPU_CLIP_RECTANGLE			0x00000188
+
+#define NV01_IMAGE_FROM_CPU_PATTERN				0x0000018c
+
+#define NV04_IMAGE_FROM_CPU_PATTERN				0x0000018c
+
+#define NV01_IMAGE_FROM_CPU_ROP					0x00000190
+
+#define NV01_IMAGE_FROM_CPU_BETA1				0x00000194
+
+
+#define NV01_IMAGE_FROM_CPU_SURFACE_DST				0x00000198
+
+
+#define NV04_IMAGE_FROM_CPU_BETA4				0x00000198
+
+#define NV04_IMAGE_FROM_CPU_SURFACE				0x0000019c
+
+#define NV05_IMAGE_FROM_CPU_COLOR_CONVERSION			0x000002f8
+
+#define NV01_IMAGE_FROM_CPU_OPERATION				0x000002fc
+#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_AND		0x00000000
+#define NV01_IMAGE_FROM_CPU_OPERATION_ROP_AND			0x00000001
+#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_AND			0x00000002
+#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY			0x00000003
+#define NV01_IMAGE_FROM_CPU_OPERATION_SRCCOPY_PREMULT		0x00000004
+#define NV01_IMAGE_FROM_CPU_OPERATION_BLEND_PREMULT		0x00000005
+
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT			0x00000300
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_R5G6G5			0x00000001
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A1R5G5B5		0x00000002
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X1R5G5B5		0x00000003
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_A8R8G8B8		0x00000004
+#define NV01_IMAGE_FROM_CPU_COLOR_FORMAT_X8R8G8B8		0x00000005
+
+#define NV01_IMAGE_FROM_CPU_POINT				0x00000304
+#define NV01_IMAGE_FROM_CPU_POINT_X__MASK			0x0000ffff
+#define NV01_IMAGE_FROM_CPU_POINT_X__SHIFT			0
+#define NV01_IMAGE_FROM_CPU_POINT_Y__MASK			0xffff0000
+#define NV01_IMAGE_FROM_CPU_POINT_Y__SHIFT			16
+
+#define NV01_IMAGE_FROM_CPU_SIZE_OUT				0x00000308
+#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__MASK			0x0000ffff
+#define NV01_IMAGE_FROM_CPU_SIZE_OUT_W__SHIFT			0
+#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__MASK			0xffff0000
+#define NV01_IMAGE_FROM_CPU_SIZE_OUT_H__SHIFT			16
+
+#define NV01_IMAGE_FROM_CPU_SIZE_IN				0x0000030c
+#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__MASK			0x0000ffff
+#define NV01_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT			0
+#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__MASK			0xffff0000
+#define NV01_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT			16
+
+#define NV01_IMAGE_FROM_CPU_COLOR(i0)			       (0x00000400 + 0x4*(i0))
+#define NV01_IMAGE_FROM_CPU_COLOR__ESIZE			0x00000004
+#define NV01_IMAGE_FROM_CPU_COLOR__LEN				0x00000020
+
+#define NV04_IMAGE_FROM_CPU_COLOR(i0)			       (0x00000400 + 0x4*(i0))
+#define NV04_IMAGE_FROM_CPU_COLOR__ESIZE			0x00000004
+#define NV04_IMAGE_FROM_CPU_COLOR__LEN				0x00000700
+
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_PATCH			0x0000010c
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_DMA_NOTIFY		0x00000180
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY			0x00000184
+
+#define NV04_STRETCHED_IMAGE_FROM_CPU_COLOR_KEY			0x00000184
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_PATTERN			0x00000188
+
+#define NV04_STRETCHED_IMAGE_FROM_CPU_PATTERN			0x00000188
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_ROP			0x0000018c
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_BETA1			0x00000190
+
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SURFACE_DST		0x00000194
+
+
+#define NV04_STRETCHED_IMAGE_FROM_CPU_BETA4			0x00000194
+
+#define NV04_STRETCHED_IMAGE_FROM_CPU_SURFACE			0x00000198
+
+#define NV05_STRETCHED_IMAGE_FROM_CPU_COLOR_CONVERSION		0x000002f8
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_OPERATION			0x000002fc
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR_FORMAT		0x00000300
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN			0x00000304
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__MASK		0x0000ffff
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_W__SHIFT		0
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__MASK		0xffff0000
+#define NV03_STRETCHED_IMAGE_FROM_CPU_SIZE_IN_H__SHIFT		16
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_DX_DU			0x00000308
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_DY_DV			0x0000030c
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT		0x00000310
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__MASK	0x0000ffff
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_X__SHIFT	0
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__MASK	0xffff0000
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_POINT_Y__SHIFT	16
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE			0x00000314
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__MASK		0x0000ffff
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_W__SHIFT	0
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__MASK		0xffff0000
+#define NV03_STRETCHED_IMAGE_FROM_CPU_CLIP_SIZE_H__SHIFT	16
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4			0x00000318
+#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__MASK		0x0000ffff
+#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_X__SHIFT	0
+#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__MASK		0xffff0000
+#define NV03_STRETCHED_IMAGE_FROM_CPU_POINT12D4_Y__SHIFT	16
+
+#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR(i0)		       (0x00000400 + 0x4*(i0))
+#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__ESIZE		0x00000004
+#define NV03_STRETCHED_IMAGE_FROM_CPU_COLOR__LEN		0x00000700
+
+
+#define NV10_SCALED_IMAGE_FROM_MEMORY_WAIT_FOR_IDLE		0x00000108
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_NOTIFY		0x00000180
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE			0x00000184
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_PATTERN			0x00000188
+
+#define NV04_SCALED_IMAGE_FROM_MEMORY_PATTERN			0x00000188
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_ROP			0x0000018c
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_BETA1			0x00000190
+
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SURFACE_DST		0x00000194
+
+
+#define NV04_SCALED_IMAGE_FROM_MEMORY_BETA4			0x00000194
+
+#define NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE			0x00000198
+
+#define NV05_SCALED_IMAGE_FROM_MEMORY_SURFACE			0x00000198
+
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION		0x000002fc
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_DITHER	0x00000000
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE	0x00000001
+#define NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_SUBTR_TRUNCATE	0x00000002
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT		0x00000300
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5	0x00000001
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X1R5G5B5	0x00000002
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8	0x00000003
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8	0x00000004
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_V8YB8U8YA8	0x00000005
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_YB8V8YA8U8	0x00000006
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5	0x00000007
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8		0x00000008
+#define NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_AY8		0x00000009
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION			0x00000304
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_AND	0x00000000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_ROP_AND		0x00000001
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_AND	0x00000002
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY		0x00000003
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY_PREMULT	0x00000004
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_BLEND_PREMULT	0x00000005
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT		0x00000308
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__MASK	0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_X__SHIFT	0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__MASK	0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y__SHIFT	16
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE			0x0000030c
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__MASK		0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_W__SHIFT	0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__MASK		0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H__SHIFT	16
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT			0x00000310
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__MASK		0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_X__SHIFT	0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__MASK		0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y__SHIFT	16
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE			0x00000314
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__MASK		0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_W__SHIFT		0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__MASK		0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H__SHIFT		16
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DU_DX			0x00000318
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_DV_DY			0x0000031c
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE			0x00000400
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__MASK		0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_W__SHIFT		0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__MASK		0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H__SHIFT		16
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT			0x00000404
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__MASK	0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_PITCH__SHIFT	0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__MASK	0x00ff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN__SHIFT	16
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER	0x00010000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CORNER	0x00020000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__MASK	0xff000000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER__SHIFT	24
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE	0x00000000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_BILINEAR	0x01000000
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_OFFSET			0x00000408
+
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT			0x0000040c
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__MASK		0x0000ffff
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_U__SHIFT		0
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__MASK		0xffff0000
+#define NV03_SCALED_IMAGE_FROM_MEMORY_POINT_V__SHIFT		16
+
+
+#define NV50_SCALED_IMAGE_FROM_MEMORY_OFFSET_HIGH		0x00000410
+
+#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_LINEAR		0x00000414
+
+#define NV50_SCALED_IMAGE_FROM_MEMORY_SRC_TILE_MODE		0x00000418
+
+
+#define NV03_GDI_RECTANGLE_TEXT_DMA_NOTIFY			0x00000180
+
+#define NV03_GDI_RECTANGLE_TEXT_PATTERN				0x00000184
+
+#define NV03_GDI_RECTANGLE_TEXT_ROP				0x00000188
+
+#define NV03_GDI_RECTANGLE_TEXT_BETA1				0x0000019c
+
+#define NV03_GDI_RECTANGLE_TEXT_SURFACE_DST			0x00000190
+
+#define NV03_GDI_RECTANGLE_TEXT_OPERATION			0x000002fc
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR_FORMAT			0x00000300
+
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT		0x00000304
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR1_A			0x000003fc
+
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT	0x00000400
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK	0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT	0
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK	0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT	16
+
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE	0x00000404
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK	0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT	0
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK	0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT	16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B			0x000007f4
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_L__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT0_B_T__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B			0x000007f8
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_R__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_POINT1_B_B__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR1_B			0x000007fc
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0	0x00000800
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK	0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT	0
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK	0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT	16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1	0x00000804
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK	0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT	0
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK	0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT	16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0			0x00000bec
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1			0x00000bf0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR1_C			0x00000bf4
+
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_C				0x00000bf8
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK			0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT			0
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK			0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT			16
+
+#define NV03_GDI_RECTANGLE_TEXT_POINT_C				0x00000bfc
+#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__MASK			0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK			0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0)	       (0x00000c00 + 0x4*(i0))
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE	0x00000004
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN	0x00000020
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0			0x00000fe8
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_L__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT0_T__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1			0x00000fec
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_R__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_D_POINT1_B__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR1_D			0x00000ff0
+
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D			0x00000ff4
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_W__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_D_H__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D			0x00000ff8
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_W__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_D_H__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_POINT_D				0x00000ffc
+#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__MASK			0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_POINT_D_X__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__MASK			0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_POINT_D_Y__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D(i0)	       (0x00001000 + 0x4*(i0))
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__ESIZE	0x00000004
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_D__LEN	0x00000020
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0			0x000013e4
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1			0x000013e8
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR0_E			0x000013ec
+
+#define NV03_GDI_RECTANGLE_TEXT_COLOR1_E			0x000013f0
+
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E			0x000013f4
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E			0x000013f8
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK		0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK		0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_POINT_E				0x000013fc
+#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__MASK			0x0000ffff
+#define NV03_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT		0
+#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK			0xffff0000
+#define NV03_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT		16
+
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0)       (0x00001400 + 0x4*(i0))
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE	0x00000004
+#define NV03_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN	0x00000020
+
+
+#define NV04_GDI_RECTANGLE_TEXT_PATCH				0x0000010c
+
+#define NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY			0x00000180
+
+#define NV04_GDI_RECTANGLE_TEXT_DMA_FONTS			0x00000184
+
+#define NV04_GDI_RECTANGLE_TEXT_PATTERN				0x00000188
+
+#define NV04_GDI_RECTANGLE_TEXT_ROP				0x0000018c
+
+#define NV04_GDI_RECTANGLE_TEXT_BETA1				0x00000190
+
+#define NV04_GDI_RECTANGLE_TEXT_BETA4				0x00000194
+
+#define NV04_GDI_RECTANGLE_TEXT_SURFACE				0x00000198
+
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION			0x000002fc
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_AND		0x00000000
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_ROP_AND		0x00000001
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_AND		0x00000002
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY		0x00000003
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY_PREMULT	0x00000004
+#define NV04_GDI_RECTANGLE_TEXT_OPERATION_BLEND_PREMULT		0x00000005
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT			0x00000300
+#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5		0x00000001
+#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_X16A1R5G5B5	0x00000002
+#define NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8		0x00000003
+
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT		0x00000304
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_CGA6		0x00000001
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE		0x00000002
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_A			0x000003fc
+
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(i0)  (0x00000400 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT__LEN	0x00000020
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__MASK	0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_Y__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__MASK	0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT_X__SHIFT	16
+
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE(i0)   (0x00000404 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE__LEN	0x00000020
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__MASK	0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_H__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__MASK	0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_SIZE_W__SHIFT	16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0			0x000005f4
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_L__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT0_T__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1			0x000005f8
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_R__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_B_POINT1_B__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_B			0x000005fc
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0(i0)  (0x00000600 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0__LEN	0x00000020
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__MASK	0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_L__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__MASK	0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_0_T__SHIFT	16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1(i0)  (0x00000604 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1__LEN	0x00000020
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__MASK	0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_R__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__MASK	0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIPPED_RECTANGLE_POINT_1_B__SHIFT	16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0			0x000007ec
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_L__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT0_T__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1			0x000007f0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_R__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_C_POINT1_B__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_C			0x000007f4
+
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_C				0x000007f8
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__MASK			0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_W__SHIFT			0
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__MASK			0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_C_H__SHIFT			16
+
+#define NV04_GDI_RECTANGLE_TEXT_POINT_C				0x000007fc
+#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__MASK			0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_POINT_C_X__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__MASK			0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_POINT_C_Y__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C(i0)	       (0x00000800 + 0x4*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__ESIZE	0x00000004
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR1_C__LEN	0x00000080
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0			0x00000be4
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_L__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT0_T__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1			0x00000be8
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_R__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_E_POINT1_B__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR0_E			0x00000bec
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_E			0x00000bf0
+
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E			0x00000bf4
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_W__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_IN_E_H__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E			0x00000bf8
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_W__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_SIZE_OUT_E_H__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_POINT_E				0x00000bfc
+#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__MASK			0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_POINT_E_X__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__MASK			0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_POINT_E_Y__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E(i0)       (0x00000c00 + 0x4*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__ESIZE	0x00000004
+#define NV04_GDI_RECTANGLE_TEXT_MONOCHROME_COLOR01_E__LEN	0x00000080
+
+#define NV04_GDI_RECTANGLE_TEXT_FONT_F				0x00000ff0
+#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__MASK		0x0fffffff
+#define NV04_GDI_RECTANGLE_TEXT_FONT_F_OFFSET__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__MASK		0xf0000000
+#define NV04_GDI_RECTANGLE_TEXT_FONT_F_PITCH__SHIFT		28
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0			0x00000ff4
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_L__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT0_T__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1			0x00000ff8
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_R__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_F_POINT1_B__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_F			0x00000ffc
+
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F(i0)	       (0x00001000 + 0x4*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__ESIZE	0x00000004
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F__LEN		0x00000100
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__MASK	0x000000ff
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_INDEX__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__MASK	0x000fff00
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_X__SHIFT	8
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__MASK	0xfff00000
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_F_Y__SHIFT	20
+
+#define NV04_GDI_RECTANGLE_TEXT_FONT_G				0x000017f0
+#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__MASK		0x0fffffff
+#define NV04_GDI_RECTANGLE_TEXT_FONT_G_OFFSET__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__MASK		0xf0000000
+#define NV04_GDI_RECTANGLE_TEXT_FONT_G_PITCH__SHIFT		28
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0			0x000017f4
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_L__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT0_T__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1			0x000017f8
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__MASK		0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_R__SHIFT		0
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__MASK		0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CLIP_G_POINT1_B__SHIFT		16
+
+#define NV04_GDI_RECTANGLE_TEXT_COLOR1_G			0x000017fc
+
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT(i0)   (0x00001800 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT__LEN	0x00000100
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__MASK	0x0000ffff
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_X__SHIFT	0
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__MASK	0xffff0000
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_POINT_Y__SHIFT	16
+
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX(i0)   (0x00001804 + 0x8*(i0))
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__ESIZE	0x00000008
+#define NV04_GDI_RECTANGLE_TEXT_CHARACTER_COLOR1_G_INDEX__LEN	0x00000100
+
+
+#define NV10_TEXTURE_FROM_CPU_WAIT_FOR_IDLE			0x00000108
+
+#define NV10_TEXTURE_FROM_CPU_DMA_NOTIFY			0x00000180
+
+#define NV10_TEXTURE_FROM_CPU_SURFACE				0x00000184
+
+#define NV10_TEXTURE_FROM_CPU_COLOR_FORMAT			0x00000300
+
+#define NV10_TEXTURE_FROM_CPU_POINT				0x00000304
+#define NV10_TEXTURE_FROM_CPU_POINT_X__MASK			0x0000ffff
+#define NV10_TEXTURE_FROM_CPU_POINT_X__SHIFT			0
+#define NV10_TEXTURE_FROM_CPU_POINT_Y__MASK			0xffff0000
+#define NV10_TEXTURE_FROM_CPU_POINT_Y__SHIFT			16
+
+#define NV10_TEXTURE_FROM_CPU_SIZE				0x00000308
+#define NV10_TEXTURE_FROM_CPU_SIZE_W__MASK			0x0000ffff
+#define NV10_TEXTURE_FROM_CPU_SIZE_W__SHIFT			0
+#define NV10_TEXTURE_FROM_CPU_SIZE_H__MASK			0xffff0000
+#define NV10_TEXTURE_FROM_CPU_SIZE_H__SHIFT			16
+
+#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL			0x0000030c
+#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__MASK		0x0000ffff
+#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_X__SHIFT		0
+#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__MASK		0xffff0000
+#define NV10_TEXTURE_FROM_CPU_CLIP_HORIZONTAL_W__SHIFT		16
+
+#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL			0x00000310
+#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__MASK		0x0000ffff
+#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_Y__SHIFT		0
+#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__MASK		0xffff0000
+#define NV10_TEXTURE_FROM_CPU_CLIP_VERTICAL_H__SHIFT		16
+
+#define NV10_TEXTURE_FROM_CPU_COLOR(i0)			       (0x00000400 + 0x4*(i0))
+#define NV10_TEXTURE_FROM_CPU_COLOR__ESIZE			0x00000004
+#define NV10_TEXTURE_FROM_CPU_COLOR__LEN			0x00000700
+
+
+#endif /* NV01_2D_XML */
diff --git a/src/mesa/drivers/dri/nouveau/nv04_3d.xml.h b/src/mesa/drivers/dri/nouveau/nv04_3d.xml.h
new file mode 100644
index 0000000000..d4fb680a36
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv04_3d.xml.h
@@ -0,0 +1,738 @@
+#ifndef NV04_3D_XML
+#define NV04_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv04_3d.xml    (  17839 bytes, from 2010-11-15 02:23:48)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+- nv_3ddefs.xml  (  16394 bytes, from 2010-11-01 00:28:46)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+
+#define NV04_CONTEXT_SURFACES_3D_DMA_NOTIFY			0x00000180
+
+#define NV04_CONTEXT_SURFACES_3D_DMA_COLOR			0x00000184
+
+#define NV04_CONTEXT_SURFACES_3D_DMA_ZETA			0x00000188
+
+#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL		0x000002f8
+#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X__MASK	0x0000ffff
+#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_X__SHIFT	0
+#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W__MASK	0xffff0000
+#define NV04_CONTEXT_SURFACES_3D_CLIP_HORIZONTAL_W__SHIFT	16
+
+#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL			0x000002fc
+#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y__MASK		0x0000ffff
+#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_Y__SHIFT		0
+#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H__MASK		0xffff0000
+#define NV04_CONTEXT_SURFACES_3D_CLIP_VERTICAL_H__SHIFT		16
+
+#define NV04_CONTEXT_SURFACES_3D_FORMAT				0x00000300
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR__MASK		0x000000ff
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR__SHIFT		0
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_Z1R5G5B5	0x00000001
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1R5G5B5_X1R5G5B5	0x00000002
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5		0x00000003
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_Z8R8G8B8	0x00000004
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8	0x00000005
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_Z1A7R8G8B8	0x00000006
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X1A7R8G8B8_X1A7R8G8B8	0x00000007
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8		0x00000008
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE__MASK		0x0000ff00
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE__SHIFT		8
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_PITCH		0x00000100
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_TYPE_SWIZZLE		0x00000200
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U__MASK	0x00ff0000
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_U__SHIFT	16
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V__MASK	0xff000000
+#define NV04_CONTEXT_SURFACES_3D_FORMAT_BASE_SIZE_V__SHIFT	24
+
+#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE			0x00000304
+#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W__MASK		0x0000ffff
+#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_W__SHIFT		0
+#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H__MASK		0xffff0000
+#define NV04_CONTEXT_SURFACES_3D_CLIP_SIZE_H__SHIFT		16
+
+#define NV04_CONTEXT_SURFACES_3D_PITCH				0x00000308
+#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR__MASK		0x0000ffff
+#define NV04_CONTEXT_SURFACES_3D_PITCH_COLOR__SHIFT		0
+#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA__MASK		0xffff0000
+#define NV04_CONTEXT_SURFACES_3D_PITCH_ZETA__SHIFT		16
+
+#define NV04_CONTEXT_SURFACES_3D_OFFSET_COLOR			0x0000030c
+
+#define NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA			0x00000310
+
+
+#define NV04_TEXTURED_TRIANGLE_DMA_NOTIFY			0x00000180
+
+#define NV04_TEXTURED_TRIANGLE_DMA_A				0x00000184
+
+#define NV04_TEXTURED_TRIANGLE_DMA_B				0x00000188
+
+#define NV04_TEXTURED_TRIANGLE_SURFACES				0x0000018c
+
+#define NV04_TEXTURED_TRIANGLE_COLORKEY				0x00000300
+
+#define NV04_TEXTURED_TRIANGLE_OFFSET				0x00000304
+
+#define NV04_TEXTURED_TRIANGLE_FORMAT				0x00000308
+#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_A			0x00000001
+#define NV04_TEXTURED_TRIANGLE_FORMAT_DMA_B			0x00000002
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_KEY_ENABLE		0x00000004
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH__MASK		0x00000030
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH__SHIFT		4
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER		0x00000010
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER		0x00000020
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH__MASK		0x000000c0
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH__SHIFT		6
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER		0x00000040
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER		0x00000080
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR__MASK		0x00000f00
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR__SHIFT		8
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_Y8			0x00000100
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A1R5G5B5		0x00000200
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X1R5G5B5		0x00000300
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A4R4G4B4		0x00000400
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_R5G6B5		0x00000500
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_A8R8G8B8		0x00000600
+#define NV04_TEXTURED_TRIANGLE_FORMAT_COLOR_X8R8G8B8		0x00000700
+#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS__MASK	0x0000f000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_MIPMAP_LEVELS__SHIFT	12
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U__MASK		0x000f0000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_U__SHIFT	16
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V__MASK		0x00f00000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_BASE_SIZE_V__SHIFT	20
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU__MASK		0x07000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU__SHIFT		24
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_REPEAT		0x01000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT	0x02000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE	0x03000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER	0x04000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPU			0x08000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV__MASK		0x70000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV__SHIFT		28
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_REPEAT		0x10000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT	0x20000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE	0x30000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER	0x40000000
+#define NV04_TEXTURED_TRIANGLE_FORMAT_WRAPV			0x80000000
+
+#define NV04_TEXTURED_TRIANGLE_FILTER				0x0000030c
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X__MASK	0x000000ff
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_X__SHIFT	0
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y__MASK	0x00007f00
+#define NV04_TEXTURED_TRIANGLE_FILTER_KERNEL_SIZE_Y__SHIFT	8
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE	0x00008000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS__MASK	0x00ff0000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MIPMAP_LODBIAS__SHIFT	16
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY__MASK		0x07000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY__SHIFT		24
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST		0x01000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR		0x02000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST	0x03000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST	0x04000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR	0x05000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR	0x06000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE	0x08000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY__MASK		0x70000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY__SHIFT		28
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_NEAREST		0x10000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_MAGNIFY_LINEAR		0x20000000
+#define NV04_TEXTURED_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE	0x80000000
+
+#define NV04_TEXTURED_TRIANGLE_BLEND				0x00000310
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP__MASK		0x0000000f
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP__SHIFT		0
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_DECAL		0x00000001
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MODULATE	0x00000002
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_DECALALPHA	0x00000003
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MODULATEALPHA	0x00000004
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_DECALMASK	0x00000005
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_MODULATEMASK	0x00000006
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_COPY		0x00000007
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_MAP_ADD		0x00000008
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT__MASK		0x00000030
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT__SHIFT		4
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_LSB		0x00000010
+#define NV04_TEXTURED_TRIANGLE_BLEND_MASK_BIT_MSB		0x00000020
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE__MASK		0x000000c0
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE__SHIFT		6
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_FLAT		0x00000040
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_GOURAUD		0x00000080
+#define NV04_TEXTURED_TRIANGLE_BLEND_SHADE_MODE_PHONG		0x000000c0
+#define NV04_TEXTURED_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE	0x00000100
+#define NV04_TEXTURED_TRIANGLE_BLEND_SPECULAR_ENABLE		0x00001000
+#define NV04_TEXTURED_TRIANGLE_BLEND_FOG_ENABLE			0x00010000
+#define NV04_TEXTURED_TRIANGLE_BLEND_BLEND_ENABLE		0x00100000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC__MASK			0x0f000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC__SHIFT			24
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ZERO			0x01000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ONE			0x02000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SRC_COLOR		0x03000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ONE_MINUS_SRC_COLOR	0x04000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SRC_ALPHA		0x05000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ONE_MINUS_SRC_ALPHA	0x06000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_DST_ALPHA		0x07000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ONE_MINUS_DST_ALPHA	0x08000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_DST_COLOR		0x09000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_ONE_MINUS_DST_COLOR	0x0a000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_SRC_SRC_ALPHA_SATURATE	0x0b000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST__MASK			0xf0000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST__SHIFT			28
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ZERO			0x10000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ONE			0x20000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SRC_COLOR		0x30000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ONE_MINUS_SRC_COLOR	0x40000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SRC_ALPHA		0x50000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ONE_MINUS_SRC_ALPHA	0x60000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_DST_ALPHA		0x70000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ONE_MINUS_DST_ALPHA	0x80000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_DST_COLOR		0x90000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_ONE_MINUS_DST_COLOR	0xa0000000
+#define NV04_TEXTURED_TRIANGLE_BLEND_DST_SRC_ALPHA_SATURATE	0xb0000000
+
+#define NV04_TEXTURED_TRIANGLE_CONTROL				0x00000314
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF__MASK		0x000000ff
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_REF__SHIFT		0
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC__MASK		0x00000f00
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC__SHIFT	8
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_NEVER		0x00000100
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_LESS		0x00000200
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_EQUAL		0x00000300
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_LEQUAL	0x00000400
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_GREATER	0x00000500
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_NOTEQUAL	0x00000600
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_GEQUAL	0x00000700
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_ALWAYS	0x00000800
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ALPHA_ENABLE		0x00001000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN__MASK		0x00002000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN__SHIFT		13
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN_CENTER		0x00000000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN_CORNER		0x00002000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_ENABLE			0x00004000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC__MASK		0x000f0000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC__SHIFT		16
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_NEVER		0x00010000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_LESS		0x00020000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_EQUAL		0x00030000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_LEQUAL		0x00040000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_GREATER		0x00050000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_NOTEQUAL		0x00060000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_GEQUAL		0x00070000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FUNC_ALWAYS		0x00080000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE__MASK		0x00300000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE__SHIFT		20
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_BOTH		0x00000000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_NONE		0x00100000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CW		0x00200000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_CULL_MODE_CCW		0x00300000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_DITHER_ENABLE		0x00400000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_PERSPECTIVE_ENABLE	0x00800000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_WRITE			0x01000000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT__MASK		0xc0000000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT__SHIFT		30
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_FIXED		0x40000000
+#define NV04_TEXTURED_TRIANGLE_CONTROL_Z_FORMAT_FLOAT		0x80000000
+
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR				0x00000318
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B__MASK			0x000000ff
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_B__SHIFT		0
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G__MASK			0x0000ff00
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_G__SHIFT		8
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R__MASK			0x00ff0000
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_R__SHIFT		16
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A__MASK			0xff000000
+#define NV04_TEXTURED_TRIANGLE_FOGCOLOR_A__SHIFT		24
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX(i0)		       (0x00000400 + 0x20*(i0))
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX__ESIZE			0x00000020
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX__LEN			0x00000010
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SX(i0)		       (0x00000400 + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SY(i0)		       (0x00000404 + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SZ(i0)		       (0x00000408 + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_RHW(i0)		       (0x0000040c + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR(i0)	       (0x00000410 + 0x20*(i0))
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B__MASK		0x000000ff
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_B__SHIFT		0
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G__MASK		0x0000ff00
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_G__SHIFT		8
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R__MASK		0x00ff0000
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_R__SHIFT		16
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A__MASK		0xff000000
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_COLOR_A__SHIFT		24
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR(i0)	       (0x00000414 + 0x20*(i0))
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B__MASK	0x000000ff
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_B__SHIFT	0
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G__MASK	0x0000ff00
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_G__SHIFT	8
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R__MASK	0x00ff0000
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_R__SHIFT	16
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG__MASK	0xff000000
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_SPECULAR_FOG__SHIFT	24
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TU(i0)		       (0x00000418 + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_TLVERTEX_TV(i0)		       (0x0000041c + 0x20*(i0))
+
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE(i0)	       (0x00000600 + 0x4*(i0))
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__ESIZE		0x00000004
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE__LEN		0x00000040
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0__MASK		0x0000000f
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I0__SHIFT		0
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1__MASK		0x000000f0
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I1__SHIFT		4
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2__MASK		0x00000f00
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I2__SHIFT		8
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3__MASK		0x0000f000
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I3__SHIFT		12
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4__MASK		0x000f0000
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I4__SHIFT		16
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5__MASK		0x00f00000
+#define NV04_TEXTURED_TRIANGLE_DRAWPRIMITIVE_I5__SHIFT		20
+
+
+#define NV04_MULTITEX_TRIANGLE_DMA_NOTIFY			0x00000180
+
+#define NV04_MULTITEX_TRIANGLE_DMA_A				0x00000184
+
+#define NV04_MULTITEX_TRIANGLE_DMA_B				0x00000188
+
+#define NV04_MULTITEX_TRIANGLE_SURFACES				0x0000018c
+
+#define NV04_MULTITEX_TRIANGLE_OFFSET(i0)		       (0x00000308 + 0x4*(i0))
+#define NV04_MULTITEX_TRIANGLE_OFFSET__ESIZE			0x00000004
+#define NV04_MULTITEX_TRIANGLE_OFFSET__LEN			0x00000002
+
+#define NV04_MULTITEX_TRIANGLE_FORMAT(i0)		       (0x00000310 + 0x4*(i0))
+#define NV04_MULTITEX_TRIANGLE_FORMAT__ESIZE			0x00000004
+#define NV04_MULTITEX_TRIANGLE_FORMAT__LEN			0x00000002
+#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_A			0x00000001
+#define NV04_MULTITEX_TRIANGLE_FORMAT_DMA_B			0x00000002
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH__MASK		0x00000030
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH__SHIFT		4
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_CENTER		0x00000010
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_ZOH_CORNER		0x00000020
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH__MASK		0x000000c0
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH__SHIFT		6
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_CENTER		0x00000040
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ORIGIN_FOH_CORNER		0x00000080
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR__MASK		0x00000f00
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR__SHIFT		8
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_Y8			0x00000100
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_A1R5G5B5		0x00000200
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_X1R5G5B5		0x00000300
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_A4R4G4B4		0x00000400
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_R5G6B5		0x00000500
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_A8R8G8B8		0x00000600
+#define NV04_MULTITEX_TRIANGLE_FORMAT_COLOR_X8R8G8B8		0x00000700
+#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS__MASK	0x0000f000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_MIPMAP_LEVELS__SHIFT	12
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U__MASK		0x000f0000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_U__SHIFT	16
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V__MASK		0x00f00000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_BASE_SIZE_V__SHIFT	20
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU__MASK		0x07000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU__SHIFT		24
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_REPEAT		0x01000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_MIRRORED_REPEAT	0x02000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_EDGE	0x03000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSU_CLAMP_TO_BORDER	0x04000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPU			0x08000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV__MASK		0x70000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV__SHIFT		28
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_REPEAT		0x10000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_MIRRORED_REPEAT	0x20000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_EDGE	0x30000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_ADDRESSV_CLAMP_TO_BORDER	0x40000000
+#define NV04_MULTITEX_TRIANGLE_FORMAT_WRAPV			0x80000000
+
+#define NV04_MULTITEX_TRIANGLE_FILTER(i0)		       (0x00000318 + 0x4*(i0))
+#define NV04_MULTITEX_TRIANGLE_FILTER__ESIZE			0x00000004
+#define NV04_MULTITEX_TRIANGLE_FILTER__LEN			0x00000002
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X__MASK	0x000000ff
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_X__SHIFT	0
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y__MASK	0x00007f00
+#define NV04_MULTITEX_TRIANGLE_FILTER_KERNEL_SIZE_Y__SHIFT	8
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_DITHER_ENABLE	0x00008000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS__MASK	0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MIPMAP_LODBIAS__SHIFT	16
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY__MASK		0x07000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY__SHIFT		24
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_NEAREST		0x01000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_LINEAR		0x02000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST	0x03000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST	0x04000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR	0x05000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR	0x06000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MINIFY_ENABLE	0x08000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY__MASK		0x70000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY__SHIFT		28
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_NEAREST		0x10000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_MAGNIFY_LINEAR		0x20000000
+#define NV04_MULTITEX_TRIANGLE_FILTER_ANISOTROPIC_MAGNIFY_ENABLE	0x80000000
+
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA(i0)	       (0x00000320 + 0xc*(i0))
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__ESIZE		0x0000000c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA__LEN		0x00000002
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE0		0x00000001
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0__MASK	0x000000fc
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0__SHIFT	2
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_ZERO	0x00000004
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_CONSTANT	0x00000008
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PRIMARY_COLOR	0x0000000c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_PREVIOUS	0x00000010
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE0	0x00000014
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURE1	0x00000018
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT0_TEXTURELOD	0x0000001c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE1		0x00000100
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1__MASK	0x0000fc00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1__SHIFT	10
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_ZERO	0x00000400
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_CONSTANT	0x00000800
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PRIMARY_COLOR	0x00000c00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_PREVIOUS	0x00001000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE0	0x00001400
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURE1	0x00001800
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT1_TEXTURELOD	0x00001c00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE2		0x00010000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2__MASK	0x00fc0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2__SHIFT	18
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_ZERO	0x00040000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_CONSTANT	0x00080000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PRIMARY_COLOR	0x000c0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_PREVIOUS	0x00100000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE0	0x00140000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURE1	0x00180000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT2_TEXTURELOD	0x001c0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_INVERSE3		0x01000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3__MASK	0x1c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3__SHIFT	26
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_ZERO	0x04000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_CONSTANT	0x08000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PRIMARY_COLOR	0x0c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_PREVIOUS	0x10000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE0	0x14000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURE1	0x18000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_ARGUMENT3_TEXTURELOD	0x1c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP__MASK		0xe0000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP__SHIFT		29
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_IDENTITY	0x20000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE2		0x40000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_SCALE4		0x60000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS		0x80000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_ALPHA_MAP_BIAS_SCALE2	0xe0000000
+
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR(i0)	       (0x00000324 + 0xc*(i0))
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__ESIZE		0x0000000c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR__LEN		0x00000002
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE0		0x00000001
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA0		0x00000002
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0__MASK	0x000000fc
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0__SHIFT	2
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_ZERO	0x00000004
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_CONSTANT	0x00000008
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PRIMARY_COLOR	0x0000000c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_PREVIOUS	0x00000010
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE0	0x00000014
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURE1	0x00000018
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_TEXTURELOD	0x0000001c
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE1		0x00000100
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA1		0x00000200
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1__MASK	0x0000fc00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1__SHIFT	10
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_ZERO	0x00000400
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_CONSTANT	0x00000800
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PRIMARY_COLOR	0x00000c00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_PREVIOUS	0x00001000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE0	0x00001400
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURE1	0x00001800
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT1_TEXTURELOD	0x00001c00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE2		0x00010000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA2		0x00020000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2__MASK	0x00fc0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2__SHIFT	18
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_ZERO	0x00040000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_CONSTANT	0x00080000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PRIMARY_COLOR	0x000c0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_PREVIOUS	0x00100000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE0	0x00140000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURE1	0x00180000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT2_TEXTURELOD	0x001c0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_INVERSE3		0x01000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ALPHA3		0x02000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3__MASK	0x1c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3__SHIFT	26
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_ZERO	0x04000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_CONSTANT	0x08000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PRIMARY_COLOR	0x0c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_PREVIOUS	0x10000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE0	0x14000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURE1	0x18000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT3_TEXTURELOD	0x1c000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP__MASK		0xe0000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP__SHIFT		29
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_IDENTITY	0x20000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE2		0x40000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_SCALE4		0x60000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS		0x80000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_MAP_BIAS_SCALE2	0xe0000000
+
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR			0x00000334
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B__MASK		0x000000ff
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_B__SHIFT		0
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G__MASK		0x0000ff00
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_G__SHIFT		8
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R__MASK		0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_R__SHIFT		16
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A__MASK		0xff000000
+#define NV04_MULTITEX_TRIANGLE_COMBINE_FACTOR_A__SHIFT		24
+
+#define NV04_MULTITEX_TRIANGLE_BLEND				0x00000338
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT__MASK		0x00000030
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT__SHIFT		4
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_LSB		0x00000010
+#define NV04_MULTITEX_TRIANGLE_BLEND_MASK_BIT_MSB		0x00000020
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE__MASK		0x000000c0
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE__SHIFT		6
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_FLAT		0x00000040
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_GOURAUD		0x00000080
+#define NV04_MULTITEX_TRIANGLE_BLEND_SHADE_MODE_PHONG		0x000000c0
+#define NV04_MULTITEX_TRIANGLE_BLEND_TEXTURE_PERSPECTIVE_ENABLE	0x00000100
+#define NV04_MULTITEX_TRIANGLE_BLEND_SPECULAR_ENABLE		0x00001000
+#define NV04_MULTITEX_TRIANGLE_BLEND_FOG_ENABLE			0x00010000
+#define NV04_MULTITEX_TRIANGLE_BLEND_BLEND_ENABLE		0x00100000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC__MASK			0x0f000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC__SHIFT			24
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ZERO			0x01000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ONE			0x02000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SRC_COLOR		0x03000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ONE_MINUS_SRC_COLOR	0x04000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SRC_ALPHA		0x05000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ONE_MINUS_SRC_ALPHA	0x06000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_DST_ALPHA		0x07000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ONE_MINUS_DST_ALPHA	0x08000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_DST_COLOR		0x09000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_ONE_MINUS_DST_COLOR	0x0a000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_SRC_SRC_ALPHA_SATURATE	0x0b000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST__MASK			0xf0000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST__SHIFT			28
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ZERO			0x10000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ONE			0x20000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SRC_COLOR		0x30000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ONE_MINUS_SRC_COLOR	0x40000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SRC_ALPHA		0x50000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ONE_MINUS_SRC_ALPHA	0x60000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_DST_ALPHA		0x70000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ONE_MINUS_DST_ALPHA	0x80000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_DST_COLOR		0x90000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_ONE_MINUS_DST_COLOR	0xa0000000
+#define NV04_MULTITEX_TRIANGLE_BLEND_DST_SRC_ALPHA_SATURATE	0xb0000000
+
+#define NV04_MULTITEX_TRIANGLE_CONTROL0				0x0000033c
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF__MASK		0x000000ff
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_REF__SHIFT	0
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC__MASK	0x00000f00
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC__SHIFT	8
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_NEVER	0x00000100
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_LESS		0x00000200
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_EQUAL	0x00000300
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_LEQUAL	0x00000400
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_GREATER	0x00000500
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_NOTEQUAL	0x00000600
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_GEQUAL	0x00000700
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_FUNC_ALWAYS	0x00000800
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_ENABLE		0x00001000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN__MASK		0x00002000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN__SHIFT		13
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN_CENTER		0x00000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN_CORNER		0x00002000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_ENABLE		0x00004000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC__MASK		0x000f0000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC__SHIFT		16
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_NEVER		0x00010000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_LESS		0x00020000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_EQUAL		0x00030000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_LEQUAL		0x00040000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_GREATER		0x00050000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_NOTEQUAL		0x00060000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_GEQUAL		0x00070000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FUNC_ALWAYS		0x00080000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE__MASK		0x00300000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE__SHIFT	20
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_BOTH		0x00000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_NONE		0x00100000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CW		0x00200000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_CULL_MODE_CCW		0x00300000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_DITHER_ENABLE		0x00400000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_PERSPECTIVE_ENABLE	0x00800000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_WRITE			0x01000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_STENCIL_WRITE		0x02000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_ALPHA_WRITE		0x04000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_RED_WRITE		0x08000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_GREEN_WRITE		0x10000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_BLUE_WRITE		0x20000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT__MASK		0xc0000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT__SHIFT		30
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_FIXED		0x40000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL0_Z_FORMAT_FLOAT		0x80000000
+
+#define NV04_MULTITEX_TRIANGLE_CONTROL1				0x00000340
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_ENABLE		0x00000001
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC__MASK	0x000000f0
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_FUNC__SHIFT	4
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF__MASK	0x0000ff00
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_REF__SHIFT	8
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ__MASK	0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_READ__SHIFT	16
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE__MASK	0xff000000
+#define NV04_MULTITEX_TRIANGLE_CONTROL1_STENCIL_MASK_WRITE__SHIFT	24
+
+#define NV04_MULTITEX_TRIANGLE_CONTROL2				0x00000344
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL__MASK	0x0000000f
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_FAIL__SHIFT	0
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL__MASK	0x000000f0
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZFAIL__SHIFT	4
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS__MASK	0x00000f00
+#define NV04_MULTITEX_TRIANGLE_CONTROL2_STENCIL_OP_ZPASS__SHIFT	8
+
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR				0x00000348
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B__MASK			0x000000ff
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_B__SHIFT		0
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G__MASK			0x0000ff00
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_G__SHIFT		8
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R__MASK			0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_R__SHIFT		16
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A__MASK			0xff000000
+#define NV04_MULTITEX_TRIANGLE_FOGCOLOR_A__SHIFT		24
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX(i0)		       (0x00000400 + 0x28*(i0))
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX__ESIZE		0x00000028
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX__LEN			0x00000008
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SX(i0)	       (0x00000400 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SY(i0)	       (0x00000404 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SZ(i0)	       (0x00000408 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_RHW(i0)	       (0x0000040c + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR(i0)	       (0x00000410 + 0x28*(i0))
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B__MASK		0x000000ff
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_B__SHIFT	0
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G__MASK		0x0000ff00
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_G__SHIFT	8
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R__MASK		0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_R__SHIFT	16
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A__MASK		0xff000000
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_COLOR_A__SHIFT	24
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR(i0)	       (0x00000414 + 0x28*(i0))
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B__MASK	0x000000ff
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_B__SHIFT	0
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G__MASK	0x0000ff00
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_G__SHIFT	8
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R__MASK	0x00ff0000
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_R__SHIFT	16
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG__MASK	0xff000000
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_SPECULAR_FOG__SHIFT	24
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU0(i0)	       (0x00000418 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV0(i0)	       (0x0000041c + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TU1(i0)	       (0x00000420 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_TLMTVERTEX_TV1(i0)	       (0x00000424 + 0x28*(i0))
+
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE(i0)	       (0x00000540 + 0x4*(i0))
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__ESIZE		0x00000004
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE__LEN		0x00000030
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0__MASK		0x0000000f
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I0__SHIFT		0
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1__MASK		0x000000f0
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I1__SHIFT		4
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2__MASK		0x00000f00
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I2__SHIFT		8
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3__MASK		0x0000f000
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I3__SHIFT		12
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4__MASK		0x000f0000
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I4__SHIFT		16
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5__MASK		0x00f00000
+#define NV04_MULTITEX_TRIANGLE_DRAWPRIMITIVE_I5__SHIFT		20
+
+
+#endif /* NV04_3D_XML */
diff --git a/src/mesa/drivers/dri/nouveau/nv04_context.c b/src/mesa/drivers/dri/nouveau/nv04_context.c
index 8683343b39..3140af56fd 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_context.c
@@ -28,7 +28,7 @@
 #include "nouveau_context.h"
 #include "nouveau_fbo.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 static GLboolean
diff --git a/src/mesa/drivers/dri/nouveau/nv04_context.h b/src/mesa/drivers/dri/nouveau/nv04_context.h
index 45e70d2bc3..960a6550dc 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_context.h
+++ b/src/mesa/drivers/dri/nouveau/nv04_context.h
@@ -28,6 +28,7 @@
 #define __NV04_CONTEXT_H__
 
 #include "nouveau_context.h"
+#include "nv_object.xml.h"
 
 struct nv04_context {
 	struct nouveau_context base;
diff --git a/src/mesa/drivers/dri/nouveau/nv04_render.c b/src/mesa/drivers/dri/nouveau/nv04_render.c
index 47bad24f9d..ad45093edd 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_render.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_render.c
@@ -27,7 +27,7 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 #include "tnl/tnl.h"
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
index a3e343660f..854571d07e 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_fb.c
@@ -28,7 +28,7 @@
 #include "nouveau_context.h"
 #include "nouveau_fbo.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 static inline unsigned
@@ -36,11 +36,11 @@ get_rt_format(gl_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
-		return 0x05;
+		return NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_X8R8G8B8_X8R8G8B8;
 	case MESA_FORMAT_ARGB8888:
-		return 0x08;
+		return NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_A8R8G8B8;
 	case MESA_FORMAT_RGB565:
-		return 0x03;
+		return NV04_CONTEXT_SURFACES_3D_FORMAT_COLOR_R5G6B5;
 	default:
 		assert(0);
 	}
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
index 658b23a4d9..21478de262 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_frag.c
@@ -27,12 +27,13 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 #define COMBINER_SHIFT(in)						\
-	(NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT##in##_SHIFT	\
-	 - NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_SHIFT)
+	(NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT##in##__SHIFT	\
+	 - NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0__SHIFT)
 #define COMBINER_SOURCE(reg)					\
 	NV04_MULTITEX_TRIANGLE_COMBINE_COLOR_ARGUMENT0_##reg
 #define COMBINER_INVERT					\
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
index a114f44b22..98f2f98f1d 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_raster.c
@@ -27,7 +27,8 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 static unsigned
@@ -142,7 +143,7 @@ nv04_emit_control(struct gl_context *ctx, int emit)
 		int cull_mode = ctx->Polygon.CullFaceMode;
 		int front_face = ctx->Polygon.FrontFace;
 		uint32_t ctrl0 = 1 << 30 |
-			NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN;
+			NV04_MULTITEX_TRIANGLE_CONTROL0_ORIGIN_CORNER;
 		uint32_t ctrl1 = 0, ctrl2 = 0;
 
 		/* Color mask. */
@@ -210,7 +211,7 @@ nv04_emit_control(struct gl_context *ctx, int emit)
 		int cull_mode = ctx->Polygon.CullFaceMode;
 		int front_face = ctx->Polygon.FrontFace;
 		uint32_t ctrl = 1 << 30 |
-			NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN;
+			NV04_TEXTURED_TRIANGLE_CONTROL_ORIGIN_CORNER;
 
 		/* Dithering. */
 		if (ctx->Color.DitherFlag)
diff --git a/src/mesa/drivers/dri/nouveau/nv04_state_tex.c b/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
index 1fe47a30e4..5ed8b14755 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_state_tex.c
@@ -29,7 +29,8 @@
 #include "nouveau_texture.h"
 #include "nouveau_util.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv04_3d.xml.h"
 #include "nv04_driver.h"
 
 static uint32_t
diff --git a/src/mesa/drivers/dri/nouveau/nv04_surface.c b/src/mesa/drivers/dri/nouveau/nv04_surface.c
index 6d3ffa26d3..c1eda8b7f3 100644
--- a/src/mesa/drivers/dri/nouveau/nv04_surface.c
+++ b/src/mesa/drivers/dri/nouveau/nv04_surface.c
@@ -25,7 +25,10 @@
  */
 
 #include "nouveau_driver.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv_m2mf.xml.h"
+#include "nv01_2d.xml.h"
+#include "nv04_3d.xml.h"
 #include "nouveau_context.h"
 #include "nouveau_util.h"
 #include "nv04_driver.h"
@@ -283,9 +286,9 @@ nv04_surface_copy_m2mf(struct gl_context *ctx,
 	unsigned dst_offset = dst->offset + dy * dst->pitch + dx * dst->cpp;
 	unsigned src_offset = src->offset + sy * src->pitch + sx * src->cpp;
 
-	nouveau_bo_marko(bctx, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN,
+	nouveau_bo_marko(bctx, m2mf, NV04_M2MF_DMA_BUFFER_IN,
 			 src->bo, bo_flags | NOUVEAU_BO_RD);
-	nouveau_bo_marko(bctx, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_OUT,
+	nouveau_bo_marko(bctx, m2mf, NV04_M2MF_DMA_BUFFER_OUT,
 			 dst->bo, bo_flags | NOUVEAU_BO_WR);
 
 	while (h) {
@@ -293,7 +296,7 @@ nv04_surface_copy_m2mf(struct gl_context *ctx,
 
 		MARK_RING(chan, 9, 2);
 
-		BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
+		BEGIN_RING(chan, m2mf, NV04_M2MF_OFFSET_IN, 8);
 		OUT_RELOCl(chan, src->bo, src_offset,
 			   bo_flags | NOUVEAU_BO_RD);
 		OUT_RELOCl(chan, dst->bo, dst_offset,
@@ -488,12 +491,11 @@ nv04_surface_init(struct gl_context *ctx)
 		goto fail;
 
 	/* Memory to memory format. */
-	ret = nouveau_grobj_alloc(chan, handle++, NV04_MEMORY_TO_MEMORY_FORMAT,
-				  &hw->m2mf);
+	ret = nouveau_grobj_alloc(chan, handle++, NV04_M2MF, &hw->m2mf);
 	if (ret)
 		goto fail;
 
-	BEGIN_RING(chan, hw->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
+	BEGIN_RING(chan, hw->m2mf, NV04_M2MF_DMA_NOTIFY, 1);
 	OUT_RING  (chan, hw->ntfy->handle);
 
 	/* Context surfaces 2D. */
diff --git a/src/mesa/drivers/dri/nouveau/nv10_3d.xml.h b/src/mesa/drivers/dri/nouveau/nv10_3d.xml.h
new file mode 100644
index 0000000000..cdc61f4573
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv10_3d.xml.h
@@ -0,0 +1,1619 @@
+#ifndef NV10_3D_XML
+#define NV10_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv10_3d.xml    (  18437 bytes, from 2010-11-15 15:30:21)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+- nv_3ddefs.xml  (  16394 bytes, from 2010-11-01 00:28:46)
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define NV10_VERTEX_ATTR_POS					0x00000000
+#define NV10_VERTEX_ATTR_COLOR0					0x00000001
+#define NV10_VERTEX_ATTR_COLOR1					0x00000002
+#define NV10_VERTEX_ATTR_TEX0					0x00000003
+#define NV10_VERTEX_ATTR_TEX1					0x00000004
+#define NV10_VERTEX_ATTR_NORMAL					0x00000005
+#define NV10_VERTEX_ATTR_WEIGHT					0x00000006
+#define NV10_VERTEX_ATTR_FOG					0x00000007
+
+
+
+#define NV11_3D_FLIP_SET_READ					0x00000120
+
+#define NV11_3D_FLIP_SET_WRITE					0x00000124
+
+#define NV11_3D_FLIP_MAX					0x00000128
+
+#define NV11_3D_FLIP_INCR_WRITE					0x0000012c
+
+#define NV11_3D_FLIP_WAIT					0x00000130
+
+#define NV10_3D_DMA_NOTIFY					0x00000180
+
+#define NV10_3D_DMA_TEXTURE0					0x00000184
+
+#define NV10_3D_DMA_TEXTURE1					0x00000188
+
+#define NV10_3D_DMA_COLOR					0x00000194
+
+#define NV10_3D_DMA_ZETA					0x00000198
+
+#define NV10_3D_RT_HORIZ					0x00000200
+#define NV10_3D_RT_HORIZ_X__MASK				0x0000ffff
+#define NV10_3D_RT_HORIZ_X__SHIFT				0
+#define NV10_3D_RT_HORIZ_W__MASK				0xffff0000
+#define NV10_3D_RT_HORIZ_W__SHIFT				16
+
+#define NV10_3D_RT_VERT						0x00000204
+#define NV10_3D_RT_VERT_Y__MASK					0x0000ffff
+#define NV10_3D_RT_VERT_Y__SHIFT				0
+#define NV10_3D_RT_VERT_H__MASK					0xffff0000
+#define NV10_3D_RT_VERT_H__SHIFT				16
+
+#define NV10_3D_RT_FORMAT					0x00000208
+#define NV10_3D_RT_FORMAT_TYPE__MASK				0x00000f00
+#define NV10_3D_RT_FORMAT_TYPE__SHIFT				8
+#define NV10_3D_RT_FORMAT_TYPE_LINEAR				0x00000100
+#define NV10_3D_RT_FORMAT_TYPE_SWIZZLED				0x00000200
+#define NV10_3D_RT_FORMAT_DEPTH__MASK				0x00000030
+#define NV10_3D_RT_FORMAT_DEPTH__SHIFT				4
+#define NV10_3D_RT_FORMAT_DEPTH_Z24S8				0x00000000
+#define NV10_3D_RT_FORMAT_DEPTH_Z16				0x00000010
+#define NV10_3D_RT_FORMAT_COLOR__MASK				0x0000000f
+#define NV10_3D_RT_FORMAT_COLOR__SHIFT				0
+#define NV10_3D_RT_FORMAT_COLOR_R5G6B5				0x00000003
+#define NV10_3D_RT_FORMAT_COLOR_X8R8G8B8			0x00000005
+#define NV10_3D_RT_FORMAT_COLOR_A8R8G8B8			0x00000008
+#define NV10_3D_RT_FORMAT_COLOR_B8				0x00000009
+
+#define NV10_3D_RT_PITCH					0x0000020c
+#define NV10_3D_RT_PITCH_COLOR_PITCH__MASK			0x0000ffff
+#define NV10_3D_RT_PITCH_COLOR_PITCH__SHIFT			0
+#define NV10_3D_RT_PITCH_ZETA_PITCH__MASK			0xffff0000
+#define NV10_3D_RT_PITCH_ZETA_PITCH__SHIFT			16
+
+#define NV10_3D_COLOR_OFFSET					0x00000210
+
+#define NV10_3D_ZETA_OFFSET					0x00000214
+
+#define NV10_3D_UNK0290						0x00000290
+
+#define NV10_3D_VIEWPORT_CLIP_MODE				0x000002b4
+
+#define NV10_3D_VIEWPORT_CLIP_HORIZ(i0)			       (0x000002c0 + 0x4*(i0))
+#define NV10_3D_VIEWPORT_CLIP_HORIZ__ESIZE			0x00000004
+#define NV10_3D_VIEWPORT_CLIP_HORIZ__LEN			0x00000008
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_L__MASK		0x000007ff
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_L__SHIFT		0
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_LEFT_ENABLE		0x00000800
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_R__MASK		0x07ff0000
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_R__SHIFT		16
+#define NV10_3D_VIEWPORT_CLIP_HORIZ_CLIP_RIGHT_ENABLE		0x08000000
+
+#define NV10_3D_VIEWPORT_CLIP_VERT(i0)			       (0x000002e0 + 0x4*(i0))
+#define NV10_3D_VIEWPORT_CLIP_VERT__ESIZE			0x00000004
+#define NV10_3D_VIEWPORT_CLIP_VERT__LEN				0x00000008
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_T__MASK			0x000007ff
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_T__SHIFT		0
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_TOP_ENABLE		0x00000800
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_B__MASK			0x07ff0000
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_B__SHIFT		16
+#define NV10_3D_VIEWPORT_CLIP_VERT_CLIP_BOTTOM_ENABLE		0x08000000
+
+#define NV10_3D_ALPHA_FUNC_ENABLE				0x00000300
+
+#define NV10_3D_BLEND_FUNC_ENABLE				0x00000304
+
+#define NV10_3D_CULL_FACE_ENABLE				0x00000308
+
+#define NV10_3D_DEPTH_TEST_ENABLE				0x0000030c
+
+#define NV10_3D_DITHER_ENABLE					0x00000310
+
+#define NV10_3D_LIGHTING_ENABLE					0x00000314
+
+#define NV10_3D_POINT_PARAMETERS_ENABLE				0x00000318
+
+#define NV10_3D_POINT_SMOOTH_ENABLE				0x0000031c
+
+#define NV10_3D_LINE_SMOOTH_ENABLE				0x00000320
+
+#define NV10_3D_POLYGON_SMOOTH_ENABLE				0x00000324
+
+#define NV10_3D_STENCIL_ENABLE					0x0000032c
+
+#define NV10_3D_POLYGON_OFFSET_POINT_ENABLE			0x00000330
+
+#define NV10_3D_POLYGON_OFFSET_LINE_ENABLE			0x00000334
+
+#define NV10_3D_POLYGON_OFFSET_FILL_ENABLE			0x00000338
+
+#define NV10_3D_ALPHA_FUNC_FUNC					0x0000033c
+#define NV10_3D_ALPHA_FUNC_FUNC_NEVER				0x00000200
+#define NV10_3D_ALPHA_FUNC_FUNC_LESS				0x00000201
+#define NV10_3D_ALPHA_FUNC_FUNC_EQUAL				0x00000202
+#define NV10_3D_ALPHA_FUNC_FUNC_LEQUAL				0x00000203
+#define NV10_3D_ALPHA_FUNC_FUNC_GREATER				0x00000204
+#define NV10_3D_ALPHA_FUNC_FUNC_NOTEQUAL			0x00000205
+#define NV10_3D_ALPHA_FUNC_FUNC_GEQUAL				0x00000206
+#define NV10_3D_ALPHA_FUNC_FUNC_ALWAYS				0x00000207
+
+#define NV10_3D_ALPHA_FUNC_REF					0x00000340
+
+#define NV10_3D_BLEND_FUNC_SRC					0x00000344
+#define NV10_3D_BLEND_FUNC_SRC_ZERO				0x00000000
+#define NV10_3D_BLEND_FUNC_SRC_ONE				0x00000001
+#define NV10_3D_BLEND_FUNC_SRC_SRC_COLOR			0x00000300
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR		0x00000301
+#define NV10_3D_BLEND_FUNC_SRC_SRC_ALPHA			0x00000302
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA		0x00000303
+#define NV10_3D_BLEND_FUNC_SRC_DST_ALPHA			0x00000304
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA		0x00000305
+#define NV10_3D_BLEND_FUNC_SRC_DST_COLOR			0x00000306
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR		0x00000307
+#define NV10_3D_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE		0x00000308
+#define NV10_3D_BLEND_FUNC_SRC_CONSTANT_COLOR			0x00008001
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR		0x00008002
+#define NV10_3D_BLEND_FUNC_SRC_CONSTANT_ALPHA			0x00008003
+#define NV10_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA		0x00008004
+
+#define NV10_3D_BLEND_FUNC_DST					0x00000348
+#define NV10_3D_BLEND_FUNC_DST_ZERO				0x00000000
+#define NV10_3D_BLEND_FUNC_DST_ONE				0x00000001
+#define NV10_3D_BLEND_FUNC_DST_SRC_COLOR			0x00000300
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR		0x00000301
+#define NV10_3D_BLEND_FUNC_DST_SRC_ALPHA			0x00000302
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA		0x00000303
+#define NV10_3D_BLEND_FUNC_DST_DST_ALPHA			0x00000304
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA		0x00000305
+#define NV10_3D_BLEND_FUNC_DST_DST_COLOR			0x00000306
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR		0x00000307
+#define NV10_3D_BLEND_FUNC_DST_SRC_ALPHA_SATURATE		0x00000308
+#define NV10_3D_BLEND_FUNC_DST_CONSTANT_COLOR			0x00008001
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR		0x00008002
+#define NV10_3D_BLEND_FUNC_DST_CONSTANT_ALPHA			0x00008003
+#define NV10_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA		0x00008004
+
+#define NV10_3D_BLEND_COLOR					0x0000034c
+#define NV10_3D_BLEND_COLOR_B__MASK				0x000000ff
+#define NV10_3D_BLEND_COLOR_B__SHIFT				0
+#define NV10_3D_BLEND_COLOR_G__MASK				0x0000ff00
+#define NV10_3D_BLEND_COLOR_G__SHIFT				8
+#define NV10_3D_BLEND_COLOR_R__MASK				0x00ff0000
+#define NV10_3D_BLEND_COLOR_R__SHIFT				16
+#define NV10_3D_BLEND_COLOR_A__MASK				0xff000000
+#define NV10_3D_BLEND_COLOR_A__SHIFT				24
+
+#define NV10_3D_BLEND_EQUATION					0x00000350
+#define NV10_3D_BLEND_EQUATION_FUNC_ADD				0x00008006
+#define NV10_3D_BLEND_EQUATION_MIN				0x00008007
+#define NV10_3D_BLEND_EQUATION_MAX				0x00008008
+#define NV10_3D_BLEND_EQUATION_FUNC_SUBTRACT			0x0000800a
+#define NV10_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT		0x0000800b
+
+#define NV10_3D_DEPTH_FUNC					0x00000354
+#define NV10_3D_DEPTH_FUNC_NEVER				0x00000200
+#define NV10_3D_DEPTH_FUNC_LESS					0x00000201
+#define NV10_3D_DEPTH_FUNC_EQUAL				0x00000202
+#define NV10_3D_DEPTH_FUNC_LEQUAL				0x00000203
+#define NV10_3D_DEPTH_FUNC_GREATER				0x00000204
+#define NV10_3D_DEPTH_FUNC_NOTEQUAL				0x00000205
+#define NV10_3D_DEPTH_FUNC_GEQUAL				0x00000206
+#define NV10_3D_DEPTH_FUNC_ALWAYS				0x00000207
+
+#define NV10_3D_COLOR_MASK					0x00000358
+#define NV10_3D_COLOR_MASK_B					0x00000001
+#define NV10_3D_COLOR_MASK_G					0x00000100
+#define NV10_3D_COLOR_MASK_R					0x00010000
+#define NV10_3D_COLOR_MASK_A					0x01000000
+
+#define NV10_3D_DEPTH_WRITE_ENABLE				0x0000035c
+
+#define NV10_3D_STENCIL_MASK					0x00000360
+
+#define NV10_3D_STENCIL_FUNC_FUNC				0x00000364
+#define NV10_3D_STENCIL_FUNC_FUNC_NEVER				0x00000200
+#define NV10_3D_STENCIL_FUNC_FUNC_LESS				0x00000201
+#define NV10_3D_STENCIL_FUNC_FUNC_EQUAL				0x00000202
+#define NV10_3D_STENCIL_FUNC_FUNC_LEQUAL			0x00000203
+#define NV10_3D_STENCIL_FUNC_FUNC_GREATER			0x00000204
+#define NV10_3D_STENCIL_FUNC_FUNC_NOTEQUAL			0x00000205
+#define NV10_3D_STENCIL_FUNC_FUNC_GEQUAL			0x00000206
+#define NV10_3D_STENCIL_FUNC_FUNC_ALWAYS			0x00000207
+
+#define NV10_3D_STENCIL_FUNC_REF				0x00000368
+
+#define NV10_3D_STENCIL_FUNC_MASK				0x0000036c
+
+#define NV10_3D_STENCIL_OP_FAIL					0x00000370
+#define NV10_3D_STENCIL_OP_FAIL_ZERO				0x00000000
+#define NV10_3D_STENCIL_OP_FAIL_INVERT				0x0000150a
+#define NV10_3D_STENCIL_OP_FAIL_KEEP				0x00001e00
+#define NV10_3D_STENCIL_OP_FAIL_REPLACE				0x00001e01
+#define NV10_3D_STENCIL_OP_FAIL_INCR				0x00001e02
+#define NV10_3D_STENCIL_OP_FAIL_DECR				0x00001e03
+#define NV10_3D_STENCIL_OP_FAIL_INCR_WRAP			0x00008507
+#define NV10_3D_STENCIL_OP_FAIL_DECR_WRAP			0x00008508
+
+#define NV10_3D_STENCIL_OP_ZFAIL				0x00000374
+#define NV10_3D_STENCIL_OP_ZFAIL_ZERO				0x00000000
+#define NV10_3D_STENCIL_OP_ZFAIL_INVERT				0x0000150a
+#define NV10_3D_STENCIL_OP_ZFAIL_KEEP				0x00001e00
+#define NV10_3D_STENCIL_OP_ZFAIL_REPLACE			0x00001e01
+#define NV10_3D_STENCIL_OP_ZFAIL_INCR				0x00001e02
+#define NV10_3D_STENCIL_OP_ZFAIL_DECR				0x00001e03
+#define NV10_3D_STENCIL_OP_ZFAIL_INCR_WRAP			0x00008507
+#define NV10_3D_STENCIL_OP_ZFAIL_DECR_WRAP			0x00008508
+
+#define NV10_3D_STENCIL_OP_ZPASS				0x00000378
+#define NV10_3D_STENCIL_OP_ZPASS_ZERO				0x00000000
+#define NV10_3D_STENCIL_OP_ZPASS_INVERT				0x0000150a
+#define NV10_3D_STENCIL_OP_ZPASS_KEEP				0x00001e00
+#define NV10_3D_STENCIL_OP_ZPASS_REPLACE			0x00001e01
+#define NV10_3D_STENCIL_OP_ZPASS_INCR				0x00001e02
+#define NV10_3D_STENCIL_OP_ZPASS_DECR				0x00001e03
+#define NV10_3D_STENCIL_OP_ZPASS_INCR_WRAP			0x00008507
+#define NV10_3D_STENCIL_OP_ZPASS_DECR_WRAP			0x00008508
+
+#define NV10_3D_SHADE_MODEL					0x0000037c
+#define NV10_3D_SHADE_MODEL_FLAT				0x00001d00
+#define NV10_3D_SHADE_MODEL_SMOOTH				0x00001d01
+
+#define NV10_3D_LINE_WIDTH					0x00000380
+
+#define NV10_3D_POLYGON_OFFSET_FACTOR				0x00000384
+
+#define NV10_3D_POLYGON_OFFSET_UNITS				0x00000388
+
+#define NV10_3D_POLYGON_MODE_FRONT				0x0000038c
+#define NV10_3D_POLYGON_MODE_FRONT_POINT			0x00001b00
+#define NV10_3D_POLYGON_MODE_FRONT_LINE				0x00001b01
+#define NV10_3D_POLYGON_MODE_FRONT_FILL				0x00001b02
+
+#define NV10_3D_POLYGON_MODE_BACK				0x00000390
+#define NV10_3D_POLYGON_MODE_BACK_POINT				0x00001b00
+#define NV10_3D_POLYGON_MODE_BACK_LINE				0x00001b01
+#define NV10_3D_POLYGON_MODE_BACK_FILL				0x00001b02
+
+#define NV10_3D_DEPTH_RANGE_NEAR				0x00000394
+
+#define NV10_3D_DEPTH_RANGE_FAR					0x00000398
+
+#define NV10_3D_CULL_FACE					0x0000039c
+#define NV10_3D_CULL_FACE_FRONT					0x00000404
+#define NV10_3D_CULL_FACE_BACK					0x00000405
+#define NV10_3D_CULL_FACE_FRONT_AND_BACK			0x00000408
+
+#define NV10_3D_FRONT_FACE					0x000003a0
+#define NV10_3D_FRONT_FACE_CW					0x00000900
+#define NV10_3D_FRONT_FACE_CCW					0x00000901
+
+
+#define NV10_3D_VERTEX_POS_3F					0x00000c00
+
+
+#define NV10_3D_VERTEX_POS_3F_X					0x00000c00
+
+#define NV10_3D_VERTEX_POS_3F_Y					0x00000c04
+
+#define NV10_3D_VERTEX_POS_3F_Z					0x00000c08
+
+#define NV10_3D_VERTEX_POS_4F					0x00000c18
+
+
+#define NV10_3D_VERTEX_POS_4F_X					0x00000c18
+
+#define NV10_3D_VERTEX_POS_4F_Y					0x00000c1c
+
+#define NV10_3D_VERTEX_POS_4F_Z					0x00000c20
+
+#define NV10_3D_VERTEX_POS_4F_W					0x00000c24
+
+#define NV10_3D_VERTEX_NOR_3F					0x00000c30
+
+
+#define NV10_3D_VERTEX_NOR_3F_X					0x00000c30
+
+#define NV10_3D_VERTEX_NOR_3F_Y					0x00000c34
+
+#define NV10_3D_VERTEX_NOR_3F_Z					0x00000c38
+
+#define NV10_3D_VERTEX_NOR_3I					0x00000c30
+
+
+#define NV10_3D_VERTEX_NOR_3I_XY				0x00000c30
+#define NV10_3D_VERTEX_NOR_3I_XY_X__MASK			0x0000ffff
+#define NV10_3D_VERTEX_NOR_3I_XY_X__SHIFT			0
+#define NV10_3D_VERTEX_NOR_3I_XY_Y__MASK			0xffff0000
+#define NV10_3D_VERTEX_NOR_3I_XY_Y__SHIFT			16
+
+#define NV10_3D_VERTEX_NOR_3I_Z					0x00000c34
+#define NV10_3D_VERTEX_NOR_3I_Z_Z__MASK				0x0000ffff
+#define NV10_3D_VERTEX_NOR_3I_Z_Z__SHIFT			0
+
+#define NV10_3D_VERTEX_COL_4F					0x00000c50
+
+
+#define NV10_3D_VERTEX_COL_4F_R					0x00000c50
+
+#define NV10_3D_VERTEX_COL_4F_G					0x00000c54
+
+#define NV10_3D_VERTEX_COL_4F_B					0x00000c58
+
+#define NV10_3D_VERTEX_COL_4F_A					0x00000c5c
+
+#define NV10_3D_VERTEX_COL_3F					0x00000c60
+
+
+#define NV10_3D_VERTEX_COL_3F_R					0x00000c60
+
+#define NV10_3D_VERTEX_COL_3F_G					0x00000c64
+
+#define NV10_3D_VERTEX_COL_3F_B					0x00000c68
+
+#define NV10_3D_VERTEX_COL_4I					0x00000c6c
+#define NV10_3D_VERTEX_COL_4I_R__MASK				0x000000ff
+#define NV10_3D_VERTEX_COL_4I_R__SHIFT				0
+#define NV10_3D_VERTEX_COL_4I_G__MASK				0x0000ff00
+#define NV10_3D_VERTEX_COL_4I_G__SHIFT				8
+#define NV10_3D_VERTEX_COL_4I_B__MASK				0x00ff0000
+#define NV10_3D_VERTEX_COL_4I_B__SHIFT				16
+#define NV10_3D_VERTEX_COL_4I_A__MASK				0xff000000
+#define NV10_3D_VERTEX_COL_4I_A__SHIFT				24
+
+#define NV10_3D_VERTEX_COL2_3F					0x00000c80
+
+
+#define NV10_3D_VERTEX_COL2_3F_R				0x00000c80
+
+#define NV10_3D_VERTEX_COL2_3F_G				0x00000c84
+
+#define NV10_3D_VERTEX_COL2_3F_B				0x00000c88
+
+#define NV10_3D_VERTEX_COL2_3I					0x00000c8c
+#define NV10_3D_VERTEX_COL2_3I_R__MASK				0x000000ff
+#define NV10_3D_VERTEX_COL2_3I_R__SHIFT				0
+#define NV10_3D_VERTEX_COL2_3I_G__MASK				0x0000ff00
+#define NV10_3D_VERTEX_COL2_3I_G__SHIFT				8
+#define NV10_3D_VERTEX_COL2_3I_B__MASK				0x00ff0000
+#define NV10_3D_VERTEX_COL2_3I_B__SHIFT				16
+
+#define NV10_3D_VERTEX_TX0_2F					0x00000c90
+
+
+#define NV10_3D_VERTEX_TX0_2F_S					0x00000c90
+
+#define NV10_3D_VERTEX_TX0_2F_T					0x00000c94
+
+#define NV10_3D_VERTEX_TX0_2I					0x00000c98
+#define NV10_3D_VERTEX_TX0_2I_S__MASK				0x0000ffff
+#define NV10_3D_VERTEX_TX0_2I_S__SHIFT				0
+#define NV10_3D_VERTEX_TX0_2I_T__MASK				0xffff0000
+#define NV10_3D_VERTEX_TX0_2I_T__SHIFT				16
+
+#define NV10_3D_VERTEX_TX0_4F					0x00000ca0
+
+
+#define NV10_3D_VERTEX_TX0_4F_S					0x00000ca0
+
+#define NV10_3D_VERTEX_TX0_4F_T					0x00000ca4
+
+#define NV10_3D_VERTEX_TX0_4F_R					0x00000ca8
+
+#define NV10_3D_VERTEX_TX0_4F_Q					0x00000cac
+
+#define NV10_3D_VERTEX_TX0_4I					0x00000cb0
+
+
+#define NV10_3D_VERTEX_TX0_4I_ST				0x00000cb0
+#define NV10_3D_VERTEX_TX0_4I_ST_S__MASK			0x0000ffff
+#define NV10_3D_VERTEX_TX0_4I_ST_S__SHIFT			0
+#define NV10_3D_VERTEX_TX0_4I_ST_T__MASK			0xffff0000
+#define NV10_3D_VERTEX_TX0_4I_ST_T__SHIFT			16
+
+#define NV10_3D_VERTEX_TX0_4I_RQ				0x00000cb4
+#define NV10_3D_VERTEX_TX0_4I_RQ_R__MASK			0x0000ffff
+#define NV10_3D_VERTEX_TX0_4I_RQ_R__SHIFT			0
+#define NV10_3D_VERTEX_TX0_4I_RQ_Q__MASK			0xffff0000
+#define NV10_3D_VERTEX_TX0_4I_RQ_Q__SHIFT			16
+
+#define NV10_3D_VERTEX_TX1_2F					0x00000cb8
+
+
+#define NV10_3D_VERTEX_TX1_2F_S					0x00000cb8
+
+#define NV10_3D_VERTEX_TX1_2F_T					0x00000cbc
+
+#define NV10_3D_VERTEX_TX1_2I					0x00000cc0
+#define NV10_3D_VERTEX_TX1_2I_S__MASK				0x0000ffff
+#define NV10_3D_VERTEX_TX1_2I_S__SHIFT				0
+#define NV10_3D_VERTEX_TX1_2I_T__MASK				0xffff0000
+#define NV10_3D_VERTEX_TX1_2I_T__SHIFT				16
+
+#define NV10_3D_VERTEX_TX1_4F					0x00000cc8
+
+
+#define NV10_3D_VERTEX_TX1_4F_S					0x00000cc8
+
+#define NV10_3D_VERTEX_TX1_4F_T					0x00000ccc
+
+#define NV10_3D_VERTEX_TX1_4F_R					0x00000cd0
+
+#define NV10_3D_VERTEX_TX1_4F_Q					0x00000cd4
+
+#define NV10_3D_VERTEX_TX1_4I					0x00000cd8
+
+
+#define NV10_3D_VERTEX_TX1_4I_ST				0x00000cd8
+#define NV10_3D_VERTEX_TX1_4I_ST_S__MASK			0x0000ffff
+#define NV10_3D_VERTEX_TX1_4I_ST_S__SHIFT			0
+#define NV10_3D_VERTEX_TX1_4I_ST_T__MASK			0xffff0000
+#define NV10_3D_VERTEX_TX1_4I_ST_T__SHIFT			16
+
+#define NV10_3D_VERTEX_TX1_4I_RQ				0x00000cdc
+#define NV10_3D_VERTEX_TX1_4I_RQ_R__MASK			0x0000ffff
+#define NV10_3D_VERTEX_TX1_4I_RQ_R__SHIFT			0
+#define NV10_3D_VERTEX_TX1_4I_RQ_Q__MASK			0xffff0000
+#define NV10_3D_VERTEX_TX1_4I_RQ_Q__SHIFT			16
+
+#define NV10_3D_VERTEX_FOG_1F					0x00000ce0
+
+#define NV10_3D_VERTEX_WGH_1F					0x00000ce4
+
+#define NV10_3D_EDGEFLAG_ENABLE					0x00000cec
+
+
+#define NV10_3D_DMA_VTXBUF					0x0000018c
+
+#define NV10_3D_VTXBUF_VALIDATE					0x00000cf0
+
+
+#define NV10_3D_VTXBUF_OFFSET(i0)			       (0x00000d00 + 0x8*(i0))
+
+#define NV10_3D_VTXBUF_FMT(i0)				       (0x00000d04 + 0x8*(i0))
+#define NV10_3D_VTXBUF_FMT_TYPE__MASK				0x0000000f
+#define NV10_3D_VTXBUF_FMT_TYPE__SHIFT				0
+#define NV10_3D_VTXBUF_FMT_TYPE_B8G8R8A8_UNORM			0x00000000
+#define NV10_3D_VTXBUF_FMT_TYPE_V16_SNORM			0x00000001
+#define NV10_3D_VTXBUF_FMT_TYPE_V32_FLOAT			0x00000002
+#define NV10_3D_VTXBUF_FMT_TYPE_U8_UNORM			0x00000004
+#define NV10_3D_VTXBUF_FMT_FIELDS__MASK				0x000000f0
+#define NV10_3D_VTXBUF_FMT_FIELDS__SHIFT			4
+#define NV10_3D_VTXBUF_FMT_STRIDE__MASK				0x0000ff00
+#define NV10_3D_VTXBUF_FMT_STRIDE__SHIFT			8
+#define NV10_3D_VTXBUF_FMT_HOMOGENEOUS				0x01000000
+
+#define NV10_3D_VERTEX_BEGIN_END				0x00000dfc
+#define NV10_3D_VERTEX_BEGIN_END_STOP				0x00000000
+#define NV10_3D_VERTEX_BEGIN_END_POINTS				0x00000001
+#define NV10_3D_VERTEX_BEGIN_END_LINES				0x00000002
+#define NV10_3D_VERTEX_BEGIN_END_LINE_LOOP			0x00000003
+#define NV10_3D_VERTEX_BEGIN_END_LINE_STRIP			0x00000004
+#define NV10_3D_VERTEX_BEGIN_END_TRIANGLES			0x00000005
+#define NV10_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP			0x00000006
+#define NV10_3D_VERTEX_BEGIN_END_TRIANGLE_FAN			0x00000007
+#define NV10_3D_VERTEX_BEGIN_END_QUADS				0x00000008
+#define NV10_3D_VERTEX_BEGIN_END_QUAD_STRIP			0x00000009
+#define NV10_3D_VERTEX_BEGIN_END_POLYGON			0x0000000a
+
+#define NV10_3D_VTXBUF_ELEMENT_U16				0x00000e00
+#define NV10_3D_VTXBUF_ELEMENT_U16_I0__MASK			0x0000ffff
+#define NV10_3D_VTXBUF_ELEMENT_U16_I0__SHIFT			0
+#define NV10_3D_VTXBUF_ELEMENT_U16_I1__MASK			0xffff0000
+#define NV10_3D_VTXBUF_ELEMENT_U16_I1__SHIFT			16
+
+#define NV10_3D_VTXBUF_ELEMENT_U32				0x00001100
+
+#define NV10_3D_VTXBUF_BEGIN_END				0x000013fc
+#define NV10_3D_VTXBUF_BEGIN_END_STOP				0x00000000
+#define NV10_3D_VTXBUF_BEGIN_END_POINTS				0x00000001
+#define NV10_3D_VTXBUF_BEGIN_END_LINES				0x00000002
+#define NV10_3D_VTXBUF_BEGIN_END_LINE_LOOP			0x00000003
+#define NV10_3D_VTXBUF_BEGIN_END_LINE_STRIP			0x00000004
+#define NV10_3D_VTXBUF_BEGIN_END_TRIANGLES			0x00000005
+#define NV10_3D_VTXBUF_BEGIN_END_TRIANGLE_STRIP			0x00000006
+#define NV10_3D_VTXBUF_BEGIN_END_TRIANGLE_FAN			0x00000007
+#define NV10_3D_VTXBUF_BEGIN_END_QUADS				0x00000008
+#define NV10_3D_VTXBUF_BEGIN_END_QUAD_STRIP			0x00000009
+#define NV10_3D_VTXBUF_BEGIN_END_POLYGON			0x0000000a
+
+#define NV10_3D_VTXBUF_BATCH					0x00001400
+#define NV10_3D_VTXBUF_BATCH_FIRST__MASK			0x0000ffff
+#define NV10_3D_VTXBUF_BATCH_FIRST__SHIFT			0
+#define NV10_3D_VTXBUF_BATCH_LAST__MASK				0xff000000
+#define NV10_3D_VTXBUF_BATCH_LAST__SHIFT			24
+
+#define NV10_3D_VTXBUF_DATA					0x00001800
+
+
+#define NV10_3D_VERTEX_WEIGHT_ENABLE				0x00000328
+
+#define NV10_3D_VIEW_MATRIX_ENABLE				0x000003e8
+#define NV10_3D_VIEW_MATRIX_ENABLE_MODELVIEW1			0x00000001
+#define NV10_3D_VIEW_MATRIX_ENABLE_MODELVIEW0			0x00000002
+#define NV10_3D_VIEW_MATRIX_ENABLE_PROJECTION			0x00000004
+
+
+#define NV10_3D_MODELVIEW_MATRIX(i0, i1)		       (0x00000400 + 0x40*(i0) + 0x4*(i1))
+#define NV10_3D_MODELVIEW_MATRIX__ESIZE				0x00000004
+#define NV10_3D_MODELVIEW_MATRIX__LEN				0x00000010
+
+#define NV10_3D_INVERSE_MODELVIEW_MATRIX(i0, i1)	       (0x00000480 + 0x40*(i0) + 0x4*(i1))
+#define NV10_3D_INVERSE_MODELVIEW_MATRIX__ESIZE			0x00000004
+#define NV10_3D_INVERSE_MODELVIEW_MATRIX__LEN			0x0000000c
+
+#define NV10_3D_PROJECTION_MATRIX(i0)			       (0x00000500 + 0x4*(i0))
+#define NV10_3D_PROJECTION_MATRIX__ESIZE			0x00000004
+#define NV10_3D_PROJECTION_MATRIX__LEN				0x00000010
+
+#define NV10_3D_VIEWPORT_TRANSLATE				0x000006e8
+
+
+#define NV10_3D_VIEWPORT_TRANSLATE_X				0x000006e8
+
+#define NV10_3D_VIEWPORT_TRANSLATE_Y				0x000006ec
+
+#define NV10_3D_VIEWPORT_TRANSLATE_Z				0x000006f0
+
+#define NV10_3D_VIEWPORT_TRANSLATE_W				0x000006f4
+
+
+#define NV10_3D_LIGHT_MODEL					0x00000294
+#define NV10_3D_LIGHT_MODEL_VERTEX_SPECULAR			0x00000001
+#define NV10_3D_LIGHT_MODEL_SEPARATE_SPECULAR			0x00000002
+#define NV10_3D_LIGHT_MODEL_LOCAL_VIEWER			0x00010000
+
+#define NV10_3D_COLOR_MATERIAL					0x00000298
+#define NV10_3D_COLOR_MATERIAL_EMISSION				0x00000001
+#define NV10_3D_COLOR_MATERIAL_AMBIENT				0x00000002
+#define NV10_3D_COLOR_MATERIAL_DIFFUSE				0x00000004
+#define NV10_3D_COLOR_MATERIAL_SPECULAR				0x00000008
+
+#define NV10_3D_MATERIAL_FACTOR					0x000003a8
+
+
+#define NV10_3D_MATERIAL_FACTOR_R				0x000003a8
+
+#define NV10_3D_MATERIAL_FACTOR_G				0x000003ac
+
+#define NV10_3D_MATERIAL_FACTOR_B				0x000003b0
+
+#define NV10_3D_MATERIAL_FACTOR_A				0x000003b4
+
+#define NV10_3D_NORMALIZE_ENABLE				0x000003a4
+
+#define NV10_3D_SEPARATE_SPECULAR_ENABLE			0x000003b8
+
+#define NV10_3D_ENABLED_LIGHTS					0x000003bc
+#define NV10_3D_ENABLED_LIGHTS_0__MASK				0x00000003
+#define NV10_3D_ENABLED_LIGHTS_0__SHIFT				0
+#define NV10_3D_ENABLED_LIGHTS_0_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_0_NONPOSITIONAL			0x00000001
+#define NV10_3D_ENABLED_LIGHTS_0_POSITIONAL			0x00000002
+#define NV10_3D_ENABLED_LIGHTS_0_DIRECTIONAL			0x00000003
+#define NV10_3D_ENABLED_LIGHTS_1__MASK				0x0000000c
+#define NV10_3D_ENABLED_LIGHTS_1__SHIFT				2
+#define NV10_3D_ENABLED_LIGHTS_1_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_1_NONPOSITIONAL			0x00000004
+#define NV10_3D_ENABLED_LIGHTS_1_POSITIONAL			0x00000008
+#define NV10_3D_ENABLED_LIGHTS_1_DIRECTIONAL			0x0000000c
+#define NV10_3D_ENABLED_LIGHTS_2__MASK				0x00000030
+#define NV10_3D_ENABLED_LIGHTS_2__SHIFT				4
+#define NV10_3D_ENABLED_LIGHTS_2_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_2_NONPOSITIONAL			0x00000010
+#define NV10_3D_ENABLED_LIGHTS_2_POSITIONAL			0x00000020
+#define NV10_3D_ENABLED_LIGHTS_2_DIRECTIONAL			0x00000030
+#define NV10_3D_ENABLED_LIGHTS_3__MASK				0x000000c0
+#define NV10_3D_ENABLED_LIGHTS_3__SHIFT				6
+#define NV10_3D_ENABLED_LIGHTS_3_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_3_NONPOSITIONAL			0x00000040
+#define NV10_3D_ENABLED_LIGHTS_3_POSITIONAL			0x00000080
+#define NV10_3D_ENABLED_LIGHTS_3_DIRECTIONAL			0x000000c0
+#define NV10_3D_ENABLED_LIGHTS_4__MASK				0x00000300
+#define NV10_3D_ENABLED_LIGHTS_4__SHIFT				8
+#define NV10_3D_ENABLED_LIGHTS_4_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_4_NONPOSITIONAL			0x00000100
+#define NV10_3D_ENABLED_LIGHTS_4_POSITIONAL			0x00000200
+#define NV10_3D_ENABLED_LIGHTS_4_DIRECTIONAL			0x00000300
+#define NV10_3D_ENABLED_LIGHTS_5__MASK				0x00000c00
+#define NV10_3D_ENABLED_LIGHTS_5__SHIFT				10
+#define NV10_3D_ENABLED_LIGHTS_5_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_5_NONPOSITIONAL			0x00000400
+#define NV10_3D_ENABLED_LIGHTS_5_POSITIONAL			0x00000800
+#define NV10_3D_ENABLED_LIGHTS_5_DIRECTIONAL			0x00000c00
+#define NV10_3D_ENABLED_LIGHTS_6__MASK				0x00003000
+#define NV10_3D_ENABLED_LIGHTS_6__SHIFT				12
+#define NV10_3D_ENABLED_LIGHTS_6_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_6_NONPOSITIONAL			0x00001000
+#define NV10_3D_ENABLED_LIGHTS_6_POSITIONAL			0x00002000
+#define NV10_3D_ENABLED_LIGHTS_6_DIRECTIONAL			0x00003000
+#define NV10_3D_ENABLED_LIGHTS_7__MASK				0x0000c000
+#define NV10_3D_ENABLED_LIGHTS_7__SHIFT				14
+#define NV10_3D_ENABLED_LIGHTS_7_DISABLED			0x00000000
+#define NV10_3D_ENABLED_LIGHTS_7_NONPOSITIONAL			0x00004000
+#define NV10_3D_ENABLED_LIGHTS_7_POSITIONAL			0x00008000
+#define NV10_3D_ENABLED_LIGHTS_7_DIRECTIONAL			0x0000c000
+
+#define NV10_3D_MATERIAL_SHININESS(i0)			       (0x000006a0 + 0x4*(i0))
+#define NV10_3D_MATERIAL_SHININESS__ESIZE			0x00000004
+#define NV10_3D_MATERIAL_SHININESS__LEN				0x00000006
+
+#define NV10_3D_LIGHT_MODEL_AMBIENT				0x000006c4
+
+
+#define NV10_3D_LIGHT_MODEL_AMBIENT_R				0x000006c4
+
+#define NV10_3D_LIGHT_MODEL_AMBIENT_G				0x000006c8
+
+#define NV10_3D_LIGHT_MODEL_AMBIENT_B				0x000006cc
+
+#define NV10_3D_LIGHT(i0)				       (0x00000800 + 0x80*(i0))
+#define NV10_3D_LIGHT__ESIZE					0x00000080
+#define NV10_3D_LIGHT__LEN					0x00000008
+
+#define NV10_3D_LIGHT_AMBIENT(i0)			       (0x00000800 + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_AMBIENT_R(i0)			       (0x00000800 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_AMBIENT_G(i0)			       (0x00000804 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_AMBIENT_B(i0)			       (0x00000808 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIFFUSE(i0)			       (0x0000080c + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_DIFFUSE_R(i0)			       (0x0000080c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIFFUSE_G(i0)			       (0x00000810 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIFFUSE_B(i0)			       (0x00000814 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_SPECULAR(i0)			       (0x00000818 + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_SPECULAR_R(i0)			       (0x00000818 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_SPECULAR_G(i0)			       (0x0000081c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_SPECULAR_B(i0)			       (0x00000820 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_HALF_VECTOR(i0)			       (0x00000828 + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_HALF_VECTOR_X(i0)			       (0x00000828 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_HALF_VECTOR_Y(i0)			       (0x0000082c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_HALF_VECTOR_Z(i0)			       (0x00000830 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIRECTION(i0)			       (0x00000834 + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_DIRECTION_X(i0)			       (0x00000834 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIRECTION_Y(i0)			       (0x00000838 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_DIRECTION_Z(i0)			       (0x0000083c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_SPOT_CUTOFF(i0, i1)		       (0x00000840 + 0x80*(i0) + 0x4*(i1))
+#define NV10_3D_LIGHT_SPOT_CUTOFF__ESIZE			0x00000004
+#define NV10_3D_LIGHT_SPOT_CUTOFF__LEN				0x00000007
+
+#define NV10_3D_LIGHT_POSITION(i0)			       (0x0000085c + 0x80*(i0))
+
+
+#define NV10_3D_LIGHT_POSITION_X(i0)			       (0x0000085c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_POSITION_Y(i0)			       (0x00000860 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_POSITION_Z(i0)			       (0x00000864 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_ATTENUATION(i0)			       (0x00000868 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_ATTENUATION_CONSTANT(i0)		       (0x00000868 + 0x80*(i0))
+
+#define NV10_3D_LIGHT_ATTENUATION_LINEAR(i0)		       (0x0000086c + 0x80*(i0))
+
+#define NV10_3D_LIGHT_ATTENUATION_QUADRATIC(i0)		       (0x00000870 + 0x80*(i0))
+
+
+#define NV10_3D_FOG_MODE					0x0000029c
+#define NV10_3D_FOG_MODE_LINEAR					0x00002601
+#define NV10_3D_FOG_MODE_EXP					0x00000800
+#define NV10_3D_FOG_MODE_EXP_ABS				0x00000802
+#define NV10_3D_FOG_MODE_EXP2					0x00000803
+
+#define NV10_3D_FOG_COORD					0x000002a0
+#define NV10_3D_FOG_COORD_FOG					0x00000000
+#define NV10_3D_FOG_COORD_DIST_RADIAL				0x00000001
+#define NV10_3D_FOG_COORD_DIST_ORTHOGONAL			0x00000002
+#define NV10_3D_FOG_COORD_DIST_ORTHOGONAL_ABS			0x00000003
+
+#define NV10_3D_FOG_ENABLE					0x000002a4
+
+#define NV10_3D_FOG_COLOR					0x000002a8
+#define NV10_3D_FOG_COLOR_R__MASK				0x000000ff
+#define NV10_3D_FOG_COLOR_R__SHIFT				0
+#define NV10_3D_FOG_COLOR_G__MASK				0x0000ff00
+#define NV10_3D_FOG_COLOR_G__SHIFT				8
+#define NV10_3D_FOG_COLOR_B__MASK				0x00ff0000
+#define NV10_3D_FOG_COLOR_B__SHIFT				16
+#define NV10_3D_FOG_COLOR_A__MASK				0xff000000
+#define NV10_3D_FOG_COLOR_A__SHIFT				24
+
+#define NV10_3D_FOG_COEFF(i0)				       (0x00000680 + 0x4*(i0))
+#define NV10_3D_FOG_COEFF__ESIZE				0x00000004
+#define NV10_3D_FOG_COEFF__LEN					0x00000003
+
+
+
+#define NV10_3D_TEX_GEN_MODE(i0, i1)			       (0x000003c0 + 0x10*(i0) + 0x4*(i1))
+#define NV10_3D_TEX_GEN_MODE__ESIZE				0x00000004
+#define NV10_3D_TEX_GEN_MODE__LEN				0x00000004
+#define NV10_3D_TEX_GEN_MODE_FALSE				0x00000000
+#define NV10_3D_TEX_GEN_MODE_EYE_LINEAR				0x00002400
+#define NV10_3D_TEX_GEN_MODE_OBJECT_LINEAR			0x00002401
+#define NV10_3D_TEX_GEN_MODE_SPHERE_MAP				0x00002402
+#define NV10_3D_TEX_GEN_MODE_NORMAL_MAP				0x00008511
+#define NV10_3D_TEX_GEN_MODE_REFLECTION_MAP			0x00008512
+
+
+#define NV10_3D_TEX_GEN_COEFF(i0, i1)			       (0x00000600 + 0x40*(i0) + 0x10*(i1))
+#define NV10_3D_TEX_GEN_COEFF__ESIZE				0x00000010
+#define NV10_3D_TEX_GEN_COEFF__LEN				0x00000004
+
+#define NV10_3D_TEX_GEN_COEFF_A(i0, i1)			       (0x00000600 + 0x40*(i0) + 0x10*(i1))
+
+#define NV10_3D_TEX_GEN_COEFF_B(i0, i1)			       (0x00000604 + 0x40*(i0) + 0x10*(i1))
+
+#define NV10_3D_TEX_GEN_COEFF_C(i0, i1)			       (0x00000608 + 0x40*(i0) + 0x10*(i1))
+
+#define NV10_3D_TEX_GEN_COEFF_D(i0, i1)			       (0x0000060c + 0x40*(i0) + 0x10*(i1))
+
+#define NV10_3D_TEX_MATRIX_ENABLE(i0)			       (0x000003e0 + 0x4*(i0))
+#define NV10_3D_TEX_MATRIX_ENABLE__ESIZE			0x00000004
+#define NV10_3D_TEX_MATRIX_ENABLE__LEN				0x00000002
+
+
+#define NV10_3D_TEX_MATRIX(i0, i1)			       (0x00000540 + 0x40*(i0) + 0x4*(i1))
+#define NV10_3D_TEX_MATRIX__ESIZE				0x00000004
+#define NV10_3D_TEX_MATRIX__LEN					0x00000010
+
+#define NV10_3D_TEX(i0)					       (0x00000000 + 0x4*(i0))
+#define NV10_3D_TEX__ESIZE					0x00000004
+#define NV10_3D_TEX__LEN					0x00000002
+
+#define NV10_3D_TEX_OFFSET(i0)				       (0x00000218 + 0x4*(i0))
+
+#define NV10_3D_TEX_FORMAT(i0)				       (0x00000220 + 0x4*(i0))
+#define NV10_3D_TEX_FORMAT_DMA0					0x00000001
+#define NV10_3D_TEX_FORMAT_DMA1					0x00000002
+#define NV10_3D_TEX_FORMAT_CUBE_MAP				0x00000004
+#define NV10_3D_TEX_FORMAT_FORMAT__MASK				0x00000f80
+#define NV10_3D_TEX_FORMAT_FORMAT__SHIFT			7
+#define NV10_3D_TEX_FORMAT_FORMAT_L8				0x00000000
+#define NV10_3D_TEX_FORMAT_FORMAT_I8				0x00000080
+#define NV10_3D_TEX_FORMAT_FORMAT_A1R5G5B5			0x00000100
+#define NV10_3D_TEX_FORMAT_FORMAT_A4R4G4B4			0x00000200
+#define NV10_3D_TEX_FORMAT_FORMAT_R5G6B5			0x00000280
+#define NV10_3D_TEX_FORMAT_FORMAT_A8R8G8B8			0x00000300
+#define NV10_3D_TEX_FORMAT_FORMAT_X8R8G8B8			0x00000380
+#define NV10_3D_TEX_FORMAT_FORMAT_INDEX8			0x00000580
+#define NV10_3D_TEX_FORMAT_FORMAT_DXT1				0x00000600
+#define NV10_3D_TEX_FORMAT_FORMAT_DXT3				0x00000700
+#define NV10_3D_TEX_FORMAT_FORMAT_DXT5				0x00000780
+#define NV10_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT			0x00000800
+#define NV10_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT			0x00000880
+#define NV10_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT			0x00000900
+#define NV10_3D_TEX_FORMAT_FORMAT_I8_RECT			0x00000980
+#define NV10_3D_TEX_FORMAT_MIPMAP				0x00008000
+#define NV10_3D_TEX_FORMAT_BASE_SIZE_U__MASK			0x000f0000
+#define NV10_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT			16
+#define NV10_3D_TEX_FORMAT_BASE_SIZE_V__MASK			0x00f00000
+#define NV10_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT			20
+#define NV10_3D_TEX_FORMAT_WRAP_S__MASK				0x0f000000
+#define NV10_3D_TEX_FORMAT_WRAP_S__SHIFT			24
+#define NV10_3D_TEX_FORMAT_WRAP_S_REPEAT			0x01000000
+#define NV10_3D_TEX_FORMAT_WRAP_S_MIRRORED_REPEAT		0x02000000
+#define NV10_3D_TEX_FORMAT_WRAP_S_CLAMP_TO_EDGE			0x03000000
+#define NV10_3D_TEX_FORMAT_WRAP_S_CLAMP_TO_BORDER		0x04000000
+#define NV10_3D_TEX_FORMAT_WRAP_S_CLAMP				0x05000000
+#define NV10_3D_TEX_FORMAT_WRAP_T__MASK				0xf0000000
+#define NV10_3D_TEX_FORMAT_WRAP_T__SHIFT			28
+#define NV10_3D_TEX_FORMAT_WRAP_T_REPEAT			0x10000000
+#define NV10_3D_TEX_FORMAT_WRAP_T_MIRRORED_REPEAT		0x20000000
+#define NV10_3D_TEX_FORMAT_WRAP_T_CLAMP_TO_EDGE			0x30000000
+#define NV10_3D_TEX_FORMAT_WRAP_T_CLAMP_TO_BORDER		0x40000000
+#define NV10_3D_TEX_FORMAT_WRAP_T_CLAMP				0x50000000
+
+#define NV10_3D_TEX_ENABLE(i0)				       (0x00000228 + 0x4*(i0))
+#define NV10_3D_TEX_ENABLE_CULL__MASK				0x0000000f
+#define NV10_3D_TEX_ENABLE_CULL__SHIFT				0
+#define NV10_3D_TEX_ENABLE_CULL_DISABLED			0x00000000
+#define NV10_3D_TEX_ENABLE_CULL_TEST_ALL			0x00000003
+#define NV10_3D_TEX_ENABLE_CULL_TEST_ALPHA			0x00000004
+#define NV10_3D_TEX_ENABLE_ANISOTROPY__MASK			0x00000030
+#define NV10_3D_TEX_ENABLE_ANISOTROPY__SHIFT			4
+#define NV10_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK			0x0003c000
+#define NV10_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT		14
+#define NV10_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK			0x3c000000
+#define NV10_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT		26
+#define NV10_3D_TEX_ENABLE_ENABLE				0x40000000
+
+#define NV10_3D_TEX_NPOT_PITCH(i0)			       (0x00000230 + 0x4*(i0))
+#define NV10_3D_TEX_NPOT_PITCH_PITCH__MASK			0xffff0000
+#define NV10_3D_TEX_NPOT_PITCH_PITCH__SHIFT			16
+
+#define NV10_3D_TEX_NPOT_SIZE(i0)			       (0x00000240 + 0x4*(i0))
+#define NV10_3D_TEX_NPOT_SIZE_H__MASK				0x0000ffff
+#define NV10_3D_TEX_NPOT_SIZE_H__SHIFT				0
+#define NV10_3D_TEX_NPOT_SIZE_W__MASK				0xffff0000
+#define NV10_3D_TEX_NPOT_SIZE_W__SHIFT				16
+
+#define NV10_3D_TEX_FILTER(i0)				       (0x00000248 + 0x4*(i0))
+#define NV10_3D_TEX_FILTER_LOD_BIAS__MASK			0x00000f00
+#define NV10_3D_TEX_FILTER_LOD_BIAS__SHIFT			8
+#define NV10_3D_TEX_FILTER_MINIFY__MASK				0x0f000000
+#define NV10_3D_TEX_FILTER_MINIFY__SHIFT			24
+#define NV10_3D_TEX_FILTER_MINIFY_NEAREST			0x01000000
+#define NV10_3D_TEX_FILTER_MINIFY_LINEAR			0x02000000
+#define NV10_3D_TEX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST	0x03000000
+#define NV10_3D_TEX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST		0x04000000
+#define NV10_3D_TEX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR		0x05000000
+#define NV10_3D_TEX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR		0x06000000
+#define NV10_3D_TEX_FILTER_MAGNIFY__MASK			0xf0000000
+#define NV10_3D_TEX_FILTER_MAGNIFY__SHIFT			28
+#define NV10_3D_TEX_FILTER_MAGNIFY_NEAREST			0x10000000
+#define NV10_3D_TEX_FILTER_MAGNIFY_LINEAR			0x20000000
+
+#define NV10_3D_TEX_PALETTE_OFFSET(i0)			       (0x00000250 + 0x4*(i0))
+
+
+
+#define NV10_3D_RC_IN_ALPHA(i0)				       (0x00000260 + 0x4*(i0))
+#define NV10_3D_RC_IN_ALPHA_D_INPUT__MASK			0x0000000f
+#define NV10_3D_RC_IN_ALPHA_D_INPUT__SHIFT			0
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_ZERO			0x00000000
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_FOG				0x00000003
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR		0x00000004
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0			0x00000008
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1			0x00000009
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_TEXTURE2			0x0000000a
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_TEXTURE3			0x0000000b
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_SPARE0			0x0000000c
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_SPARE1			0x0000000d
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV10_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F			0x0000000f
+#define NV10_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV10_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__SHIFT		4
+#define NV10_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE		0x00000000
+#define NV10_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING__MASK			0x000000e0
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING__SHIFT			5
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV10_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV10_3D_RC_IN_ALPHA_C_INPUT__MASK			0x00000f00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT__SHIFT			8
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_ZERO			0x00000000
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_FOG				0x00000300
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR		0x00000400
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0			0x00000800
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1			0x00000900
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_TEXTURE2			0x00000a00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_TEXTURE3			0x00000b00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F			0x00000f00
+#define NV10_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV10_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__SHIFT		12
+#define NV10_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE		0x00000000
+#define NV10_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING__MASK			0x0000e000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING__SHIFT			13
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV10_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT__MASK			0x000f0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT__SHIFT			16
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_ZERO			0x00000000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_FOG				0x00030000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR		0x00040000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0			0x00080000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1			0x00090000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_TEXTURE2			0x000a0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_TEXTURE3			0x000b0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_SPARE0			0x000c0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_SPARE1			0x000d0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV10_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F			0x000f0000
+#define NV10_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV10_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__SHIFT		20
+#define NV10_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE		0x00000000
+#define NV10_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING__MASK			0x00e00000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING__SHIFT			21
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV10_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT__MASK			0x0f000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT__SHIFT			24
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_ZERO			0x00000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_FOG				0x03000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR		0x04000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0			0x08000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1			0x09000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_TEXTURE2			0x0a000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_TEXTURE3			0x0b000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_SPARE0			0x0c000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_SPARE1			0x0d000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV10_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F			0x0f000000
+#define NV10_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV10_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__SHIFT		28
+#define NV10_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE		0x00000000
+#define NV10_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING__MASK			0xe0000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING__SHIFT			29
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV10_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV10_3D_RC_IN_RGB(i0)				       (0x00000268 + 0x4*(i0))
+#define NV10_3D_RC_IN_RGB_D_INPUT__MASK				0x0000000f
+#define NV10_3D_RC_IN_RGB_D_INPUT__SHIFT			0
+#define NV10_3D_RC_IN_RGB_D_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV10_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV10_3D_RC_IN_RGB_D_INPUT_FOG				0x00000003
+#define NV10_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR			0x00000004
+#define NV10_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV10_3D_RC_IN_RGB_D_INPUT_TEXTURE0			0x00000008
+#define NV10_3D_RC_IN_RGB_D_INPUT_TEXTURE1			0x00000009
+#define NV10_3D_RC_IN_RGB_D_INPUT_TEXTURE2			0x0000000a
+#define NV10_3D_RC_IN_RGB_D_INPUT_TEXTURE3			0x0000000b
+#define NV10_3D_RC_IN_RGB_D_INPUT_SPARE0			0x0000000c
+#define NV10_3D_RC_IN_RGB_D_INPUT_SPARE1			0x0000000d
+#define NV10_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV10_3D_RC_IN_RGB_D_INPUT_E_TIMES_F			0x0000000f
+#define NV10_3D_RC_IN_RGB_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV10_3D_RC_IN_RGB_D_COMPONENT_USAGE__SHIFT		4
+#define NV10_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV10_3D_RC_IN_RGB_D_MAPPING__MASK			0x000000e0
+#define NV10_3D_RC_IN_RGB_D_MAPPING__SHIFT			5
+#define NV10_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV10_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV10_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV10_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV10_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV10_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV10_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV10_3D_RC_IN_RGB_C_INPUT__MASK				0x00000f00
+#define NV10_3D_RC_IN_RGB_C_INPUT__SHIFT			8
+#define NV10_3D_RC_IN_RGB_C_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_IN_RGB_C_INPUT_FOG				0x00000300
+#define NV10_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR			0x00000400
+#define NV10_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_IN_RGB_C_INPUT_TEXTURE0			0x00000800
+#define NV10_3D_RC_IN_RGB_C_INPUT_TEXTURE1			0x00000900
+#define NV10_3D_RC_IN_RGB_C_INPUT_TEXTURE2			0x00000a00
+#define NV10_3D_RC_IN_RGB_C_INPUT_TEXTURE3			0x00000b00
+#define NV10_3D_RC_IN_RGB_C_INPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_IN_RGB_C_INPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_IN_RGB_C_INPUT_E_TIMES_F			0x00000f00
+#define NV10_3D_RC_IN_RGB_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV10_3D_RC_IN_RGB_C_COMPONENT_USAGE__SHIFT		12
+#define NV10_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV10_3D_RC_IN_RGB_C_MAPPING__MASK			0x0000e000
+#define NV10_3D_RC_IN_RGB_C_MAPPING__SHIFT			13
+#define NV10_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV10_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV10_3D_RC_IN_RGB_B_INPUT__MASK				0x000f0000
+#define NV10_3D_RC_IN_RGB_B_INPUT__SHIFT			16
+#define NV10_3D_RC_IN_RGB_B_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV10_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV10_3D_RC_IN_RGB_B_INPUT_FOG				0x00030000
+#define NV10_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR			0x00040000
+#define NV10_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV10_3D_RC_IN_RGB_B_INPUT_TEXTURE0			0x00080000
+#define NV10_3D_RC_IN_RGB_B_INPUT_TEXTURE1			0x00090000
+#define NV10_3D_RC_IN_RGB_B_INPUT_TEXTURE2			0x000a0000
+#define NV10_3D_RC_IN_RGB_B_INPUT_TEXTURE3			0x000b0000
+#define NV10_3D_RC_IN_RGB_B_INPUT_SPARE0			0x000c0000
+#define NV10_3D_RC_IN_RGB_B_INPUT_SPARE1			0x000d0000
+#define NV10_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV10_3D_RC_IN_RGB_B_INPUT_E_TIMES_F			0x000f0000
+#define NV10_3D_RC_IN_RGB_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV10_3D_RC_IN_RGB_B_COMPONENT_USAGE__SHIFT		20
+#define NV10_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV10_3D_RC_IN_RGB_B_MAPPING__MASK			0x00e00000
+#define NV10_3D_RC_IN_RGB_B_MAPPING__SHIFT			21
+#define NV10_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV10_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV10_3D_RC_IN_RGB_A_INPUT__MASK				0x0f000000
+#define NV10_3D_RC_IN_RGB_A_INPUT__SHIFT			24
+#define NV10_3D_RC_IN_RGB_A_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_FOG				0x03000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR			0x04000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_TEXTURE0			0x08000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_TEXTURE1			0x09000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_TEXTURE2			0x0a000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_TEXTURE3			0x0b000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_SPARE0			0x0c000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_SPARE1			0x0d000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV10_3D_RC_IN_RGB_A_INPUT_E_TIMES_F			0x0f000000
+#define NV10_3D_RC_IN_RGB_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV10_3D_RC_IN_RGB_A_COMPONENT_USAGE__SHIFT		28
+#define NV10_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING__MASK			0xe0000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING__SHIFT			29
+#define NV10_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV10_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV10_3D_RC_COLOR(i0)				       (0x00000270 + 0x4*(i0))
+#define NV10_3D_RC_COLOR_B__MASK				0x000000ff
+#define NV10_3D_RC_COLOR_B__SHIFT				0
+#define NV10_3D_RC_COLOR_G__MASK				0x0000ff00
+#define NV10_3D_RC_COLOR_G__SHIFT				8
+#define NV10_3D_RC_COLOR_R__MASK				0x00ff0000
+#define NV10_3D_RC_COLOR_R__SHIFT				16
+#define NV10_3D_RC_COLOR_A__MASK				0xff000000
+#define NV10_3D_RC_COLOR_A__SHIFT				24
+
+#define NV10_3D_RC_OUT_ALPHA(i0)			       (0x00000278 + 0x4*(i0))
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT__MASK			0x0000000f
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT__SHIFT			0
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0		0x00000001
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1		0x00000002
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG			0x00000003
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR		0x00000004
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR		0x00000005
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0			0x00000008
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1			0x00000009
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2			0x0000000a
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3			0x0000000b
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0			0x0000000c
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1			0x0000000d
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV10_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F		0x0000000f
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT__MASK			0x000000f0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT__SHIFT			4
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0		0x00000010
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1		0x00000020
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG			0x00000030
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR		0x00000040
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR		0x00000050
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0			0x00000080
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1			0x00000090
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2			0x000000a0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3			0x000000b0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0			0x000000c0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1			0x000000d0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000000e0
+#define NV10_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F		0x000000f0
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT__MASK			0x00000f00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT__SHIFT			8
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG			0x00000300
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR		0x00000400
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0		0x00000800
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1		0x00000900
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2		0x00000a00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3		0x00000b00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F		0x00000f00
+#define NV10_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT			0x00001000
+#define NV10_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT			0x00002000
+#define NV10_3D_RC_OUT_ALPHA_MUX_SUM				0x00004000
+#define NV10_3D_RC_OUT_ALPHA_BIAS__MASK				0x00008000
+#define NV10_3D_RC_OUT_ALPHA_BIAS__SHIFT			15
+#define NV10_3D_RC_OUT_ALPHA_BIAS_NONE				0x00000000
+#define NV10_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF	0x00008000
+#define NV10_3D_RC_OUT_ALPHA_SCALE__MASK			0x00030000
+#define NV10_3D_RC_OUT_ALPHA_SCALE__SHIFT			16
+#define NV10_3D_RC_OUT_ALPHA_SCALE_NONE				0x00000000
+#define NV10_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO			0x00010000
+#define NV10_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR		0x00020000
+#define NV10_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF		0x00030000
+
+#define NV10_3D_RC_OUT_RGB(i0)				       (0x00000280 + 0x4*(i0))
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT__MASK			0x0000000f
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT__SHIFT			0
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0		0x00000001
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1		0x00000002
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_FOG			0x00000003
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR		0x00000004
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR		0x00000005
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0			0x00000008
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1			0x00000009
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE2			0x0000000a
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE3			0x0000000b
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0			0x0000000c
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1			0x0000000d
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV10_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F			0x0000000f
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT__MASK			0x000000f0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT__SHIFT			4
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0		0x00000010
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1		0x00000020
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_FOG			0x00000030
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR		0x00000040
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR		0x00000050
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0			0x00000080
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1			0x00000090
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE2			0x000000a0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE3			0x000000b0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0			0x000000c0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1			0x000000d0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000000e0
+#define NV10_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F			0x000000f0
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT__MASK			0x00000f00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT__SHIFT			8
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO			0x00000000
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_FOG			0x00000300
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR		0x00000400
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0			0x00000800
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1			0x00000900
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2			0x00000a00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3			0x00000b00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F			0x00000f00
+#define NV10_3D_RC_OUT_RGB_CD_DOT_PRODUCT			0x00001000
+#define NV10_3D_RC_OUT_RGB_AB_DOT_PRODUCT			0x00002000
+#define NV10_3D_RC_OUT_RGB_MUX_SUM				0x00004000
+#define NV10_3D_RC_OUT_RGB_BIAS__MASK				0x00008000
+#define NV10_3D_RC_OUT_RGB_BIAS__SHIFT				15
+#define NV10_3D_RC_OUT_RGB_BIAS_NONE				0x00000000
+#define NV10_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF	0x00008000
+#define NV10_3D_RC_OUT_RGB_SCALE__MASK				0x00030000
+#define NV10_3D_RC_OUT_RGB_SCALE__SHIFT				16
+#define NV10_3D_RC_OUT_RGB_SCALE_NONE				0x00000000
+#define NV10_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO			0x00010000
+#define NV10_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR			0x00020000
+#define NV10_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF		0x00030000
+#define NV10_3D_RC_OUT_RGB_OPERATION__MASK			0x38000000
+#define NV10_3D_RC_OUT_RGB_OPERATION__SHIFT			27
+
+#define NV10_3D_RC_FINAL0					0x00000288
+#define NV10_3D_RC_FINAL0_D_INPUT__MASK				0x0000000f
+#define NV10_3D_RC_FINAL0_D_INPUT__SHIFT			0
+#define NV10_3D_RC_FINAL0_D_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV10_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV10_3D_RC_FINAL0_D_INPUT_FOG				0x00000003
+#define NV10_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR			0x00000004
+#define NV10_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV10_3D_RC_FINAL0_D_INPUT_TEXTURE0			0x00000008
+#define NV10_3D_RC_FINAL0_D_INPUT_TEXTURE1			0x00000009
+#define NV10_3D_RC_FINAL0_D_INPUT_TEXTURE2			0x0000000a
+#define NV10_3D_RC_FINAL0_D_INPUT_TEXTURE3			0x0000000b
+#define NV10_3D_RC_FINAL0_D_INPUT_SPARE0			0x0000000c
+#define NV10_3D_RC_FINAL0_D_INPUT_SPARE1			0x0000000d
+#define NV10_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV10_3D_RC_FINAL0_D_INPUT_E_TIMES_F			0x0000000f
+#define NV10_3D_RC_FINAL0_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV10_3D_RC_FINAL0_D_COMPONENT_USAGE__SHIFT		4
+#define NV10_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV10_3D_RC_FINAL0_D_MAPPING__MASK			0x000000e0
+#define NV10_3D_RC_FINAL0_D_MAPPING__SHIFT			5
+#define NV10_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV10_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV10_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV10_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV10_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV10_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV10_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV10_3D_RC_FINAL0_C_INPUT__MASK				0x00000f00
+#define NV10_3D_RC_FINAL0_C_INPUT__SHIFT			8
+#define NV10_3D_RC_FINAL0_C_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_FINAL0_C_INPUT_FOG				0x00000300
+#define NV10_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR			0x00000400
+#define NV10_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_FINAL0_C_INPUT_TEXTURE0			0x00000800
+#define NV10_3D_RC_FINAL0_C_INPUT_TEXTURE1			0x00000900
+#define NV10_3D_RC_FINAL0_C_INPUT_TEXTURE2			0x00000a00
+#define NV10_3D_RC_FINAL0_C_INPUT_TEXTURE3			0x00000b00
+#define NV10_3D_RC_FINAL0_C_INPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_FINAL0_C_INPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_FINAL0_C_INPUT_E_TIMES_F			0x00000f00
+#define NV10_3D_RC_FINAL0_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV10_3D_RC_FINAL0_C_COMPONENT_USAGE__SHIFT		12
+#define NV10_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV10_3D_RC_FINAL0_C_MAPPING__MASK			0x0000e000
+#define NV10_3D_RC_FINAL0_C_MAPPING__SHIFT			13
+#define NV10_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV10_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV10_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV10_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV10_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV10_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV10_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV10_3D_RC_FINAL0_B_INPUT__MASK				0x000f0000
+#define NV10_3D_RC_FINAL0_B_INPUT__SHIFT			16
+#define NV10_3D_RC_FINAL0_B_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV10_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV10_3D_RC_FINAL0_B_INPUT_FOG				0x00030000
+#define NV10_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR			0x00040000
+#define NV10_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV10_3D_RC_FINAL0_B_INPUT_TEXTURE0			0x00080000
+#define NV10_3D_RC_FINAL0_B_INPUT_TEXTURE1			0x00090000
+#define NV10_3D_RC_FINAL0_B_INPUT_TEXTURE2			0x000a0000
+#define NV10_3D_RC_FINAL0_B_INPUT_TEXTURE3			0x000b0000
+#define NV10_3D_RC_FINAL0_B_INPUT_SPARE0			0x000c0000
+#define NV10_3D_RC_FINAL0_B_INPUT_SPARE1			0x000d0000
+#define NV10_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV10_3D_RC_FINAL0_B_INPUT_E_TIMES_F			0x000f0000
+#define NV10_3D_RC_FINAL0_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV10_3D_RC_FINAL0_B_COMPONENT_USAGE__SHIFT		20
+#define NV10_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV10_3D_RC_FINAL0_B_MAPPING__MASK			0x00e00000
+#define NV10_3D_RC_FINAL0_B_MAPPING__SHIFT			21
+#define NV10_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV10_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV10_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV10_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV10_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV10_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV10_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV10_3D_RC_FINAL0_A_INPUT__MASK				0x0f000000
+#define NV10_3D_RC_FINAL0_A_INPUT__SHIFT			24
+#define NV10_3D_RC_FINAL0_A_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV10_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV10_3D_RC_FINAL0_A_INPUT_FOG				0x03000000
+#define NV10_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR			0x04000000
+#define NV10_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV10_3D_RC_FINAL0_A_INPUT_TEXTURE0			0x08000000
+#define NV10_3D_RC_FINAL0_A_INPUT_TEXTURE1			0x09000000
+#define NV10_3D_RC_FINAL0_A_INPUT_TEXTURE2			0x0a000000
+#define NV10_3D_RC_FINAL0_A_INPUT_TEXTURE3			0x0b000000
+#define NV10_3D_RC_FINAL0_A_INPUT_SPARE0			0x0c000000
+#define NV10_3D_RC_FINAL0_A_INPUT_SPARE1			0x0d000000
+#define NV10_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV10_3D_RC_FINAL0_A_INPUT_E_TIMES_F			0x0f000000
+#define NV10_3D_RC_FINAL0_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV10_3D_RC_FINAL0_A_COMPONENT_USAGE__SHIFT		28
+#define NV10_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV10_3D_RC_FINAL0_A_MAPPING__MASK			0xe0000000
+#define NV10_3D_RC_FINAL0_A_MAPPING__SHIFT			29
+#define NV10_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV10_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV10_3D_RC_FINAL1					0x0000028c
+#define NV10_3D_RC_FINAL1_COLOR_SUM_CLAMP			0x00000080
+#define NV10_3D_RC_FINAL1_G_INPUT__MASK				0x00000f00
+#define NV10_3D_RC_FINAL1_G_INPUT__SHIFT			8
+#define NV10_3D_RC_FINAL1_G_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV10_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV10_3D_RC_FINAL1_G_INPUT_FOG				0x00000300
+#define NV10_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR			0x00000400
+#define NV10_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR		0x00000500
+#define NV10_3D_RC_FINAL1_G_INPUT_TEXTURE0			0x00000800
+#define NV10_3D_RC_FINAL1_G_INPUT_TEXTURE1			0x00000900
+#define NV10_3D_RC_FINAL1_G_INPUT_TEXTURE2			0x00000a00
+#define NV10_3D_RC_FINAL1_G_INPUT_TEXTURE3			0x00000b00
+#define NV10_3D_RC_FINAL1_G_INPUT_SPARE0			0x00000c00
+#define NV10_3D_RC_FINAL1_G_INPUT_SPARE1			0x00000d00
+#define NV10_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV10_3D_RC_FINAL1_G_INPUT_E_TIMES_F			0x00000f00
+#define NV10_3D_RC_FINAL1_G_COMPONENT_USAGE__MASK		0x00001000
+#define NV10_3D_RC_FINAL1_G_COMPONENT_USAGE__SHIFT		12
+#define NV10_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV10_3D_RC_FINAL1_G_MAPPING__MASK			0x0000e000
+#define NV10_3D_RC_FINAL1_G_MAPPING__SHIFT			13
+#define NV10_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV10_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV10_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV10_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV10_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV10_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV10_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV10_3D_RC_FINAL1_F_INPUT__MASK				0x000f0000
+#define NV10_3D_RC_FINAL1_F_INPUT__SHIFT			16
+#define NV10_3D_RC_FINAL1_F_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV10_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV10_3D_RC_FINAL1_F_INPUT_FOG				0x00030000
+#define NV10_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR			0x00040000
+#define NV10_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR		0x00050000
+#define NV10_3D_RC_FINAL1_F_INPUT_TEXTURE0			0x00080000
+#define NV10_3D_RC_FINAL1_F_INPUT_TEXTURE1			0x00090000
+#define NV10_3D_RC_FINAL1_F_INPUT_TEXTURE2			0x000a0000
+#define NV10_3D_RC_FINAL1_F_INPUT_TEXTURE3			0x000b0000
+#define NV10_3D_RC_FINAL1_F_INPUT_SPARE0			0x000c0000
+#define NV10_3D_RC_FINAL1_F_INPUT_SPARE1			0x000d0000
+#define NV10_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV10_3D_RC_FINAL1_F_INPUT_E_TIMES_F			0x000f0000
+#define NV10_3D_RC_FINAL1_F_COMPONENT_USAGE__MASK		0x00100000
+#define NV10_3D_RC_FINAL1_F_COMPONENT_USAGE__SHIFT		20
+#define NV10_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV10_3D_RC_FINAL1_F_MAPPING__MASK			0x00e00000
+#define NV10_3D_RC_FINAL1_F_MAPPING__SHIFT			21
+#define NV10_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV10_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV10_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV10_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV10_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV10_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV10_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV10_3D_RC_FINAL1_E_INPUT__MASK				0x0f000000
+#define NV10_3D_RC_FINAL1_E_INPUT__SHIFT			24
+#define NV10_3D_RC_FINAL1_E_INPUT_ZERO				0x00000000
+#define NV10_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV10_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV10_3D_RC_FINAL1_E_INPUT_FOG				0x03000000
+#define NV10_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR			0x04000000
+#define NV10_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR		0x05000000
+#define NV10_3D_RC_FINAL1_E_INPUT_TEXTURE0			0x08000000
+#define NV10_3D_RC_FINAL1_E_INPUT_TEXTURE1			0x09000000
+#define NV10_3D_RC_FINAL1_E_INPUT_TEXTURE2			0x0a000000
+#define NV10_3D_RC_FINAL1_E_INPUT_TEXTURE3			0x0b000000
+#define NV10_3D_RC_FINAL1_E_INPUT_SPARE0			0x0c000000
+#define NV10_3D_RC_FINAL1_E_INPUT_SPARE1			0x0d000000
+#define NV10_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV10_3D_RC_FINAL1_E_INPUT_E_TIMES_F			0x0f000000
+#define NV10_3D_RC_FINAL1_E_COMPONENT_USAGE__MASK		0x10000000
+#define NV10_3D_RC_FINAL1_E_COMPONENT_USAGE__SHIFT		28
+#define NV10_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB			0x00000000
+#define NV10_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV10_3D_RC_FINAL1_E_MAPPING__MASK			0xe0000000
+#define NV10_3D_RC_FINAL1_E_MAPPING__SHIFT			29
+#define NV10_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV10_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE		0xe0000000
+
+
+#define NV17_3D_DMA_HIERZ					0x000001b0
+
+#define NV17_3D_HIERZ_PITCH					0x00000d5c
+
+#define NV17_3D_HIERZ_OFFSET					0x00000d60
+
+#define NV17_3D_HIERZ_FILL_VALUE				0x00000d68
+
+#define NV17_3D_HIERZ_BUFFER_CLEAR				0x00000d6c
+
+#define NV17_3D_UNK0D74						0x00000d74
+
+#define NV17_3D_UNK0D84						0x00000d84
+
+
+#define NV17_3D_HIERZ_WINDOW					0x00001638
+
+
+#define NV17_3D_HIERZ_WINDOW_X					0x00001638
+
+#define NV17_3D_HIERZ_WINDOW_Y					0x0000163c
+
+#define NV17_3D_HIERZ_WINDOW_Z					0x00001640
+
+#define NV17_3D_HIERZ_WINDOW_W					0x00001644
+
+#define NV17_3D_HIERZ_ENABLE					0x00001658
+
+
+#define NV17_3D_UNK01AC						0x000001ac
+
+#define NV17_3D_UNK0258						0x00000258
+
+#define NV17_3D_UNK025C						0x0000025c
+
+#define NV10_3D_UNK0290						0x00000290
+
+#define NV17_3D_COLOR_MASK_ENABLE				0x000002bc
+
+#define NV10_3D_UNK03F0						0x000003f0
+
+#define NV10_3D_UNK03F4						0x000003f4
+
+#define NV17_3D_ZCLEAR_ENABLE					0x000003f8
+
+#define NV17_3D_ZCLEAR_VALUE					0x000003fc
+#define NV17_3D_ZCLEAR_VALUE_DEPTH__MASK			0xffffff00
+#define NV17_3D_ZCLEAR_VALUE_DEPTH__SHIFT			8
+#define NV17_3D_ZCLEAR_VALUE_SEQUENCE__MASK			0x000000ff
+#define NV17_3D_ZCLEAR_VALUE_SEQUENCE__SHIFT			0
+
+#define NV10_3D_POINT_SIZE					0x000003ec
+
+#define NV10_3D_POINT_PARAMETER(i0)			       (0x000006f8 + 0x4*(i0))
+#define NV10_3D_POINT_PARAMETER__ESIZE				0x00000004
+#define NV10_3D_POINT_PARAMETER__LEN				0x00000008
+
+#define NV11_3D_COLOR_LOGIC_OP					0x00000d40
+
+#define NV11_3D_COLOR_LOGIC_OP_ENABLE				0x00000d40
+
+#define NV11_3D_COLOR_LOGIC_OP_OP				0x00000d44
+#define NV11_3D_COLOR_LOGIC_OP_OP_CLEAR				0x00001500
+#define NV11_3D_COLOR_LOGIC_OP_OP_AND				0x00001501
+#define NV11_3D_COLOR_LOGIC_OP_OP_AND_REVERSE			0x00001502
+#define NV11_3D_COLOR_LOGIC_OP_OP_COPY				0x00001503
+#define NV11_3D_COLOR_LOGIC_OP_OP_AND_INVERTED			0x00001504
+#define NV11_3D_COLOR_LOGIC_OP_OP_NOOP				0x00001505
+#define NV11_3D_COLOR_LOGIC_OP_OP_XOR				0x00001506
+#define NV11_3D_COLOR_LOGIC_OP_OP_OR				0x00001507
+#define NV11_3D_COLOR_LOGIC_OP_OP_NOR				0x00001508
+#define NV11_3D_COLOR_LOGIC_OP_OP_EQUIV				0x00001509
+#define NV11_3D_COLOR_LOGIC_OP_OP_INVERT			0x0000150a
+#define NV11_3D_COLOR_LOGIC_OP_OP_OR_REVERSE			0x0000150b
+#define NV11_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED			0x0000150c
+#define NV11_3D_COLOR_LOGIC_OP_OP_OR_INVERTED			0x0000150d
+#define NV11_3D_COLOR_LOGIC_OP_OP_NAND				0x0000150e
+#define NV11_3D_COLOR_LOGIC_OP_OP_SET				0x0000150f
+
+
+#endif /* NV10_3D_XML */
diff --git a/src/mesa/drivers/dri/nouveau/nv10_context.c b/src/mesa/drivers/dri/nouveau/nv10_context.c
index de2c93ec81..8074b4bb47 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_context.c
@@ -29,7 +29,8 @@
 #include "nouveau_context.h"
 #include "nouveau_fbo.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv10_3d.xml.h"
 #include "nv04_driver.h"
 #include "nv10_driver.h"
 
@@ -157,9 +158,9 @@ nv17_zclear(struct gl_context *ctx, GLbitfield *buffers)
 		nfb->base._DepthBuffer->Wrapped)->surface;
 
 	/* Clear the hierarchical depth buffer */
-	BEGIN_RING(chan, celsius, NV17TCL_LMA_DEPTH_FILL_VALUE, 1);
+	BEGIN_RING(chan, celsius, NV17_3D_HIERZ_FILL_VALUE, 1);
 	OUT_RING(chan, pack_zs_f(s->format, ctx->Depth.Clear, 0));
-	BEGIN_RING(chan, celsius, NV17TCL_LMA_DEPTH_BUFFER_CLEAR, 1);
+	BEGIN_RING(chan, celsius, NV17_3D_HIERZ_BUFFER_CLEAR, 1);
 	OUT_RING(chan, 1);
 
 	/* Mark the depth buffer as cleared */
@@ -201,33 +202,33 @@ nv10_hwctx_init(struct gl_context *ctx)
 	struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw;
 	int i;
 
-	BEGIN_RING(chan, celsius, NV10TCL_DMA_NOTIFY, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_DMA_NOTIFY, 1);
 	OUT_RING(chan, hw->ntfy->handle);
 
-	BEGIN_RING(chan, celsius, NV10TCL_DMA_IN_MEMORY0, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_DMA_TEXTURE0, 3);
 	OUT_RING(chan, chan->vram->handle);
 	OUT_RING(chan, chan->gart->handle);
 	OUT_RING(chan, chan->gart->handle);
-	BEGIN_RING(chan, celsius, NV10TCL_DMA_IN_MEMORY2, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_DMA_COLOR, 2);
 	OUT_RING(chan, chan->vram->handle);
 	OUT_RING(chan, chan->vram->handle);
 
-	BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+	BEGIN_RING(chan, celsius, NV04_GRAPH_NOP, 1);
 	OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_RT_HORIZ, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_RT_HORIZ, 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_HORIZ(0), 1);
 	OUT_RING(chan, 0x7ff << 16 | 0x800);
-	BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_VERT(0), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_VERT(0), 1);
 	OUT_RING(chan, 0x7ff << 16 | 0x800);
 
 	for (i = 1; i < 8; i++) {
-		BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 		OUT_RING(chan, 0);
-		BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_VERT(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_VERT(i), 1);
 		OUT_RING(chan, 0);
 	}
 
@@ -236,18 +237,18 @@ nv10_hwctx_init(struct gl_context *ctx)
 	BEGIN_RING(chan, celsius, 0x3f4, 1);
 	OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+	BEGIN_RING(chan, celsius,  NV04_GRAPH_NOP, 1);
 	OUT_RING(chan, 0);
 
 	if (context_chipset(ctx) >= 0x17) {
-		BEGIN_RING(chan, celsius, NV17TCL_DMA_IN_MEMORY4, 2);
+		BEGIN_RING(chan, celsius, NV17_3D_UNK01AC, 2);
 		OUT_RING(chan, chan->vram->handle);
 		OUT_RING(chan, chan->vram->handle);
 
 		BEGIN_RING(chan, celsius, 0xd84, 1);
 		OUT_RING(chan, 0x3);
 
-		BEGIN_RING(chan, celsius, NV17TCL_COLOR_MASK_ENABLE, 1);
+		BEGIN_RING(chan, celsius, NV17_3D_COLOR_MASK_ENABLE, 1);
 		OUT_RING(chan, 1);
 	}
 
@@ -257,41 +258,41 @@ nv10_hwctx_init(struct gl_context *ctx)
 		OUT_RING(chan, 1);
 		OUT_RING(chan, 2);
 
-		BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+		BEGIN_RING(chan, celsius, NV04_GRAPH_NOP, 1);
 		OUT_RING(chan, 0);
 	}
 
-	BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+	BEGIN_RING(chan, celsius,  NV04_GRAPH_NOP, 1);
 	OUT_RING(chan, 0);
 
 	/* Set state */
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_ALPHA_FUNC_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_FUNC, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_ALPHA_FUNC_FUNC, 2);
 	OUT_RING(chan, 0x207);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(0), 2);
+	BEGIN_RING(chan, celsius, NV10_3D_TEX_ENABLE(0), 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_FUNC_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_DITHER_ENABLE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_DITHER_ENABLE, 2);
 	OUT_RING(chan, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LINE_SMOOTH_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_WEIGHT_ENABLE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_WEIGHT_ENABLE, 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_SRC, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_FUNC_SRC, 4);
 	OUT_RING(chan, 1);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0x8006);
-	BEGIN_RING(chan, celsius, NV10TCL_STENCIL_MASK, 8);
+	BEGIN_RING(chan, celsius, NV10_3D_STENCIL_MASK, 8);
 	OUT_RING(chan, 0xff);
 	OUT_RING(chan, 0x207);
 	OUT_RING(chan, 0);
@@ -300,105 +301,105 @@ nv10_hwctx_init(struct gl_context *ctx)
 	OUT_RING(chan, 0x1e00);
 	OUT_RING(chan, 0x1e00);
 	OUT_RING(chan, 0x1d01);
-	BEGIN_RING(chan, celsius, NV10TCL_NORMALIZE_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_NORMALIZE_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_ENABLE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_ENABLE, 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_LIGHT_MODEL, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LIGHT_MODEL, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_SEPARATE_SPECULAR_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_SEPARATE_SPECULAR_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_ENABLED_LIGHTS, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_ENABLED_LIGHTS, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_OFFSET_POINT_ENABLE, 3);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_FUNC, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_FUNC, 1);
 	OUT_RING(chan, 0x201);
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_WRITE_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_TEST_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_FACTOR, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_OFFSET_FACTOR, 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_POINT_SIZE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_POINT_SIZE, 1);
 	OUT_RING(chan, 8);
-	BEGIN_RING(chan, celsius, NV10TCL_POINT_PARAMETERS_ENABLE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_POINT_PARAMETERS_ENABLE, 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_LINE_WIDTH, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LINE_WIDTH, 1);
 	OUT_RING(chan, 8);
-	BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LINE_SMOOTH_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_MODE_FRONT, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_MODE_FRONT, 2);
 	OUT_RING(chan, 0x1b02);
 	OUT_RING(chan, 0x1b02);
-	BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_CULL_FACE, 2);
 	OUT_RING(chan, 0x405);
 	OUT_RING(chan, 0x901);
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_SMOOTH_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_SMOOTH_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_CULL_FACE_ENABLE, 1);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_TX_GEN_MODE_S(0), 8);
+	BEGIN_RING(chan, celsius, NV10_3D_TEX_GEN_MODE(0, 0), 8);
 	for (i = 0; i < 8; i++)
 		OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_TX_MATRIX_ENABLE(0), 2);
+	BEGIN_RING(chan, celsius, NV10_3D_TEX_MATRIX_ENABLE(0), 2);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_EQUATION_CONSTANT, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_COEFF(0), 3);
 	OUT_RING(chan, 0x3fc00000);	/* -1.50 */
 	OUT_RING(chan, 0xbdb8aa0a);	/* -0.09 */
 	OUT_RING(chan, 0);		/*  0.00 */
 
-	BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+	BEGIN_RING(chan, celsius,  NV04_GRAPH_NOP, 1);
 	OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_MODE, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_MODE, 2);
 	OUT_RING(chan, 0x802);
 	OUT_RING(chan, 2);
 	/* for some reason VIEW_MATRIX_ENABLE need to be 6 instead of 4 when
 	 * using texturing, except when using the texture matrix
 	 */
-	BEGIN_RING(chan, celsius, NV10TCL_VIEW_MATRIX_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEW_MATRIX_ENABLE, 1);
 	OUT_RING(chan, 6);
-	BEGIN_RING(chan, celsius, NV10TCL_COLOR_MASK, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_COLOR_MASK, 1);
 	OUT_RING(chan, 0x01010101);
 
 	/* Set vertex component */
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_COL_4F_R, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_COL_4F_R, 4);
 	OUT_RINGf(chan, 1.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 1.0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_COL2_3F_R, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_COL2_3F_R, 3);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_NOR_3F_X, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_NOR_3F_X, 3);
 	OUT_RING(chan, 0);
 	OUT_RING(chan, 0);
 	OUT_RINGf(chan, 1.0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_TX0_4F_S, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_TX0_4F_S, 4);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 1.0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_TX1_4F_S, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_TX1_4F_S, 4);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 1.0);
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_FOG_1F, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VERTEX_FOG_1F, 1);
 	OUT_RINGf(chan, 0.0);
-	BEGIN_RING(chan, celsius, NV10TCL_EDGEFLAG_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_EDGEFLAG_ENABLE, 1);
 	OUT_RING(chan, 1);
 
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_RANGE_NEAR, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_RANGE_NEAR, 2);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 16777216.0);
 
@@ -456,11 +457,11 @@ nv10_context_create(struct nouveau_screen *screen, const struct gl_config *visua
 
 	/* 3D engine. */
 	if (context_chipset(ctx) >= 0x17)
-		celsius_class = NV17TCL;
+		celsius_class = NV17_3D;
 	else if (context_chipset(ctx) >= 0x11)
-		celsius_class = NV11TCL;
+		celsius_class = NV11_3D;
 	else
-		celsius_class = NV10TCL;
+		celsius_class = NV10_3D;
 
 	ret = nouveau_grobj_alloc(context_chan(ctx), 0xbeef0001, celsius_class,
 				  &nctx->hw.eng3d);
diff --git a/src/mesa/drivers/dri/nouveau/nv10_render.c b/src/mesa/drivers/dri/nouveau/nv10_render.c
index 7115739b5a..20fb447842 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_render.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_render.c
@@ -26,7 +26,7 @@
 
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
-#include "nouveau_class.h"
+#include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
 #define NUM_VERTEX_ATTRS 8
@@ -39,37 +39,37 @@ nv10_emit_material(struct gl_context *ctx, struct nouveau_array *a,
 static struct nouveau_attr_info nv10_vertex_attrs[VERT_ATTRIB_MAX] = {
 	[VERT_ATTRIB_POS] = {
 		.vbo_index = 0,
-		.imm_method = NV10TCL_VERTEX_POS_4F_X,
+		.imm_method = NV10_3D_VERTEX_POS_4F_X,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_COLOR0] = {
 		.vbo_index = 1,
-		.imm_method = NV10TCL_VERTEX_COL_4F_R,
+		.imm_method = NV10_3D_VERTEX_COL_4F_R,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_COLOR1] = {
 		.vbo_index = 2,
-		.imm_method = NV10TCL_VERTEX_COL2_3F_R,
+		.imm_method = NV10_3D_VERTEX_COL2_3F_R,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_TEX0] = {
 		.vbo_index = 3,
-		.imm_method = NV10TCL_VERTEX_TX0_4F_S,
+		.imm_method = NV10_3D_VERTEX_TX0_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX1] = {
 		.vbo_index = 4,
-		.imm_method = NV10TCL_VERTEX_TX1_4F_S,
+		.imm_method = NV10_3D_VERTEX_TX1_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_NORMAL] = {
 		.vbo_index = 5,
-		.imm_method = NV10TCL_VERTEX_NOR_3F_X,
+		.imm_method = NV10_3D_VERTEX_NOR_3F_X,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_FOG] = {
 		.vbo_index = 7,
-		.imm_method = NV10TCL_VERTEX_FOG_1F,
+		.imm_method = NV10_3D_VERTEX_FOG_1F,
 		.imm_fields = 1,
 	},
 	[VERT_ATTRIB_GENERIC0] = {
@@ -94,12 +94,12 @@ get_hw_format(int type)
 {
 	switch (type) {
 	case GL_FLOAT:
-		return NV10TCL_VTXFMT_TYPE_FLOAT;
+		return NV10_3D_VTXBUF_FMT_TYPE_V32_FLOAT;
 	case GL_SHORT:
 	case GL_UNSIGNED_SHORT:
-		return NV10TCL_VTXFMT_TYPE_SHORT;
+		return NV10_3D_VTXBUF_FMT_TYPE_V16_SNORM;
 	case GL_UNSIGNED_BYTE:
-		return NV10TCL_VTXFMT_TYPE_BYTE_RGBA;
+		return NV10_3D_VTXBUF_FMT_TYPE_B8G8R8A8_UNORM;
 	default:
 		assert(0);
 	}
@@ -122,13 +122,13 @@ nv10_render_set_format(struct gl_context *ctx)
 				get_hw_format(a->type);
 
 			if (attr == VERT_ATTRIB_POS && a->fields == 4)
-				hw_format |= NV10TCL_VTXFMT_POS_HOMOGENEOUS;
+				hw_format |= NV10_3D_VTXBUF_FMT_HOMOGENEOUS;
 		} else {
 			/* Unused attribute. */
-			hw_format = NV10TCL_VTXFMT_TYPE_FLOAT;
+			hw_format = NV10_3D_VTXBUF_FMT_TYPE_V32_FLOAT;
 		}
 
-		BEGIN_RING(chan, celsius, NV10TCL_VTXFMT(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_VTXBUF_FMT(i), 1);
 		OUT_RING(chan, hw_format);
 	}
 }
@@ -145,7 +145,7 @@ nv10_render_bind_vertices(struct gl_context *ctx)
 		struct nouveau_array *a = &render->attrs[attr];
 
 		nouveau_bo_markl(bctx, celsius,
-				 NV10TCL_VTXBUF_ADDRESS(i),
+				 NV10_3D_VTXBUF_OFFSET(i),
 				 a->bo, a->offset,
 				 NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 	}
@@ -156,33 +156,33 @@ nv10_render_bind_vertices(struct gl_context *ctx)
 	struct nouveau_grobj *celsius = context_eng3d(ctx)
 
 #define BATCH_VALIDATE()						\
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_ARRAY_VALIDATE, 1);	\
+	BEGIN_RING(chan, celsius, NV10_3D_VTXBUF_VALIDATE, 1);	\
 	OUT_RING(chan, 0)
 
 #define BATCH_BEGIN(prim)						\
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);	\
+	BEGIN_RING(chan, celsius, NV10_3D_VTXBUF_BEGIN_END, 1);	\
 	OUT_RING(chan, prim)
 #define BATCH_END()							\
-	BEGIN_RING(chan, celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1);	\
+	BEGIN_RING(chan, celsius, NV10_3D_VTXBUF_BEGIN_END, 1);	\
 	OUT_RING(chan, 0)
 
 #define MAX_PACKET 0x400
 
 #define MAX_OUT_L 0x100
 #define BATCH_PACKET_L(n)						\
-	BEGIN_RING_NI(chan, celsius, NV10TCL_VERTEX_BUFFER_DRAW_ARRAYS, n)
+	BEGIN_RING_NI(chan, celsius, NV10_3D_VTXBUF_BATCH, n)
 #define BATCH_OUT_L(i, n)			\
 	OUT_RING(chan, ((n) - 1) << 24 | (i))
 
 #define MAX_OUT_I16 0x2
 #define BATCH_PACKET_I16(n)						\
-	BEGIN_RING_NI(chan, celsius, NV10TCL_VB_ELEMENT_U16, n)
+	BEGIN_RING_NI(chan, celsius, NV10_3D_VTXBUF_ELEMENT_U16, n)
 #define BATCH_OUT_I16(i0, i1)			\
 	OUT_RING(chan, (i1) << 16 | (i0))
 
 #define MAX_OUT_I32 0x1
 #define BATCH_PACKET_I32(n)						\
-	BEGIN_RING_NI(chan, celsius, NV10TCL_VB_ELEMENT_U32, n)
+	BEGIN_RING_NI(chan, celsius, NV10_3D_VTXBUF_ELEMENT_U32, n)
 #define BATCH_OUT_I32(i)			\
 	OUT_RING(chan, i)
 
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
index 0fda9faf49..0505547421 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_fb.c
@@ -27,8 +27,9 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_fbo.h"
-#include "nouveau_class.h"
 #include "nouveau_util.h"
+#include "nv_object.xml.h"
+#include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
 static inline unsigned
@@ -36,15 +37,15 @@ get_rt_format(gl_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
-		return 0x05;
+		return NV10_3D_RT_FORMAT_COLOR_X8R8G8B8;
 	case MESA_FORMAT_ARGB8888:
-		return 0x08;
+		return NV10_3D_RT_FORMAT_COLOR_A8R8G8B8;
 	case MESA_FORMAT_RGB565:
-		return 0x03;
+		return NV10_3D_RT_FORMAT_COLOR_R5G6B5;
 	case MESA_FORMAT_Z16:
-		return 0x10;
+		return NV10_3D_RT_FORMAT_DEPTH_Z16;
 	case MESA_FORMAT_Z24_S8:
-		return 0x0;
+		return NV10_3D_RT_FORMAT_DEPTH_Z24S8;
 	default:
 		assert(0);
 	}
@@ -68,20 +69,20 @@ setup_hierz_buffer(struct gl_context *ctx)
 				    0, NOUVEAU_BO_TILE_ZETA, &nfb->hierz.bo);
 	}
 
-	nouveau_bo_markl(bctx, celsius, NV17TCL_LMA_DEPTH_BUFFER_OFFSET,
+	nouveau_bo_markl(bctx, celsius, NV17_3D_HIERZ_OFFSET,
 			 nfb->hierz.bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 
 	WAIT_RING(chan, 9);
-	BEGIN_RING(chan, celsius, NV17TCL_LMA_DEPTH_WINDOW_X, 4);
+	BEGIN_RING(chan, celsius, NV17_3D_HIERZ_WINDOW_X, 4);
 	OUT_RINGf(chan, - 1792);
 	OUT_RINGf(chan, - 2304 + fb->Height);
 	OUT_RINGf(chan, fb->_DepthMaxF / 2);
 	OUT_RINGf(chan, 0);
 
-	BEGIN_RING(chan, celsius, NV17TCL_LMA_DEPTH_BUFFER_PITCH, 1);
+	BEGIN_RING(chan, celsius, NV17_3D_HIERZ_PITCH, 1);
 	OUT_RING(chan, pitch);
 
-	BEGIN_RING(chan, celsius, NV17TCL_LMA_DEPTH_ENABLE, 1);
+	BEGIN_RING(chan, celsius, NV17_3D_HIERZ_ENABLE, 1);
 	OUT_RING(chan, 1);
 }
 
@@ -93,7 +94,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 	struct nouveau_bo_context *bctx = context_bctx(ctx, FRAMEBUFFER);
 	struct gl_framebuffer *fb = ctx->DrawBuffer;
 	struct nouveau_surface *s;
-	unsigned rt_format = NV10TCL_RT_FORMAT_TYPE_LINEAR;
+	unsigned rt_format = NV10_3D_RT_FORMAT_TYPE_LINEAR;
 	unsigned rt_pitch = 0, zeta_pitch = 0;
 	unsigned bo_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
 
@@ -106,7 +107,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 		int i;
 
 		for (i = 0; i < 6; i++) {
-			BEGIN_RING(chan, celsius, NV10TCL_NOP, 1);
+			BEGIN_RING(chan, celsius, NV04_GRAPH_NOP, 1);
 			OUT_RING(chan, 0);
 		}
 	}
@@ -119,7 +120,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 		rt_format |= get_rt_format(s->format);
 		zeta_pitch = rt_pitch = s->pitch;
 
-		nouveau_bo_markl(bctx, celsius, NV10TCL_COLOR_OFFSET,
+		nouveau_bo_markl(bctx, celsius, NV10_3D_COLOR_OFFSET,
 				 s->bo, 0, bo_flags);
 	}
 
@@ -131,7 +132,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 		rt_format |= get_rt_format(s->format);
 		zeta_pitch = s->pitch;
 
-		nouveau_bo_markl(bctx, celsius, NV10TCL_ZETA_OFFSET,
+		nouveau_bo_markl(bctx, celsius, NV10_3D_ZETA_OFFSET,
 				 s->bo, 0, bo_flags);
 
 		if (context_chipset(ctx) >= 0x17) {
@@ -140,7 +141,7 @@ nv10_emit_framebuffer(struct gl_context *ctx, int emit)
 		}
 	}
 
-	BEGIN_RING(chan, celsius, NV10TCL_RT_FORMAT, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_RT_FORMAT, 2);
 	OUT_RING(chan, rt_format);
 	OUT_RING(chan, zeta_pitch << 16 | rt_pitch);
 
@@ -162,7 +163,7 @@ nv10_emit_scissor(struct gl_context *ctx, int emit)
 
 	get_scissors(ctx->DrawBuffer, &x, &y, &w, &h);
 
-	BEGIN_RING(chan, celsius, NV10TCL_RT_HORIZ, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_RT_HORIZ, 2);
 	OUT_RING(chan, w << 16 | x);
 	OUT_RING(chan, h << 16 | y);
 }
@@ -182,12 +183,12 @@ nv10_emit_viewport(struct gl_context *ctx, int emit)
 	if (nv10_use_viewport_zclear(ctx))
 		a[2] = nv10_transform_depth(ctx, (vp->Far + vp->Near) / 2);
 
-	BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_TRANSLATE_X, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_TRANSLATE_X, 4);
 	OUT_RINGp(chan, a, 4);
 
-	BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_HORIZ(0), 1);
 	OUT_RING(chan, (fb->Width - 1) << 16 | 0x08000800);
-	BEGIN_RING(chan, celsius, NV10TCL_VIEWPORT_CLIP_VERT(0), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_VIEWPORT_CLIP_VERT(0), 1);
 	OUT_RING(chan, (fb->Height - 1) << 16 | 0x08000800);
 
 	context_dirty(ctx, PROJECTION);
@@ -203,12 +204,12 @@ nv10_emit_zclear(struct gl_context *ctx, int emit)
 		to_nouveau_framebuffer(ctx->DrawBuffer);
 
 	if (nfb->hierz.bo) {
-		BEGIN_RING(chan, celsius, NV17TCL_ZCLEAR_ENABLE, 2);
-		OUT_RING(chan, nctx->hierz.clear_blocked ? 0 : 1);
+		BEGIN_RING(chan, celsius, NV17_3D_ZCLEAR_ENABLE, 2);
+		OUT_RINGb(chan, !nctx->hierz.clear_blocked);
 		OUT_RING(chan, nfb->hierz.clear_value |
 			 (nctx->hierz.clear_seq & 0xff));
 	} else {
-		BEGIN_RING(chan, celsius, NV10TCL_DEPTH_RANGE_NEAR, 2);
+		BEGIN_RING(chan, celsius, NV10_3D_DEPTH_RANGE_NEAR, 2);
 		OUT_RINGf(chan, nv10_transform_depth(ctx, 0));
 		OUT_RINGf(chan, nv10_transform_depth(ctx, 1));
 		context_dirty(ctx, VIEWPORT);
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
index 5138c36df7..1adc86086c 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_frag.c
@@ -27,7 +27,7 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nv10_3d.xml.h"
 #include "nouveau_util.h"
 #include "nv10_driver.h"
 #include "nv20_driver.h"
@@ -41,24 +41,24 @@
 #define RC_IN_SHIFT_G	40
 
 #define RC_IN_SOURCE(source)				\
-	((uint64_t)NV10TCL_RC_IN_RGB_D_INPUT_##source)
+	((uint64_t)NV10_3D_RC_IN_RGB_D_INPUT_##source)
 #define RC_IN_USAGE(usage)					\
-	((uint64_t)NV10TCL_RC_IN_RGB_D_COMPONENT_USAGE_##usage)
+	((uint64_t)NV10_3D_RC_IN_RGB_D_COMPONENT_USAGE_##usage)
 #define RC_IN_MAPPING(mapping)					\
-	((uint64_t)NV10TCL_RC_IN_RGB_D_MAPPING_##mapping)
+	((uint64_t)NV10_3D_RC_IN_RGB_D_MAPPING_##mapping)
 
-#define RC_OUT_BIAS	NV10TCL_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF
-#define RC_OUT_SCALE_1	NV10TCL_RC_OUT_RGB_SCALE_NONE
-#define RC_OUT_SCALE_2	NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_TWO
-#define RC_OUT_SCALE_4	NV10TCL_RC_OUT_RGB_SCALE_SCALE_BY_FOUR
+#define RC_OUT_BIAS	NV10_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF
+#define RC_OUT_SCALE_1	NV10_3D_RC_OUT_RGB_SCALE_NONE
+#define RC_OUT_SCALE_2	NV10_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO
+#define RC_OUT_SCALE_4	NV10_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR
 
 /* Make the combiner do: spare0_i = A_i * B_i */
-#define RC_OUT_AB	NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0
+#define RC_OUT_AB	NV10_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0
 /* spare0_i = dot3(A, B) */
-#define RC_OUT_DOT_AB	(NV10TCL_RC_OUT_RGB_AB_OUTPUT_SPARE0 |	\
-			 NV10TCL_RC_OUT_RGB_AB_DOT_PRODUCT)
+#define RC_OUT_DOT_AB	(NV10_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0 |	\
+			 NV10_3D_RC_OUT_RGB_AB_DOT_PRODUCT)
 /* spare0_i = A_i * B_i + C_i * D_i */
-#define RC_OUT_SUM	NV10TCL_RC_OUT_RGB_SUM_OUTPUT_SPARE0
+#define RC_OUT_SUM	NV10_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0
 
 struct combiner_state {
 	struct gl_context *ctx;
@@ -383,15 +383,15 @@ nv10_emit_tex_env(struct gl_context *ctx, int emit)
 			c_out |= 0x3 << 27;
 	}
 
-	BEGIN_RING(chan, celsius, NV10TCL_RC_IN_ALPHA(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_IN_ALPHA(i), 1);
 	OUT_RING(chan, a_in);
-	BEGIN_RING(chan, celsius, NV10TCL_RC_IN_RGB(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_IN_RGB(i), 1);
 	OUT_RING(chan, c_in);
-	BEGIN_RING(chan, celsius, NV10TCL_RC_COLOR(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_COLOR(i), 1);
 	OUT_RING(chan, k);
-	BEGIN_RING(chan, celsius, NV10TCL_RC_OUT_ALPHA(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_OUT_ALPHA(i), 1);
 	OUT_RING(chan, a_out);
-	BEGIN_RING(chan, celsius, NV10TCL_RC_OUT_RGB(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_OUT_RGB(i), 1);
 	OUT_RING(chan, c_out);
 
 	context_dirty(ctx, FRAG);
@@ -407,7 +407,7 @@ nv10_emit_frag(struct gl_context *ctx, int emit)
 
 	nv10_get_final_combiner(ctx, &in, &n);
 
-	BEGIN_RING(chan, celsius, NV10TCL_RC_FINAL0, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_RC_FINAL0, 2);
 	OUT_RING(chan, in);
 	OUT_RING(chan, in >> 32);
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c b/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c
index 4e49b0278c..3f80790483 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_polygon.c
@@ -27,7 +27,8 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nouveau_util.h"
+#include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
 void
@@ -37,13 +38,13 @@ nv10_emit_cull_face(struct gl_context *ctx, int emit)
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 	GLenum mode = ctx->Polygon.CullFaceMode;
 
-	BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE_ENABLE, 1);
-	OUT_RING(chan, ctx->Polygon.CullFlag ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_CULL_FACE_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Polygon.CullFlag);
 
-	BEGIN_RING(chan, celsius, NV10TCL_CULL_FACE, 1);
-	OUT_RING(chan, (mode == GL_FRONT ? NV10TCL_CULL_FACE_FRONT :
-			mode == GL_BACK ? NV10TCL_CULL_FACE_BACK :
-			NV10TCL_CULL_FACE_FRONT_AND_BACK));
+	BEGIN_RING(chan, celsius, NV10_3D_CULL_FACE, 1);
+	OUT_RING(chan, (mode == GL_FRONT ? NV10_3D_CULL_FACE_FRONT :
+			mode == GL_BACK ? NV10_3D_CULL_FACE_BACK :
+			NV10_3D_CULL_FACE_FRONT_AND_BACK));
 }
 
 void
@@ -52,9 +53,9 @@ nv10_emit_front_face(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_FRONT_FACE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_FRONT_FACE, 1);
 	OUT_RING(chan, ctx->Polygon.FrontFace == GL_CW ?
-		 NV10TCL_FRONT_FACE_CW : NV10TCL_FRONT_FACE_CCW);
+		 NV10_3D_FRONT_FACE_CW : NV10_3D_FRONT_FACE_CCW);
 }
 
 void
@@ -65,11 +66,11 @@ nv10_emit_line_mode(struct gl_context *ctx, int emit)
 	GLboolean smooth = ctx->Line.SmoothFlag &&
 		ctx->Hint.LineSmooth == GL_NICEST;
 
-	BEGIN_RING(chan, celsius, NV10TCL_LINE_WIDTH, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LINE_WIDTH, 1);
 	OUT_RING(chan, MAX2(smooth ? 0 : 1,
 			    ctx->Line.Width) * 8);
-	BEGIN_RING(chan, celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1);
-	OUT_RING(chan, smooth ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_LINE_SMOOTH_ENABLE, 1);
+	OUT_RINGb(chan, smooth);
 }
 
 void
@@ -83,11 +84,11 @@ nv10_emit_point_mode(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_POINT_SIZE, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_POINT_SIZE, 1);
 	OUT_RING(chan, (uint32_t)(ctx->Point.Size * 8));
 
-	BEGIN_RING(chan, celsius, NV10TCL_POINT_SMOOTH_ENABLE, 1);
-	OUT_RING(chan, ctx->Point.SmoothFlag ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_POINT_SMOOTH_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Point.SmoothFlag);
 }
 
 void
@@ -96,12 +97,12 @@ nv10_emit_polygon_mode(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_MODE_FRONT, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_MODE_FRONT, 2);
 	OUT_RING(chan, nvgl_polygon_mode(ctx->Polygon.FrontMode));
 	OUT_RING(chan, nvgl_polygon_mode(ctx->Polygon.BackMode));
 
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_SMOOTH_ENABLE, 1);
-	OUT_RING(chan, ctx->Polygon.SmoothFlag ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_SMOOTH_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Polygon.SmoothFlag);
 }
 
 void
@@ -110,12 +111,12 @@ nv10_emit_polygon_offset(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
-	OUT_RING(chan, ctx->Polygon.OffsetPoint ? 1 : 0);
-	OUT_RING(chan, ctx->Polygon.OffsetLine ? 1 : 0);
-	OUT_RING(chan, ctx->Polygon.OffsetFill ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_OFFSET_POINT_ENABLE, 3);
+	OUT_RINGb(chan, ctx->Polygon.OffsetPoint);
+	OUT_RINGb(chan, ctx->Polygon.OffsetLine);
+	OUT_RINGb(chan, ctx->Polygon.OffsetFill);
 
-	BEGIN_RING(chan, celsius, NV10TCL_POLYGON_OFFSET_FACTOR, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_POLYGON_OFFSET_FACTOR, 2);
 	OUT_RINGf(chan, ctx->Polygon.OffsetFactor);
 	OUT_RINGf(chan, ctx->Polygon.OffsetUnits);
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
index 99609844a1..bb1084ed11 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_raster.c
@@ -27,7 +27,8 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nouveau_util.h"
+#include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
 void
@@ -36,10 +37,10 @@ nv10_emit_alpha_func(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1);
-	OUT_RING(chan, ctx->Color.AlphaEnabled ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_ALPHA_FUNC_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Color.AlphaEnabled);
 
-	BEGIN_RING(chan, celsius, NV10TCL_ALPHA_FUNC_FUNC, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_ALPHA_FUNC_FUNC, 2);
 	OUT_RING(chan, nvgl_comparison_op(ctx->Color.AlphaFunc));
 	OUT_RING(chan, FLOAT_TO_UBYTE(ctx->Color.AlphaRef));
 }
@@ -50,7 +51,7 @@ nv10_emit_blend_color(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_COLOR, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_COLOR, 1);
 	OUT_RING(chan, FLOAT_TO_UBYTE(ctx->Color.BlendColor[3]) << 24 |
 		 FLOAT_TO_UBYTE(ctx->Color.BlendColor[0]) << 16 |
 		 FLOAT_TO_UBYTE(ctx->Color.BlendColor[1]) << 8 |
@@ -63,10 +64,10 @@ nv10_emit_blend_equation(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_ENABLE, 1);
-	OUT_RING(chan, ctx->Color.BlendEnabled ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_FUNC_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Color.BlendEnabled);
 
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_EQUATION, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_EQUATION, 1);
 	OUT_RING(chan, nvgl_blend_eqn(ctx->Color.BlendEquationRGB));
 }
 
@@ -76,7 +77,7 @@ nv10_emit_blend_func(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_BLEND_FUNC_SRC, 2);
+	BEGIN_RING(chan, celsius, NV10_3D_BLEND_FUNC_SRC, 2);
 	OUT_RING(chan, nvgl_blend_func(ctx->Color.BlendSrcRGB));
 	OUT_RING(chan, nvgl_blend_func(ctx->Color.BlendDstRGB));
 }
@@ -87,7 +88,7 @@ nv10_emit_color_mask(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_COLOR_MASK, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_COLOR_MASK, 1);
 	OUT_RING(chan, ((ctx->Color.ColorMask[0][3] ? 1 << 24 : 0) |
 			(ctx->Color.ColorMask[0][0] ? 1 << 16 : 0) |
 			(ctx->Color.ColorMask[0][1] ? 1 << 8 : 0) |
@@ -100,11 +101,11 @@ nv10_emit_depth(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_TEST_ENABLE, 1);
-	OUT_RING(chan, ctx->Depth.Test ? 1 : 0);
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1);
-	OUT_RING(chan, ctx->Depth.Mask ? 1 : 0);
-	BEGIN_RING(chan, celsius, NV10TCL_DEPTH_FUNC, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_TEST_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Depth.Test);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_WRITE_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Depth.Mask);
+	BEGIN_RING(chan, celsius, NV10_3D_DEPTH_FUNC, 1);
 	OUT_RING(chan, nvgl_comparison_op(ctx->Depth.Func));
 }
 
@@ -114,8 +115,8 @@ nv10_emit_dither(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_DITHER_ENABLE, 1);
-	OUT_RING(chan, ctx->Color.DitherFlag ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_DITHER_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Color.DitherFlag);
 }
 
 void
@@ -127,8 +128,8 @@ nv10_emit_logic_opcode(struct gl_context *ctx, int emit)
 	assert(!ctx->Color.ColorLogicOpEnabled
 	       || context_chipset(ctx) >= 0x11);
 
-	BEGIN_RING(chan, celsius, NV11TCL_COLOR_LOGIC_OP_ENABLE, 2);
-	OUT_RING(chan, ctx->Color.ColorLogicOpEnabled ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV11_3D_COLOR_LOGIC_OP_ENABLE, 2);
+	OUT_RINGb(chan, ctx->Color.ColorLogicOpEnabled);
 	OUT_RING(chan, nvgl_logicop_func(ctx->Color.LogicOp));
 }
 
@@ -138,9 +139,9 @@ nv10_emit_shade_model(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_SHADE_MODEL, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_SHADE_MODEL, 1);
 	OUT_RING(chan, ctx->Light.ShadeModel == GL_SMOOTH ?
-		 NV10TCL_SHADE_MODEL_SMOOTH : NV10TCL_SHADE_MODEL_FLAT);
+		 NV10_3D_SHADE_MODEL_SMOOTH : NV10_3D_SHADE_MODEL_FLAT);
 }
 
 void
@@ -149,10 +150,10 @@ nv10_emit_stencil_func(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_STENCIL_ENABLE, 1);
-	OUT_RING(chan, ctx->Stencil.Enabled ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_STENCIL_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Stencil.Enabled);
 
-	BEGIN_RING(chan, celsius, NV10TCL_STENCIL_FUNC_FUNC, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_STENCIL_FUNC_FUNC, 3);
 	OUT_RING(chan, nvgl_comparison_op(ctx->Stencil.Function[0]));
 	OUT_RING(chan, ctx->Stencil.Ref[0]);
 	OUT_RING(chan, ctx->Stencil.ValueMask[0]);
@@ -164,7 +165,7 @@ nv10_emit_stencil_mask(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_STENCIL_MASK, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_STENCIL_MASK, 1);
 	OUT_RING(chan, ctx->Stencil.WriteMask[0]);
 }
 
@@ -174,7 +175,7 @@ nv10_emit_stencil_op(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 
-	BEGIN_RING(chan, celsius, NV10TCL_STENCIL_OP_FAIL, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_STENCIL_OP_FAIL, 3);
 	OUT_RING(chan, nvgl_stencil_op(ctx->Stencil.FailFunc[0]));
 	OUT_RING(chan, nvgl_stencil_op(ctx->Stencil.ZFailFunc[0]));
 	OUT_RING(chan, nvgl_stencil_op(ctx->Stencil.ZPassFunc[0]));
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_tex.c b/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
index 0092ad0c20..fda67b1507 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_tex.c
@@ -28,14 +28,10 @@
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_texture.h"
-#include "nouveau_class.h"
+#include "nv10_3d.xml.h"
 #include "nouveau_util.h"
 #include "nv10_driver.h"
 
-#define TX_GEN_MODE(i, j) (NV10TCL_TX_GEN_MODE_S(i) + 4 * (j))
-#define TX_GEN_COEFF(i, j) (NV10TCL_TX_GEN_COEFF_S_A(i) + 16 * (j))
-#define TX_MATRIX(i) (NV10TCL_TX0_MATRIX(0) + 64 * (i))
-
 void
 nv10_emit_tex_gen(struct gl_context *ctx, int emit)
 {
@@ -53,15 +49,15 @@ nv10_emit_tex_gen(struct gl_context *ctx, int emit)
 
 			if (k) {
 				BEGIN_RING(chan, celsius,
-					   TX_GEN_COEFF(i, j), 4);
+					   NV10_3D_TEX_GEN_COEFF(i, j), 4);
 				OUT_RINGp(chan, k, 4);
 			}
 
-			BEGIN_RING(chan, celsius, TX_GEN_MODE(i, j), 1);
+			BEGIN_RING(chan, celsius, NV10_3D_TEX_GEN_MODE(i,j), 1);
 			OUT_RING(chan, nvgl_texgen_mode(coord->Mode));
 
 		} else {
-			BEGIN_RING(chan, celsius, TX_GEN_MODE(i, j), 1);
+			BEGIN_RING(chan, celsius, NV10_3D_TEX_GEN_MODE(i,j), 1);
 			OUT_RING(chan, 0);
 		}
 	}
@@ -80,14 +76,14 @@ nv10_emit_tex_mat(struct gl_context *ctx, int emit)
 	if (nctx->fallback == HWTNL &&
 	    ((ctx->Texture._TexMatEnabled & 1 << i) ||
 	     ctx->Texture.Unit[i]._GenFlags)) {
-		BEGIN_RING(chan, celsius, NV10TCL_TX_MATRIX_ENABLE(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_MATRIX_ENABLE(i), 1);
 		OUT_RING(chan, 1);
 
-		BEGIN_RING(chan, celsius, TX_MATRIX(i), 16);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_MATRIX(i, 0), 16);
 		OUT_RINGm(chan, ctx->TextureMatrixStack[i].Top->m);
 
 	} else {
-		BEGIN_RING(chan, celsius, NV10TCL_TX_MATRIX_ENABLE(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_MATRIX_ENABLE(i), 1);
 		OUT_RING(chan, 0);
 	}
 }
@@ -97,29 +93,29 @@ get_tex_format_pot(struct gl_texture_image *ti)
 {
 	switch (ti->TexFormat) {
 	case MESA_FORMAT_ARGB8888:
-		return NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8;
+		return NV10_3D_TEX_FORMAT_FORMAT_A8R8G8B8;
 
 	case MESA_FORMAT_XRGB8888:
-		return NV10TCL_TX_FORMAT_FORMAT_X8R8G8B8;
+		return NV10_3D_TEX_FORMAT_FORMAT_X8R8G8B8;
 
 	case MESA_FORMAT_ARGB1555:
-		return NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5;
+		return NV10_3D_TEX_FORMAT_FORMAT_A1R5G5B5;
 
 	case MESA_FORMAT_ARGB4444:
-		return NV10TCL_TX_FORMAT_FORMAT_A4R4G4B4;
+		return NV10_3D_TEX_FORMAT_FORMAT_A4R4G4B4;
 
 	case MESA_FORMAT_RGB565:
-		return NV10TCL_TX_FORMAT_FORMAT_R5G6B5;
+		return NV10_3D_TEX_FORMAT_FORMAT_R5G6B5;
 
 	case MESA_FORMAT_A8:
 	case MESA_FORMAT_I8:
-		return NV10TCL_TX_FORMAT_FORMAT_A8;
+		return NV10_3D_TEX_FORMAT_FORMAT_I8;
 
 	case MESA_FORMAT_L8:
-		return NV10TCL_TX_FORMAT_FORMAT_L8;
+		return NV10_3D_TEX_FORMAT_FORMAT_L8;
 
 	case MESA_FORMAT_CI8:
-		return NV10TCL_TX_FORMAT_FORMAT_INDEX8;
+		return NV10_3D_TEX_FORMAT_FORMAT_INDEX8;
 
 	default:
 		assert(0);
@@ -131,19 +127,19 @@ get_tex_format_rect(struct gl_texture_image *ti)
 {
 	switch (ti->TexFormat) {
 	case MESA_FORMAT_ARGB1555:
-		return NV10TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT;
+		return NV10_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT;
 
 	case MESA_FORMAT_RGB565:
-		return NV10TCL_TX_FORMAT_FORMAT_R5G6B5_RECT;
+		return NV10_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT;
 
 	case MESA_FORMAT_ARGB8888:
 	case MESA_FORMAT_XRGB8888:
-		return NV10TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT;
+		return NV10_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT;
 
 	case MESA_FORMAT_A8:
 	case MESA_FORMAT_L8:
 	case MESA_FORMAT_I8:
-		return NV10TCL_TX_FORMAT_FORMAT_A8_RECT;
+		return NV10_3D_TEX_FORMAT_FORMAT_I8_RECT;
 
 	default:
 		assert(0);
@@ -164,7 +160,7 @@ nv10_emit_tex_obj(struct gl_context *ctx, int emit)
 	uint32_t tx_format, tx_filter, tx_enable;
 
 	if (!ctx->Texture.Unit[i]._ReallyEnabled) {
-		BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_ENABLE(i), 1);
 		OUT_RING(chan, 0);
 		return;
 	}
@@ -186,13 +182,13 @@ nv10_emit_tex_obj(struct gl_context *ctx, int emit)
 	tx_filter = nvgl_filter_mode(t->MagFilter) << 28
 		| nvgl_filter_mode(t->MinFilter) << 24;
 
-	tx_enable = NV10TCL_TX_ENABLE_ENABLE
+	tx_enable = NV10_3D_TEX_ENABLE_ENABLE
 		| log2i(t->MaxAnisotropy) << 4;
 
 	if (t->Target == GL_TEXTURE_RECTANGLE) {
-		BEGIN_RING(chan, celsius, NV10TCL_TX_NPOT_PITCH(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_NPOT_PITCH(i), 1);
 		OUT_RING(chan, s->pitch << 16);
-		BEGIN_RING(chan, celsius, NV10TCL_TX_NPOT_SIZE(i), 1);
+		BEGIN_RING(chan, celsius, NV10_3D_TEX_NPOT_SIZE(i), 1);
 		OUT_RING(chan, align(s->width, 2) << 16 | s->height);
 
 		tx_format |= get_tex_format_rect(ti);
@@ -211,26 +207,26 @@ nv10_emit_tex_obj(struct gl_context *ctx, int emit)
 		lod_min = CLAMP(lod_min, 0, 15);
 		lod_bias = CLAMP(lod_bias, 0, 15);
 
-		tx_format |= NV10TCL_TX_FORMAT_MIPMAP;
+		tx_format |= NV10_3D_TEX_FORMAT_MIPMAP;
 		tx_filter |= lod_bias << 8;
 		tx_enable |= lod_min << 26
 			| lod_max << 14;
 	}
 
 	/* Write it to the hardware. */
-	nouveau_bo_mark(bctx, celsius, NV10TCL_TX_FORMAT(i),
+	nouveau_bo_mark(bctx, celsius, NV10_3D_TEX_FORMAT(i),
 			s->bo, tx_format, 0,
-			NV10TCL_TX_FORMAT_DMA0,
-			NV10TCL_TX_FORMAT_DMA1,
+			NV10_3D_TEX_FORMAT_DMA0,
+			NV10_3D_TEX_FORMAT_DMA1,
 			bo_flags | NOUVEAU_BO_OR);
 
-	nouveau_bo_markl(bctx, celsius, NV10TCL_TX_OFFSET(i),
+	nouveau_bo_markl(bctx, celsius, NV10_3D_TEX_OFFSET(i),
 			 s->bo, s->offset, bo_flags);
 
-	BEGIN_RING(chan, celsius, NV10TCL_TX_FILTER(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_TEX_FILTER(i), 1);
 	OUT_RING(chan, tx_filter);
 
-	BEGIN_RING(chan, celsius, NV10TCL_TX_ENABLE(i), 1);
+	BEGIN_RING(chan, celsius, NV10_3D_TEX_ENABLE(i), 1);
 	OUT_RING(chan, tx_enable);
 }
 
diff --git a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
index 175abfca5c..e8bd12e6e0 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_state_tnl.c
@@ -28,7 +28,7 @@
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv10_3d.xml.h"
 #include "nv10_driver.h"
 
 void
@@ -42,13 +42,13 @@ get_material_bitmask(unsigned m)
 	unsigned ret = 0;
 
 	if (m & MAT_BIT_FRONT_EMISSION)
-		ret |= NV10TCL_COLOR_MATERIAL_EMISSION;
+		ret |= NV10_3D_COLOR_MATERIAL_EMISSION;
 	if (m & MAT_BIT_FRONT_AMBIENT)
-		ret |= NV10TCL_COLOR_MATERIAL_AMBIENT;
+		ret |= NV10_3D_COLOR_MATERIAL_AMBIENT;
 	if (m & MAT_BIT_FRONT_DIFFUSE)
-		ret |= NV10TCL_COLOR_MATERIAL_DIFFUSE;
+		ret |= NV10_3D_COLOR_MATERIAL_DIFFUSE;
 	if (m & MAT_BIT_FRONT_SPECULAR)
-		ret |= NV10TCL_COLOR_MATERIAL_SPECULAR;
+		ret |= NV10_3D_COLOR_MATERIAL_SPECULAR;
 
 	return ret;
 }
@@ -60,7 +60,7 @@ nv10_emit_color_material(struct gl_context *ctx, int emit)
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 	unsigned mask = get_material_bitmask(ctx->Light.ColorMaterialBitmask);
 
-	BEGIN_RING(chan, celsius, NV10TCL_COLOR_MATERIAL, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_COLOR_MATERIAL, 1);
 	OUT_RING(chan, ctx->Light.ColorMaterialEnabled ? mask : 0);
 }
 
@@ -69,11 +69,11 @@ get_fog_mode(unsigned mode)
 {
 	switch (mode) {
 	case GL_LINEAR:
-		return NV10TCL_FOG_MODE_LINEAR;
+		return NV10_3D_FOG_MODE_LINEAR;
 	case GL_EXP:
-		return NV10TCL_FOG_MODE_EXP;
+		return NV10_3D_FOG_MODE_EXP;
 	case GL_EXP2:
-		return NV10TCL_FOG_MODE_EXP2;
+		return NV10_3D_FOG_MODE_EXP2;
 	default:
 		assert(0);
 	}
@@ -84,9 +84,9 @@ get_fog_source(unsigned source)
 {
 	switch (source) {
 	case GL_FOG_COORDINATE_EXT:
-		return NV10TCL_FOG_COORD_FOG;
+		return NV10_3D_FOG_COORD_FOG;
 	case GL_FRAGMENT_DEPTH_EXT:
-		return NV10TCL_FOG_COORD_DIST_ORTHOGONAL_ABS;
+		return NV10_3D_FOG_COORD_DIST_ORTHOGONAL_ABS;
 	default:
 		assert(0);
 	}
@@ -133,13 +133,13 @@ nv10_emit_fog(struct gl_context *ctx, int emit)
 
 	nv10_get_fog_coeff(ctx, k);
 
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_MODE, 4);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_MODE, 4);
 	OUT_RING(chan, get_fog_mode(f->Mode));
 	OUT_RING(chan, get_fog_source(source));
-	OUT_RING(chan, f->Enabled ? 1 : 0);
+	OUT_RINGb(chan, f->Enabled);
 	OUT_RING(chan, pack_rgba_f(MESA_FORMAT_RGBA8888_REV, f->Color));
 
-	BEGIN_RING(chan, celsius, NV10TCL_FOG_EQUATION_CONSTANT, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_FOG_COEFF(0), 3);
 	OUT_RINGp(chan, k, 3);
 
 	context_dirty(ctx, FRAG);
@@ -150,13 +150,13 @@ get_light_mode(struct gl_light *l)
 {
 	if (l->Enabled) {
 		if (l->_Flags & LIGHT_SPOT)
-			return NV10TCL_ENABLED_LIGHTS_0_DIRECTIONAL;
+			return NV10_3D_ENABLED_LIGHTS_0_DIRECTIONAL;
 		else if (l->_Flags & LIGHT_POSITIONAL)
-			return NV10TCL_ENABLED_LIGHTS_0_POSITIONAL;
+			return NV10_3D_ENABLED_LIGHTS_0_POSITIONAL;
 		else
-			return NV10TCL_ENABLED_LIGHTS_0_NONPOSITIONAL;
+			return NV10_3D_ENABLED_LIGHTS_0_NONPOSITIONAL;
 	} else {
-		return NV10TCL_ENABLED_LIGHTS_0_DISABLED;
+		return NV10_3D_ENABLED_LIGHTS_0_DISABLED;
 	}
 }
 
@@ -170,7 +170,7 @@ nv10_emit_light_enable(struct gl_context *ctx, int emit)
 	int i;
 
 	if (nctx->fallback != HWTNL) {
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHTING_ENABLE, 1);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHTING_ENABLE, 1);
 		OUT_RING(chan, 0);
 		return;
 	}
@@ -178,12 +178,12 @@ nv10_emit_light_enable(struct gl_context *ctx, int emit)
 	for (i = 0; i < MAX_LIGHTS; i++)
 		en_lights |= get_light_mode(&ctx->Light.Light[i]) << 2 * i;
 
-	BEGIN_RING(chan, celsius, NV10TCL_ENABLED_LIGHTS, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_ENABLED_LIGHTS, 1);
 	OUT_RING(chan, en_lights);
-	BEGIN_RING(chan, celsius, NV10TCL_LIGHTING_ENABLE, 1);
-	OUT_RING(chan, ctx->Light.Enabled ? 1 : 0);
-	BEGIN_RING(chan, celsius, NV10TCL_NORMALIZE_ENABLE, 1);
-	OUT_RING(chan, ctx->Transform.Normalize ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_LIGHTING_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Light.Enabled);
+	BEGIN_RING(chan, celsius, NV10_3D_NORMALIZE_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Transform.Normalize);
 }
 
 void
@@ -193,16 +193,16 @@ nv10_emit_light_model(struct gl_context *ctx, int emit)
 	struct nouveau_grobj *celsius = context_eng3d(ctx);
 	struct gl_lightmodel *m = &ctx->Light.Model;
 
-	BEGIN_RING(chan, celsius, NV10TCL_SEPARATE_SPECULAR_ENABLE, 1);
-	OUT_RING(chan, m->ColorControl == GL_SEPARATE_SPECULAR_COLOR ? 1 : 0);
+	BEGIN_RING(chan, celsius, NV10_3D_SEPARATE_SPECULAR_ENABLE, 1);
+	OUT_RINGb(chan, m->ColorControl == GL_SEPARATE_SPECULAR_COLOR);
 
-	BEGIN_RING(chan, celsius, NV10TCL_LIGHT_MODEL, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_LIGHT_MODEL, 1);
 	OUT_RING(chan, ((m->LocalViewer ?
-			 NV10TCL_LIGHT_MODEL_LOCAL_VIEWER : 0) |
+			 NV10_3D_LIGHT_MODEL_LOCAL_VIEWER : 0) |
 			(NEED_SECONDARY_COLOR(ctx) ?
-			 NV10TCL_LIGHT_MODEL_SEPARATE_SPECULAR : 0) |
+			 NV10_3D_LIGHT_MODEL_SEPARATE_SPECULAR : 0) |
 			(!ctx->Light.Enabled && ctx->Fog.ColorSumEnabled ?
-			 NV10TCL_LIGHT_MODEL_VERTEX_SPECULAR : 0)));
+			 NV10_3D_LIGHT_MODEL_VERTEX_SPECULAR : 0)));
 }
 
 static float
@@ -281,20 +281,20 @@ nv10_emit_light_source(struct gl_context *ctx, int emit)
 	struct gl_light *l = &ctx->Light.Light[i];
 
 	if (l->_Flags & LIGHT_POSITIONAL) {
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_POSITION_X(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_POSITION_X(i), 3);
 		OUT_RINGp(chan, l->_Position, 3);
 
 		BEGIN_RING(chan, celsius,
-			   NV10TCL_LIGHT_ATTENUATION_CONSTANT(i), 3);
+			   NV10_3D_LIGHT_ATTENUATION_CONSTANT(i), 3);
 		OUT_RINGf(chan, l->ConstantAttenuation);
 		OUT_RINGf(chan, l->LinearAttenuation);
 		OUT_RINGf(chan, l->QuadraticAttenuation);
 
 	} else {
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_DIRECTION_X(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_DIRECTION_X(i), 3);
 		OUT_RINGp(chan, l->_VP_inf_norm, 3);
 
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_HALF_VECTOR_X(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_HALF_VECTOR_X(i), 3);
 		OUT_RINGp(chan, l->_h_inf_norm, 3);
 	}
 
@@ -303,7 +303,7 @@ nv10_emit_light_source(struct gl_context *ctx, int emit)
 
 		nv10_get_spot_coeff(l, k);
 
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_SPOT_CUTOFF_A(i), 7);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_SPOT_CUTOFF(i, 0), 7);
 		OUT_RINGp(chan, k, 7);
 	}
 }
@@ -335,11 +335,11 @@ nv10_emit_material_ambient(struct gl_context *ctx, int emit)
 		ZERO_3V(c_factor);
 	}
 
-	BEGIN_RING(chan, celsius, NV10TCL_LIGHT_MODEL_AMBIENT_R, 3);
+	BEGIN_RING(chan, celsius, NV10_3D_LIGHT_MODEL_AMBIENT_R, 3);
 	OUT_RINGp(chan, c_scene, 3);
 
 	if (ctx->Light.ColorMaterialEnabled) {
-		BEGIN_RING(chan, celsius, NV10TCL_MATERIAL_FACTOR_R, 3);
+		BEGIN_RING(chan, celsius, NV10_3D_MATERIAL_FACTOR_R, 3);
 		OUT_RINGp(chan, c_factor, 3);
 	}
 
@@ -349,7 +349,7 @@ nv10_emit_material_ambient(struct gl_context *ctx, int emit)
 				  l->Ambient :
 				  l->_MatAmbient[0]);
 
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_AMBIENT_R(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_AMBIENT_R(i), 3);
 		OUT_RINGp(chan, c_light, 3);
 	}
 }
@@ -362,7 +362,7 @@ nv10_emit_material_diffuse(struct gl_context *ctx, int emit)
 	GLfloat (*mat)[4] = ctx->Light.Material.Attrib;
 	struct gl_light *l;
 
-	BEGIN_RING(chan, celsius, NV10TCL_MATERIAL_FACTOR_A, 1);
+	BEGIN_RING(chan, celsius, NV10_3D_MATERIAL_FACTOR_A, 1);
 	OUT_RINGf(chan, mat[MAT_ATTRIB_FRONT_DIFFUSE][3]);
 
 	foreach(l, &ctx->Light.EnabledList) {
@@ -371,7 +371,7 @@ nv10_emit_material_diffuse(struct gl_context *ctx, int emit)
 				  l->Diffuse :
 				  l->_MatDiffuse[0]);
 
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_DIFFUSE_R(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_DIFFUSE_R(i), 3);
 		OUT_RINGp(chan, c_light, 3);
 	}
 }
@@ -389,7 +389,7 @@ nv10_emit_material_specular(struct gl_context *ctx, int emit)
 				  l->Specular :
 				  l->_MatSpecular[0]);
 
-		BEGIN_RING(chan, celsius, NV10TCL_LIGHT_SPECULAR_R(i), 3);
+		BEGIN_RING(chan, celsius, NV10_3D_LIGHT_SPECULAR_R(i), 3);
 		OUT_RINGp(chan, c_light, 3);
 	}
 }
@@ -430,7 +430,7 @@ nv10_emit_material_shininess(struct gl_context *ctx, int emit)
 		CLAMP(mat[MAT_ATTRIB_FRONT_SHININESS][0], 0, 1024),
 		k);
 
-	BEGIN_RING(chan, celsius, NV10TCL_MATERIAL_SHININESS(0), 6);
+	BEGIN_RING(chan, celsius, NV10_3D_MATERIAL_SHININESS(0), 6);
 	OUT_RINGp(chan, k, 6);
 }
 
@@ -447,7 +447,7 @@ nv10_emit_modelview(struct gl_context *ctx, int emit)
 
 	if (ctx->Light._NeedEyeCoords || ctx->Fog.Enabled ||
 	    (ctx->Texture._GenFlags & TEXGEN_NEED_EYE_COORD)) {
-		BEGIN_RING(chan, celsius, NV10TCL_MODELVIEW0_MATRIX(0), 16);
+		BEGIN_RING(chan, celsius, NV10_3D_MODELVIEW_MATRIX(0, 0), 16);
 		OUT_RINGm(chan, m->m);
 	}
 
@@ -456,7 +456,7 @@ nv10_emit_modelview(struct gl_context *ctx, int emit)
 		int i, j;
 
 		BEGIN_RING(chan, celsius,
-			   NV10TCL_INVERSE_MODELVIEW0_MATRIX(0), 12);
+			   NV10_3D_INVERSE_MODELVIEW_MATRIX(0, 0), 12);
 		for (i = 0; i < 3; i++)
 			for (j = 0; j < 4; j++)
 				OUT_RINGf(chan, m->inv[4*i + j]);
@@ -485,7 +485,7 @@ nv10_emit_projection(struct gl_context *ctx, int emit)
 	if (nctx->fallback == HWTNL)
 		_math_matrix_mul_matrix(&m, &m, &ctx->_ModelProjectMatrix);
 
-	BEGIN_RING(chan, celsius, NV10TCL_PROJECTION_MATRIX(0), 16);
+	BEGIN_RING(chan, celsius, NV10_3D_PROJECTION_MATRIX(0), 16);
 	OUT_RINGm(chan, m.m);
 
 	_math_matrix_dtr(&m);
diff --git a/src/mesa/drivers/dri/nouveau/nv20_3d.xml.h b/src/mesa/drivers/dri/nouveau/nv20_3d.xml.h
new file mode 100644
index 0000000000..c8ed861961
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv20_3d.xml.h
@@ -0,0 +1,2076 @@
+#ifndef NV20_3D_XML
+#define NV20_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv20_3d.xml    (  21073 bytes, from 2010-11-15 02:24:38)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nv10_3d.xml    (  18449 bytes, from 2010-11-15 02:24:38)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+- nv_3ddefs.xml  (  16394 bytes, from 2010-11-01 00:28:46)
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define NV20_VERTEX_ATTR_POS					0x00000000
+#define NV20_VERTEX_ATTR_NORMAL					0x00000002
+#define NV20_VERTEX_ATTR_COLOR0					0x00000003
+#define NV20_VERTEX_ATTR_COLOR1					0x00000004
+#define NV20_VERTEX_ATTR_FOG					0x00000005
+#define NV20_VERTEX_ATTR_TEX0					0x00000009
+#define NV20_VERTEX_ATTR_TEX1					0x0000000a
+#define NV20_VERTEX_ATTR_TEX2					0x0000000b
+#define NV20_VERTEX_ATTR_TEX3					0x0000000c
+
+
+
+#define NV20_3D_FLIP_SET_READ					0x00000120
+
+#define NV20_3D_FLIP_SET_WRITE					0x00000124
+
+#define NV20_3D_FLIP_MAX					0x00000128
+
+#define NV20_3D_FLIP_INCR_WRITE					0x0000012c
+
+#define NV20_3D_FLIP_WAIT					0x00000130
+
+#define NV20_3D_DMA_NOTIFY					0x00000180
+
+#define NV20_3D_DMA_TEXTURE0					0x00000184
+
+#define NV20_3D_DMA_TEXTURE1					0x00000188
+
+#define NV20_3D_DMA_COLOR					0x00000194
+
+#define NV20_3D_DMA_ZETA					0x00000198
+
+#define NV20_3D_RT_HORIZ					0x00000200
+#define NV20_3D_RT_HORIZ_X__MASK				0x0000ffff
+#define NV20_3D_RT_HORIZ_X__SHIFT				0
+#define NV20_3D_RT_HORIZ_W__MASK				0xffff0000
+#define NV20_3D_RT_HORIZ_W__SHIFT				16
+
+#define NV20_3D_RT_VERT						0x00000204
+#define NV20_3D_RT_VERT_Y__MASK					0x0000ffff
+#define NV20_3D_RT_VERT_Y__SHIFT				0
+#define NV20_3D_RT_VERT_H__MASK					0xffff0000
+#define NV20_3D_RT_VERT_H__SHIFT				16
+
+#define NV20_3D_RT_FORMAT					0x00000208
+#define NV20_3D_RT_FORMAT_TYPE__MASK				0x00000f00
+#define NV20_3D_RT_FORMAT_TYPE__SHIFT				8
+#define NV20_3D_RT_FORMAT_TYPE_LINEAR				0x00000100
+#define NV20_3D_RT_FORMAT_TYPE_SWIZZLED				0x00000200
+#define NV20_3D_RT_FORMAT_DEPTH__MASK				0x00000030
+#define NV20_3D_RT_FORMAT_DEPTH__SHIFT				4
+#define NV20_3D_RT_FORMAT_DEPTH_Z16				0x00000010
+#define NV20_3D_RT_FORMAT_DEPTH_Z24S8				0x00000020
+#define NV20_3D_RT_FORMAT_COLOR__MASK				0x0000000f
+#define NV20_3D_RT_FORMAT_COLOR__SHIFT				0
+#define NV20_3D_RT_FORMAT_COLOR_R5G6B5				0x00000003
+#define NV20_3D_RT_FORMAT_COLOR_X8R8G8B8			0x00000005
+#define NV20_3D_RT_FORMAT_COLOR_A8R8G8B8			0x00000008
+#define NV20_3D_RT_FORMAT_COLOR_B8				0x00000009
+
+#define NV20_3D_RT_PITCH					0x0000020c
+#define NV20_3D_RT_PITCH_COLOR_PITCH__MASK			0x0000ffff
+#define NV20_3D_RT_PITCH_COLOR_PITCH__SHIFT			0
+#define NV20_3D_RT_PITCH_ZETA_PITCH__MASK			0xffff0000
+#define NV20_3D_RT_PITCH_ZETA_PITCH__SHIFT			16
+
+#define NV20_3D_COLOR_OFFSET					0x00000210
+
+#define NV20_3D_ZETA_OFFSET					0x00000214
+
+#define NV20_3D_UNK0290						0x00000290
+
+#define NV20_3D_VIEWPORT_CLIP_MODE				0x000002b4
+
+#define NV20_3D_VIEWPORT_CLIP_HORIZ(i0)			       (0x000002c0 + 0x4*(i0))
+#define NV20_3D_VIEWPORT_CLIP_HORIZ__ESIZE			0x00000004
+#define NV20_3D_VIEWPORT_CLIP_HORIZ__LEN			0x00000008
+#define NV20_3D_VIEWPORT_CLIP_HORIZ_CLIP_L__MASK		0x000007ff
+#define NV20_3D_VIEWPORT_CLIP_HORIZ_CLIP_L__SHIFT		0
+#define NV20_3D_VIEWPORT_CLIP_HORIZ_CLIP_R__MASK		0x07ff0000
+#define NV20_3D_VIEWPORT_CLIP_HORIZ_CLIP_R__SHIFT		16
+
+#define NV20_3D_VIEWPORT_CLIP_VERT(i0)			       (0x000002e0 + 0x4*(i0))
+#define NV20_3D_VIEWPORT_CLIP_VERT__ESIZE			0x00000004
+#define NV20_3D_VIEWPORT_CLIP_VERT__LEN				0x00000008
+#define NV20_3D_VIEWPORT_CLIP_VERT_CLIP_T__MASK			0x000007ff
+#define NV20_3D_VIEWPORT_CLIP_VERT_CLIP_T__SHIFT		0
+#define NV20_3D_VIEWPORT_CLIP_VERT_CLIP_B__MASK			0x07ff0000
+#define NV20_3D_VIEWPORT_CLIP_VERT_CLIP_B__SHIFT		16
+
+#define NV20_3D_ALPHA_FUNC_ENABLE				0x00000300
+
+#define NV20_3D_BLEND_FUNC_ENABLE				0x00000304
+
+#define NV20_3D_CULL_FACE_ENABLE				0x00000308
+
+#define NV20_3D_DEPTH_TEST_ENABLE				0x0000030c
+
+#define NV20_3D_DITHER_ENABLE					0x00000310
+
+#define NV20_3D_LIGHTING_ENABLE					0x00000314
+
+#define NV20_3D_POINT_PARAMETERS_ENABLE				0x00000318
+
+#define NV20_3D_POINT_SMOOTH_ENABLE				0x0000031c
+
+#define NV20_3D_LINE_SMOOTH_ENABLE				0x00000320
+
+#define NV20_3D_POLYGON_SMOOTH_ENABLE				0x00000324
+
+#define NV20_3D_STENCIL_ENABLE					0x0000032c
+
+#define NV20_3D_POLYGON_OFFSET_POINT_ENABLE			0x00000330
+
+#define NV20_3D_POLYGON_OFFSET_LINE_ENABLE			0x00000334
+
+#define NV20_3D_POLYGON_OFFSET_FILL_ENABLE			0x00000338
+
+#define NV20_3D_ALPHA_FUNC_FUNC					0x0000033c
+#define NV20_3D_ALPHA_FUNC_FUNC_NEVER				0x00000200
+#define NV20_3D_ALPHA_FUNC_FUNC_LESS				0x00000201
+#define NV20_3D_ALPHA_FUNC_FUNC_EQUAL				0x00000202
+#define NV20_3D_ALPHA_FUNC_FUNC_LEQUAL				0x00000203
+#define NV20_3D_ALPHA_FUNC_FUNC_GREATER				0x00000204
+#define NV20_3D_ALPHA_FUNC_FUNC_NOTEQUAL			0x00000205
+#define NV20_3D_ALPHA_FUNC_FUNC_GEQUAL				0x00000206
+#define NV20_3D_ALPHA_FUNC_FUNC_ALWAYS				0x00000207
+
+#define NV20_3D_ALPHA_FUNC_REF					0x00000340
+
+#define NV20_3D_BLEND_FUNC_SRC					0x00000344
+#define NV20_3D_BLEND_FUNC_SRC_ZERO				0x00000000
+#define NV20_3D_BLEND_FUNC_SRC_ONE				0x00000001
+#define NV20_3D_BLEND_FUNC_SRC_SRC_COLOR			0x00000300
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_COLOR		0x00000301
+#define NV20_3D_BLEND_FUNC_SRC_SRC_ALPHA			0x00000302
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_SRC_ALPHA		0x00000303
+#define NV20_3D_BLEND_FUNC_SRC_DST_ALPHA			0x00000304
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_ALPHA		0x00000305
+#define NV20_3D_BLEND_FUNC_SRC_DST_COLOR			0x00000306
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_DST_COLOR		0x00000307
+#define NV20_3D_BLEND_FUNC_SRC_SRC_ALPHA_SATURATE		0x00000308
+#define NV20_3D_BLEND_FUNC_SRC_CONSTANT_COLOR			0x00008001
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_COLOR		0x00008002
+#define NV20_3D_BLEND_FUNC_SRC_CONSTANT_ALPHA			0x00008003
+#define NV20_3D_BLEND_FUNC_SRC_ONE_MINUS_CONSTANT_ALPHA		0x00008004
+
+#define NV20_3D_BLEND_FUNC_DST					0x00000348
+#define NV20_3D_BLEND_FUNC_DST_ZERO				0x00000000
+#define NV20_3D_BLEND_FUNC_DST_ONE				0x00000001
+#define NV20_3D_BLEND_FUNC_DST_SRC_COLOR			0x00000300
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_COLOR		0x00000301
+#define NV20_3D_BLEND_FUNC_DST_SRC_ALPHA			0x00000302
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_SRC_ALPHA		0x00000303
+#define NV20_3D_BLEND_FUNC_DST_DST_ALPHA			0x00000304
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_DST_ALPHA		0x00000305
+#define NV20_3D_BLEND_FUNC_DST_DST_COLOR			0x00000306
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_DST_COLOR		0x00000307
+#define NV20_3D_BLEND_FUNC_DST_SRC_ALPHA_SATURATE		0x00000308
+#define NV20_3D_BLEND_FUNC_DST_CONSTANT_COLOR			0x00008001
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_COLOR		0x00008002
+#define NV20_3D_BLEND_FUNC_DST_CONSTANT_ALPHA			0x00008003
+#define NV20_3D_BLEND_FUNC_DST_ONE_MINUS_CONSTANT_ALPHA		0x00008004
+
+#define NV20_3D_BLEND_COLOR					0x0000034c
+#define NV20_3D_BLEND_COLOR_B__MASK				0x000000ff
+#define NV20_3D_BLEND_COLOR_B__SHIFT				0
+#define NV20_3D_BLEND_COLOR_G__MASK				0x0000ff00
+#define NV20_3D_BLEND_COLOR_G__SHIFT				8
+#define NV20_3D_BLEND_COLOR_R__MASK				0x00ff0000
+#define NV20_3D_BLEND_COLOR_R__SHIFT				16
+#define NV20_3D_BLEND_COLOR_A__MASK				0xff000000
+#define NV20_3D_BLEND_COLOR_A__SHIFT				24
+
+#define NV20_3D_BLEND_EQUATION					0x00000350
+#define NV20_3D_BLEND_EQUATION_FUNC_ADD				0x00008006
+#define NV20_3D_BLEND_EQUATION_MIN				0x00008007
+#define NV20_3D_BLEND_EQUATION_MAX				0x00008008
+#define NV20_3D_BLEND_EQUATION_FUNC_SUBTRACT			0x0000800a
+#define NV20_3D_BLEND_EQUATION_FUNC_REVERSE_SUBTRACT		0x0000800b
+
+#define NV20_3D_DEPTH_FUNC					0x00000354
+#define NV20_3D_DEPTH_FUNC_NEVER				0x00000200
+#define NV20_3D_DEPTH_FUNC_LESS					0x00000201
+#define NV20_3D_DEPTH_FUNC_EQUAL				0x00000202
+#define NV20_3D_DEPTH_FUNC_LEQUAL				0x00000203
+#define NV20_3D_DEPTH_FUNC_GREATER				0x00000204
+#define NV20_3D_DEPTH_FUNC_NOTEQUAL				0x00000205
+#define NV20_3D_DEPTH_FUNC_GEQUAL				0x00000206
+#define NV20_3D_DEPTH_FUNC_ALWAYS				0x00000207
+
+#define NV20_3D_COLOR_MASK					0x00000358
+#define NV20_3D_COLOR_MASK_B					0x00000001
+#define NV20_3D_COLOR_MASK_G					0x00000100
+#define NV20_3D_COLOR_MASK_R					0x00010000
+#define NV20_3D_COLOR_MASK_A					0x01000000
+
+#define NV20_3D_DEPTH_WRITE_ENABLE				0x0000035c
+
+#define NV20_3D_STENCIL_MASK					0x00000360
+
+#define NV20_3D_STENCIL_FUNC_FUNC				0x00000364
+#define NV20_3D_STENCIL_FUNC_FUNC_NEVER				0x00000200
+#define NV20_3D_STENCIL_FUNC_FUNC_LESS				0x00000201
+#define NV20_3D_STENCIL_FUNC_FUNC_EQUAL				0x00000202
+#define NV20_3D_STENCIL_FUNC_FUNC_LEQUAL			0x00000203
+#define NV20_3D_STENCIL_FUNC_FUNC_GREATER			0x00000204
+#define NV20_3D_STENCIL_FUNC_FUNC_NOTEQUAL			0x00000205
+#define NV20_3D_STENCIL_FUNC_FUNC_GEQUAL			0x00000206
+#define NV20_3D_STENCIL_FUNC_FUNC_ALWAYS			0x00000207
+
+#define NV20_3D_STENCIL_FUNC_REF				0x00000368
+
+#define NV20_3D_STENCIL_FUNC_MASK				0x0000036c
+
+#define NV20_3D_STENCIL_OP_FAIL					0x00000370
+#define NV20_3D_STENCIL_OP_FAIL_ZERO				0x00000000
+#define NV20_3D_STENCIL_OP_FAIL_INVERT				0x0000150a
+#define NV20_3D_STENCIL_OP_FAIL_KEEP				0x00001e00
+#define NV20_3D_STENCIL_OP_FAIL_REPLACE				0x00001e01
+#define NV20_3D_STENCIL_OP_FAIL_INCR				0x00001e02
+#define NV20_3D_STENCIL_OP_FAIL_DECR				0x00001e03
+#define NV20_3D_STENCIL_OP_FAIL_INCR_WRAP			0x00008507
+#define NV20_3D_STENCIL_OP_FAIL_DECR_WRAP			0x00008508
+
+#define NV20_3D_STENCIL_OP_ZFAIL				0x00000374
+#define NV20_3D_STENCIL_OP_ZFAIL_ZERO				0x00000000
+#define NV20_3D_STENCIL_OP_ZFAIL_INVERT				0x0000150a
+#define NV20_3D_STENCIL_OP_ZFAIL_KEEP				0x00001e00
+#define NV20_3D_STENCIL_OP_ZFAIL_REPLACE			0x00001e01
+#define NV20_3D_STENCIL_OP_ZFAIL_INCR				0x00001e02
+#define NV20_3D_STENCIL_OP_ZFAIL_DECR				0x00001e03
+#define NV20_3D_STENCIL_OP_ZFAIL_INCR_WRAP			0x00008507
+#define NV20_3D_STENCIL_OP_ZFAIL_DECR_WRAP			0x00008508
+
+#define NV20_3D_STENCIL_OP_ZPASS				0x00000378
+#define NV20_3D_STENCIL_OP_ZPASS_ZERO				0x00000000
+#define NV20_3D_STENCIL_OP_ZPASS_INVERT				0x0000150a
+#define NV20_3D_STENCIL_OP_ZPASS_KEEP				0x00001e00
+#define NV20_3D_STENCIL_OP_ZPASS_REPLACE			0x00001e01
+#define NV20_3D_STENCIL_OP_ZPASS_INCR				0x00001e02
+#define NV20_3D_STENCIL_OP_ZPASS_DECR				0x00001e03
+#define NV20_3D_STENCIL_OP_ZPASS_INCR_WRAP			0x00008507
+#define NV20_3D_STENCIL_OP_ZPASS_DECR_WRAP			0x00008508
+
+#define NV20_3D_SHADE_MODEL					0x0000037c
+#define NV20_3D_SHADE_MODEL_FLAT				0x00001d00
+#define NV20_3D_SHADE_MODEL_SMOOTH				0x00001d01
+
+#define NV20_3D_LINE_WIDTH					0x00000380
+
+#define NV20_3D_POLYGON_OFFSET_FACTOR				0x00000384
+
+#define NV20_3D_POLYGON_OFFSET_UNITS				0x00000388
+
+#define NV20_3D_POLYGON_MODE_FRONT				0x0000038c
+#define NV20_3D_POLYGON_MODE_FRONT_POINT			0x00001b00
+#define NV20_3D_POLYGON_MODE_FRONT_LINE				0x00001b01
+#define NV20_3D_POLYGON_MODE_FRONT_FILL				0x00001b02
+
+#define NV20_3D_POLYGON_MODE_BACK				0x00000390
+#define NV20_3D_POLYGON_MODE_BACK_POINT				0x00001b00
+#define NV20_3D_POLYGON_MODE_BACK_LINE				0x00001b01
+#define NV20_3D_POLYGON_MODE_BACK_FILL				0x00001b02
+
+#define NV20_3D_DEPTH_RANGE_NEAR				0x00000394
+
+#define NV20_3D_DEPTH_RANGE_FAR					0x00000398
+
+#define NV20_3D_CULL_FACE					0x0000039c
+#define NV20_3D_CULL_FACE_FRONT					0x00000404
+#define NV20_3D_CULL_FACE_BACK					0x00000405
+#define NV20_3D_CULL_FACE_FRONT_AND_BACK			0x00000408
+
+#define NV20_3D_FRONT_FACE					0x000003a0
+#define NV20_3D_FRONT_FACE_CW					0x00000900
+#define NV20_3D_FRONT_FACE_CCW					0x00000901
+
+#define NV20_3D_DMA_FENCE					0x000001a4
+
+#define NV20_3D_DMA_QUERY					0x000001a8
+
+
+#define NV20_3D_VERTEX_POS_3F					0x00001500
+
+
+#define NV20_3D_VERTEX_POS_3F_X					0x00001500
+
+#define NV20_3D_VERTEX_POS_3F_Y					0x00001504
+
+#define NV20_3D_VERTEX_POS_3F_Z					0x00001508
+
+#define NV20_3D_VERTEX_POS_4F					0x00001518
+
+
+#define NV20_3D_VERTEX_POS_4F_X					0x00001518
+
+#define NV20_3D_VERTEX_POS_4F_Y					0x0000151c
+
+#define NV20_3D_VERTEX_POS_4F_Z					0x00001520
+
+#define NV20_3D_VERTEX_POS_4F_W					0x00001524
+
+#define NV20_3D_VERTEX_POS_3I					0x00001528
+
+
+#define NV20_3D_VERTEX_POS_3I_XY				0x00001528
+#define NV20_3D_VERTEX_POS_3I_XY_X__MASK			0x0000ffff
+#define NV20_3D_VERTEX_POS_3I_XY_X__SHIFT			0
+#define NV20_3D_VERTEX_POS_3I_XY_Y__MASK			0xffff0000
+#define NV20_3D_VERTEX_POS_3I_XY_Y__SHIFT			16
+
+#define NV20_3D_VERTEX_POS_3I_Z					0x0000152c
+#define NV20_3D_VERTEX_POS_3I_Z_Z__MASK				0x0000ffff
+#define NV20_3D_VERTEX_POS_3I_Z_Z__SHIFT			0
+
+#define NV20_3D_VERTEX_NOR_3F					0x00001530
+
+
+#define NV20_3D_VERTEX_NOR_3F_X					0x00001530
+
+#define NV20_3D_VERTEX_NOR_3F_Y					0x00001534
+
+#define NV20_3D_VERTEX_NOR_3F_Z					0x00001538
+
+#define NV20_3D_VERTEX_NOR_3I					0x00001540
+
+
+#define NV20_3D_VERTEX_NOR_3I_XY				0x00001540
+#define NV20_3D_VERTEX_NOR_3I_XY_X__MASK			0x0000ffff
+#define NV20_3D_VERTEX_NOR_3I_XY_X__SHIFT			0
+#define NV20_3D_VERTEX_NOR_3I_XY_Y__MASK			0xffff0000
+#define NV20_3D_VERTEX_NOR_3I_XY_Y__SHIFT			16
+
+#define NV20_3D_VERTEX_NOR_3I_Z					0x00001544
+#define NV20_3D_VERTEX_NOR_3I_Z_Z__MASK				0x0000ffff
+#define NV20_3D_VERTEX_NOR_3I_Z_Z__SHIFT			0
+
+#define NV20_3D_VERTEX_COL_4F					0x00001550
+
+
+#define NV20_3D_VERTEX_COL_4F_R					0x00001550
+
+#define NV20_3D_VERTEX_COL_4F_G					0x00001554
+
+#define NV20_3D_VERTEX_COL_4F_B					0x00001558
+
+#define NV20_3D_VERTEX_COL_4F_A					0x0000155c
+
+#define NV20_3D_VERTEX_COL_3F					0x00001560
+
+
+#define NV20_3D_VERTEX_COL_3F_R					0x00001560
+
+#define NV20_3D_VERTEX_COL_3F_G					0x00001564
+
+#define NV20_3D_VERTEX_COL_3F_B					0x00001568
+
+#define NV20_3D_VERTEX_COL_4I					0x0000156c
+#define NV20_3D_VERTEX_COL_4I_R__MASK				0x000000ff
+#define NV20_3D_VERTEX_COL_4I_R__SHIFT				0
+#define NV20_3D_VERTEX_COL_4I_G__MASK				0x0000ff00
+#define NV20_3D_VERTEX_COL_4I_G__SHIFT				8
+#define NV20_3D_VERTEX_COL_4I_B__MASK				0x00ff0000
+#define NV20_3D_VERTEX_COL_4I_B__SHIFT				16
+#define NV20_3D_VERTEX_COL_4I_A__MASK				0xff000000
+#define NV20_3D_VERTEX_COL_4I_A__SHIFT				24
+
+#define NV20_3D_VERTEX_COL2_3F					0x00001580
+
+
+#define NV20_3D_VERTEX_COL2_3F_R				0x00001580
+
+#define NV20_3D_VERTEX_COL2_3F_G				0x00001584
+
+#define NV20_3D_VERTEX_COL2_3F_B				0x00001588
+
+#define NV20_3D_VERTEX_COL2_3I					0x0000158c
+#define NV20_3D_VERTEX_COL2_3I_R__MASK				0x000000ff
+#define NV20_3D_VERTEX_COL2_3I_R__SHIFT				0
+#define NV20_3D_VERTEX_COL2_3I_G__MASK				0x0000ff00
+#define NV20_3D_VERTEX_COL2_3I_G__SHIFT				8
+#define NV20_3D_VERTEX_COL2_3I_B__MASK				0x00ff0000
+#define NV20_3D_VERTEX_COL2_3I_B__SHIFT				16
+
+#define NV20_3D_VERTEX_TX0_2F					0x00001590
+
+
+#define NV20_3D_VERTEX_TX0_2F_S					0x00001590
+
+#define NV20_3D_VERTEX_TX0_2F_T					0x00001594
+
+#define NV20_3D_VERTEX_TX0_2I					0x00001598
+#define NV20_3D_VERTEX_TX0_2I_S__MASK				0x0000ffff
+#define NV20_3D_VERTEX_TX0_2I_S__SHIFT				0
+#define NV20_3D_VERTEX_TX0_2I_T__MASK				0xffff0000
+#define NV20_3D_VERTEX_TX0_2I_T__SHIFT				16
+
+#define NV20_3D_VERTEX_TX0_4F					0x000015a0
+
+
+#define NV20_3D_VERTEX_TX0_4F_S					0x000015a0
+
+#define NV20_3D_VERTEX_TX0_4F_T					0x000015a4
+
+#define NV20_3D_VERTEX_TX0_4F_R					0x000015a8
+
+#define NV20_3D_VERTEX_TX0_4F_Q					0x000015ac
+
+#define NV20_3D_VERTEX_TX0_4I					0x000015b0
+
+
+#define NV20_3D_VERTEX_TX0_4I_ST				0x000015b0
+#define NV20_3D_VERTEX_TX0_4I_ST_S__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX0_4I_ST_S__SHIFT			0
+#define NV20_3D_VERTEX_TX0_4I_ST_T__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX0_4I_ST_T__SHIFT			16
+
+#define NV20_3D_VERTEX_TX0_4I_RQ				0x000015b4
+#define NV20_3D_VERTEX_TX0_4I_RQ_R__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX0_4I_RQ_R__SHIFT			0
+#define NV20_3D_VERTEX_TX0_4I_RQ_Q__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX0_4I_RQ_Q__SHIFT			16
+
+#define NV20_3D_VERTEX_TX1_2F					0x000015b8
+
+
+#define NV20_3D_VERTEX_TX1_2F_S					0x000015b8
+
+#define NV20_3D_VERTEX_TX1_2F_T					0x000015bc
+
+#define NV20_3D_VERTEX_TX1_2I					0x000015c0
+#define NV20_3D_VERTEX_TX1_2I_S__MASK				0x0000ffff
+#define NV20_3D_VERTEX_TX1_2I_S__SHIFT				0
+#define NV20_3D_VERTEX_TX1_2I_T__MASK				0xffff0000
+#define NV20_3D_VERTEX_TX1_2I_T__SHIFT				16
+
+#define NV20_3D_VERTEX_TX1_4F					0x000015c8
+
+
+#define NV20_3D_VERTEX_TX1_4F_S					0x000015c8
+
+#define NV20_3D_VERTEX_TX1_4F_T					0x000015cc
+
+#define NV20_3D_VERTEX_TX1_4F_R					0x000015d0
+
+#define NV20_3D_VERTEX_TX1_4F_Q					0x000015d4
+
+#define NV20_3D_VERTEX_TX1_4I					0x000015d8
+
+
+#define NV20_3D_VERTEX_TX1_4I_ST				0x000015d8
+#define NV20_3D_VERTEX_TX1_4I_ST_S__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX1_4I_ST_S__SHIFT			0
+#define NV20_3D_VERTEX_TX1_4I_ST_T__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX1_4I_ST_T__SHIFT			16
+
+#define NV20_3D_VERTEX_TX1_4I_RQ				0x000015dc
+#define NV20_3D_VERTEX_TX1_4I_RQ_R__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX1_4I_RQ_R__SHIFT			0
+#define NV20_3D_VERTEX_TX1_4I_RQ_Q__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX1_4I_RQ_Q__SHIFT			16
+
+#define NV20_3D_VERTEX_TX2_2F					0x000015e0
+
+
+#define NV20_3D_VERTEX_TX2_2F_S					0x000015e0
+
+#define NV20_3D_VERTEX_TX2_2F_T					0x000015e4
+
+#define NV20_3D_VERTEX_TX2_2I					0x000015e8
+#define NV20_3D_VERTEX_TX2_2I_S__MASK				0x0000ffff
+#define NV20_3D_VERTEX_TX2_2I_S__SHIFT				0
+#define NV20_3D_VERTEX_TX2_2I_T__MASK				0xffff0000
+#define NV20_3D_VERTEX_TX2_2I_T__SHIFT				16
+
+#define NV20_3D_VERTEX_TX2_4F					0x000015f0
+
+
+#define NV20_3D_VERTEX_TX2_4F_S					0x000015f0
+
+#define NV20_3D_VERTEX_TX2_4F_T					0x000015f4
+
+#define NV20_3D_VERTEX_TX2_4F_R					0x000015f8
+
+#define NV20_3D_VERTEX_TX2_4F_Q					0x000015fc
+
+#define NV20_3D_VERTEX_TX2_4I					0x00001600
+
+
+#define NV20_3D_VERTEX_TX2_4I_ST				0x00001600
+#define NV20_3D_VERTEX_TX2_4I_ST_S__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX2_4I_ST_S__SHIFT			0
+#define NV20_3D_VERTEX_TX2_4I_ST_T__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX2_4I_ST_T__SHIFT			16
+
+#define NV20_3D_VERTEX_TX2_4I_RQ				0x00001604
+#define NV20_3D_VERTEX_TX2_4I_RQ_R__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX2_4I_RQ_R__SHIFT			0
+#define NV20_3D_VERTEX_TX2_4I_RQ_Q__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX2_4I_RQ_Q__SHIFT			16
+
+#define NV20_3D_VERTEX_TX3_2F					0x00001608
+
+
+#define NV20_3D_VERTEX_TX3_2F_S					0x00001608
+
+#define NV20_3D_VERTEX_TX3_2F_T					0x0000160c
+
+#define NV20_3D_VERTEX_TX3_2I					0x00001610
+#define NV20_3D_VERTEX_TX3_2I_S__MASK				0x0000ffff
+#define NV20_3D_VERTEX_TX3_2I_S__SHIFT				0
+#define NV20_3D_VERTEX_TX3_2I_T__MASK				0xffff0000
+#define NV20_3D_VERTEX_TX3_2I_T__SHIFT				16
+
+#define NV20_3D_VERTEX_TX3_4F					0x00001620
+
+
+#define NV20_3D_VERTEX_TX3_4F_S					0x00001620
+
+#define NV20_3D_VERTEX_TX3_4F_T					0x00001624
+
+#define NV20_3D_VERTEX_TX3_4F_R					0x00001628
+
+#define NV20_3D_VERTEX_TX3_4F_Q					0x0000162c
+
+#define NV20_3D_VERTEX_TX3_4I					0x00001630
+
+
+#define NV20_3D_VERTEX_TX3_4I_ST				0x00001630
+#define NV20_3D_VERTEX_TX3_4I_ST_S__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX3_4I_ST_S__SHIFT			0
+#define NV20_3D_VERTEX_TX3_4I_ST_T__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX3_4I_ST_T__SHIFT			16
+
+#define NV20_3D_VERTEX_TX3_4I_RQ				0x00001634
+#define NV20_3D_VERTEX_TX3_4I_RQ_R__MASK			0x0000ffff
+#define NV20_3D_VERTEX_TX3_4I_RQ_R__SHIFT			0
+#define NV20_3D_VERTEX_TX3_4I_RQ_Q__MASK			0xffff0000
+#define NV20_3D_VERTEX_TX3_4I_RQ_Q__SHIFT			16
+
+#define NV20_3D_VERTEX_FOG_1F					0x00001698
+
+#define NV20_3D_EDGEFLAG_ENABLE					0x000016bc
+
+#define NV20_3D_VERTEX_ATTR_4F(i0)			       (0x00001a00 + 0x10*(i0))
+#define NV20_3D_VERTEX_ATTR_4F__ESIZE				0x00000010
+#define NV20_3D_VERTEX_ATTR_4F__LEN				0x00000010
+
+
+#define NV20_3D_VERTEX_ATTR_4F_X(i0)			       (0x00001a00 + 0x10*(i0))
+
+#define NV20_3D_VERTEX_ATTR_4F_Y(i0)			       (0x00001a04 + 0x10*(i0))
+
+#define NV20_3D_VERTEX_ATTR_4F_Z(i0)			       (0x00001a08 + 0x10*(i0))
+
+#define NV20_3D_VERTEX_ATTR_4F_W(i0)			       (0x00001a0c + 0x10*(i0))
+
+
+#define NV20_3D_DMA_VTXBUF0					0x0000019c
+
+#define NV20_3D_DMA_VTXBUF1					0x000001a0
+
+#define NV20_3D_VTXBUF_VALIDATE					0x00001710
+
+
+#define NV20_3D_VTXBUF_OFFSET(i0)			       (0x00001720 + 0x4*(i0))
+#define NV20_3D_VTXBUF_OFFSET_DMA1				0x80000000
+#define NV20_3D_VTXBUF_OFFSET_OFFSET__MASK			0x0fffffff
+#define NV20_3D_VTXBUF_OFFSET_OFFSET__SHIFT			0
+
+#define NV20_3D_VTXBUF_FMT(i0)				       (0x00001760 + 0x4*(i0))
+#define NV20_3D_VTXBUF_FMT_TYPE__MASK				0x0000000f
+#define NV20_3D_VTXBUF_FMT_TYPE__SHIFT				0
+#define NV20_3D_VTXBUF_FMT_TYPE_FLOAT				0x00000002
+#define NV20_3D_VTXBUF_FMT_TYPE_UBYTE				0x00000004
+#define NV20_3D_VTXBUF_FMT_TYPE_USHORT				0x00000005
+#define NV20_3D_VTXBUF_FMT_SIZE__MASK				0x000000f0
+#define NV20_3D_VTXBUF_FMT_SIZE__SHIFT				4
+#define NV20_3D_VTXBUF_FMT_STRIDE__MASK				0x0000ff00
+#define NV20_3D_VTXBUF_FMT_STRIDE__SHIFT			8
+
+#define NV20_3D_VERTEX_BEGIN_END				0x000017fc
+#define NV20_3D_VERTEX_BEGIN_END_STOP				0x00000000
+#define NV20_3D_VERTEX_BEGIN_END_POINTS				0x00000001
+#define NV20_3D_VERTEX_BEGIN_END_LINES				0x00000002
+#define NV20_3D_VERTEX_BEGIN_END_LINE_LOOP			0x00000003
+#define NV20_3D_VERTEX_BEGIN_END_LINE_STRIP			0x00000004
+#define NV20_3D_VERTEX_BEGIN_END_TRIANGLES			0x00000005
+#define NV20_3D_VERTEX_BEGIN_END_TRIANGLE_STRIP			0x00000006
+#define NV20_3D_VERTEX_BEGIN_END_TRIANGLE_FAN			0x00000007
+#define NV20_3D_VERTEX_BEGIN_END_QUADS				0x00000008
+#define NV20_3D_VERTEX_BEGIN_END_QUAD_STRIP			0x00000009
+#define NV20_3D_VERTEX_BEGIN_END_POLYGON			0x0000000a
+
+#define NV20_3D_VTXBUF_ELEMENT_U16				0x00001800
+#define NV20_3D_VTXBUF_ELEMENT_U16_I0__MASK			0x0000ffff
+#define NV20_3D_VTXBUF_ELEMENT_U16_I0__SHIFT			0
+#define NV20_3D_VTXBUF_ELEMENT_U16_I1__MASK			0xffff0000
+#define NV20_3D_VTXBUF_ELEMENT_U16_I1__SHIFT			16
+
+#define NV20_3D_VTXBUF_ELEMENT_U32				0x00001808
+
+#define NV20_3D_VTXBUF_BATCH					0x00001810
+#define NV20_3D_VTXBUF_BATCH_OFFSET__MASK			0x00ffffff
+#define NV20_3D_VTXBUF_BATCH_OFFSET__SHIFT			0
+#define NV20_3D_VTXBUF_BATCH_COUNT__MASK			0xff000000
+#define NV20_3D_VTXBUF_BATCH_COUNT__SHIFT			24
+
+#define NV20_3D_VTXBUF_DATA					0x00001818
+
+
+#define NV20_3D_ENGINE						0x00001e94
+#define NV20_3D_ENGINE_VP					0x00000002
+#define NV20_3D_ENGINE_FIXED					0x00000004
+
+#define NV20_3D_VP_UPLOAD_INST(i0)			       (0x00000b00 + 0x4*(i0))
+#define NV20_3D_VP_UPLOAD_INST__ESIZE				0x00000004
+#define NV20_3D_VP_UPLOAD_INST__LEN				0x00000004
+
+#define NV20_3D_VP_UPLOAD_CONST(i0)			       (0x00000b80 + 0x4*(i0))
+#define NV20_3D_VP_UPLOAD_CONST__ESIZE				0x00000004
+#define NV20_3D_VP_UPLOAD_CONST__LEN				0x00000004
+
+#define NV20_3D_VP_UPLOAD_FROM_ID				0x00001e9c
+
+#define NV20_3D_VP_START_FROM_ID				0x00001ea0
+
+#define NV20_3D_VP_UPLOAD_CONST_ID				0x00001ea4
+
+
+
+#define NV20_3D_MODELVIEW_MATRIX(i0, i1)		       (0x00000480 + 0x40*(i0) + 0x4*(i1))
+#define NV20_3D_MODELVIEW_MATRIX__ESIZE				0x00000004
+#define NV20_3D_MODELVIEW_MATRIX__LEN				0x00000010
+
+#define NV20_3D_INVERSE_MODELVIEW_MATRIX(i0, i1)	       (0x00000580 + 0x40*(i0) + 0x4*(i1))
+#define NV20_3D_INVERSE_MODELVIEW_MATRIX__ESIZE			0x00000004
+#define NV20_3D_INVERSE_MODELVIEW_MATRIX__LEN			0x00000010
+
+#define NV20_3D_PROJECTION_MATRIX(i0)			       (0x00000680 + 0x4*(i0))
+#define NV20_3D_PROJECTION_MATRIX__ESIZE			0x00000004
+#define NV20_3D_PROJECTION_MATRIX__LEN				0x00000010
+
+#define NV20_3D_VIEWPORT_TRANSLATE				0x00000a20
+
+
+#define NV20_3D_VIEWPORT_TRANSLATE_X				0x00000a20
+
+#define NV20_3D_VIEWPORT_TRANSLATE_Y				0x00000a24
+
+#define NV20_3D_VIEWPORT_TRANSLATE_Z				0x00000a28
+
+#define NV20_3D_VIEWPORT_TRANSLATE_W				0x00000a2c
+
+#define NV20_3D_VIEWPORT_SCALE					0x00000af0
+
+
+#define NV20_3D_VIEWPORT_SCALE_X				0x00000af0
+
+#define NV20_3D_VIEWPORT_SCALE_Y				0x00000af4
+
+#define NV20_3D_VIEWPORT_SCALE_Z				0x00000af8
+
+#define NV20_3D_VIEWPORT_SCALE_W				0x00000afc
+
+
+#define NV20_3D_NORMALIZE_ENABLE				0x000003a4
+
+#define NV20_3D_SEPARATE_SPECULAR_ENABLE			0x000003b8
+
+#define NV20_3D_LIGHT_MODEL_TWO_SIDE_ENABLE			0x000017c4
+
+#define NV20_3D_LIGHT_MODEL					0x00000294
+#define NV20_3D_LIGHT_MODEL_VIEWER__MASK			0x00030000
+#define NV20_3D_LIGHT_MODEL_VIEWER__SHIFT			16
+#define NV20_3D_LIGHT_MODEL_VIEWER_NONLOCAL			0x00020000
+#define NV20_3D_LIGHT_MODEL_VIEWER_LOCAL			0x00030000
+#define NV20_3D_LIGHT_MODEL_SEPARATE_SPECULAR			0x00000001
+
+#define NV20_3D_ENABLED_LIGHTS					0x000003bc
+#define NV20_3D_ENABLED_LIGHTS_0__MASK				0x00000003
+#define NV20_3D_ENABLED_LIGHTS_0__SHIFT				0
+#define NV20_3D_ENABLED_LIGHTS_0_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_0_NONPOSITIONAL			0x00000001
+#define NV20_3D_ENABLED_LIGHTS_0_POSITIONAL			0x00000002
+#define NV20_3D_ENABLED_LIGHTS_0_DIRECTIONAL			0x00000003
+#define NV20_3D_ENABLED_LIGHTS_1__MASK				0x0000000c
+#define NV20_3D_ENABLED_LIGHTS_1__SHIFT				2
+#define NV20_3D_ENABLED_LIGHTS_1_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_1_NONPOSITIONAL			0x00000004
+#define NV20_3D_ENABLED_LIGHTS_1_POSITIONAL			0x00000008
+#define NV20_3D_ENABLED_LIGHTS_1_DIRECTIONAL			0x0000000c
+#define NV20_3D_ENABLED_LIGHTS_2__MASK				0x00000030
+#define NV20_3D_ENABLED_LIGHTS_2__SHIFT				4
+#define NV20_3D_ENABLED_LIGHTS_2_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_2_NONPOSITIONAL			0x00000010
+#define NV20_3D_ENABLED_LIGHTS_2_POSITIONAL			0x00000020
+#define NV20_3D_ENABLED_LIGHTS_2_DIRECTIONAL			0x00000030
+#define NV20_3D_ENABLED_LIGHTS_3__MASK				0x000000c0
+#define NV20_3D_ENABLED_LIGHTS_3__SHIFT				6
+#define NV20_3D_ENABLED_LIGHTS_3_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_3_NONPOSITIONAL			0x00000040
+#define NV20_3D_ENABLED_LIGHTS_3_POSITIONAL			0x00000080
+#define NV20_3D_ENABLED_LIGHTS_3_DIRECTIONAL			0x000000c0
+#define NV20_3D_ENABLED_LIGHTS_4__MASK				0x00000300
+#define NV20_3D_ENABLED_LIGHTS_4__SHIFT				8
+#define NV20_3D_ENABLED_LIGHTS_4_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_4_NONPOSITIONAL			0x00000100
+#define NV20_3D_ENABLED_LIGHTS_4_POSITIONAL			0x00000200
+#define NV20_3D_ENABLED_LIGHTS_4_DIRECTIONAL			0x00000300
+#define NV20_3D_ENABLED_LIGHTS_5__MASK				0x00000c00
+#define NV20_3D_ENABLED_LIGHTS_5__SHIFT				10
+#define NV20_3D_ENABLED_LIGHTS_5_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_5_NONPOSITIONAL			0x00000400
+#define NV20_3D_ENABLED_LIGHTS_5_POSITIONAL			0x00000800
+#define NV20_3D_ENABLED_LIGHTS_5_DIRECTIONAL			0x00000c00
+#define NV20_3D_ENABLED_LIGHTS_6__MASK				0x00003000
+#define NV20_3D_ENABLED_LIGHTS_6__SHIFT				12
+#define NV20_3D_ENABLED_LIGHTS_6_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_6_NONPOSITIONAL			0x00001000
+#define NV20_3D_ENABLED_LIGHTS_6_POSITIONAL			0x00002000
+#define NV20_3D_ENABLED_LIGHTS_6_DIRECTIONAL			0x00003000
+#define NV20_3D_ENABLED_LIGHTS_7__MASK				0x0000c000
+#define NV20_3D_ENABLED_LIGHTS_7__SHIFT				14
+#define NV20_3D_ENABLED_LIGHTS_7_DISABLED			0x00000000
+#define NV20_3D_ENABLED_LIGHTS_7_NONPOSITIONAL			0x00004000
+#define NV20_3D_ENABLED_LIGHTS_7_POSITIONAL			0x00008000
+#define NV20_3D_ENABLED_LIGHTS_7_DIRECTIONAL			0x0000c000
+
+#define NV20_3D_COLOR_MATERIAL					0x00000298
+#define NV20_3D_COLOR_MATERIAL_FRONT_EMISSION__MASK		0x00000003
+#define NV20_3D_COLOR_MATERIAL_FRONT_EMISSION__SHIFT		0
+#define NV20_3D_COLOR_MATERIAL_FRONT_EMISSION_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_FRONT_EMISSION_COL1		0x00000001
+#define NV20_3D_COLOR_MATERIAL_FRONT_EMISSION_COL2		0x00000002
+#define NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT__MASK		0x0000000c
+#define NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT__SHIFT		2
+#define NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT_COL1		0x00000004
+#define NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT_COL2		0x00000008
+#define NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE__MASK		0x00000030
+#define NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE__SHIFT		4
+#define NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE_COL1		0x00000010
+#define NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE_COL2		0x00000020
+#define NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR__MASK		0x000000c0
+#define NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR__SHIFT		6
+#define NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR_COL1		0x00000040
+#define NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR_COL2		0x00000080
+#define NV20_3D_COLOR_MATERIAL_BACK_EMISSION__MASK		0x00000300
+#define NV20_3D_COLOR_MATERIAL_BACK_EMISSION__SHIFT		8
+#define NV20_3D_COLOR_MATERIAL_BACK_EMISSION_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_BACK_EMISSION_COL1		0x00000100
+#define NV20_3D_COLOR_MATERIAL_BACK_EMISSION_COL2		0x00000200
+#define NV20_3D_COLOR_MATERIAL_BACK_AMBIENT__MASK		0x00000c00
+#define NV20_3D_COLOR_MATERIAL_BACK_AMBIENT__SHIFT		10
+#define NV20_3D_COLOR_MATERIAL_BACK_AMBIENT_OFF			0x00000000
+#define NV20_3D_COLOR_MATERIAL_BACK_AMBIENT_COL1		0x00000400
+#define NV20_3D_COLOR_MATERIAL_BACK_AMBIENT_COL2		0x00000800
+#define NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE__MASK		0x00003000
+#define NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE__SHIFT		12
+#define NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE_OFF			0x00000000
+#define NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE_COL1		0x00001000
+#define NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE_COL2		0x00002000
+#define NV20_3D_COLOR_MATERIAL_BACK_SPECULAR__MASK		0x0000c000
+#define NV20_3D_COLOR_MATERIAL_BACK_SPECULAR__SHIFT		14
+#define NV20_3D_COLOR_MATERIAL_BACK_SPECULAR_OFF		0x00000000
+#define NV20_3D_COLOR_MATERIAL_BACK_SPECULAR_COL1		0x00004000
+#define NV20_3D_COLOR_MATERIAL_BACK_SPECULAR_COL2		0x00008000
+
+#define NV20_3D_MATERIAL_FACTOR_FRONT				0x000003a8
+
+
+#define NV20_3D_MATERIAL_FACTOR_FRONT_R				0x000003a8
+
+#define NV20_3D_MATERIAL_FACTOR_FRONT_G				0x000003ac
+
+#define NV20_3D_MATERIAL_FACTOR_FRONT_B				0x000003b0
+
+#define NV20_3D_MATERIAL_FACTOR_BACK				0x000017b0
+
+
+#define NV20_3D_MATERIAL_FACTOR_BACK_R				0x000017b0
+
+#define NV20_3D_MATERIAL_FACTOR_BACK_G				0x000017b4
+
+#define NV20_3D_MATERIAL_FACTOR_BACK_B				0x000017b8
+
+#define NV20_3D_MATERIAL_FACTOR_FRONT_A				0x000003b4
+
+#define NV20_3D_MATERIAL_FACTOR_BACK_A				0x000017ac
+
+#define NV20_3D_LIGHT_MODEL_FRONT_AMBIENT			0x00000a10
+
+
+#define NV20_3D_LIGHT_MODEL_FRONT_AMBIENT_R			0x00000a10
+
+#define NV20_3D_LIGHT_MODEL_FRONT_AMBIENT_G			0x00000a14
+
+#define NV20_3D_LIGHT_MODEL_FRONT_AMBIENT_B			0x00000a18
+
+#define NV20_3D_LIGHT_MODEL_BACK_AMBIENT			0x000017a0
+
+
+#define NV20_3D_LIGHT_MODEL_BACK_AMBIENT_R			0x000017a0
+
+#define NV20_3D_LIGHT_MODEL_BACK_AMBIENT_G			0x000017a4
+
+#define NV20_3D_LIGHT_MODEL_BACK_AMBIENT_B			0x000017a8
+
+#define NV20_3D_FRONT_MATERIAL_SHININESS(i0)		       (0x000009e0 + 0x4*(i0))
+#define NV20_3D_FRONT_MATERIAL_SHININESS__ESIZE			0x00000004
+#define NV20_3D_FRONT_MATERIAL_SHININESS__LEN			0x00000006
+
+#define NV20_3D_BACK_MATERIAL_SHININESS(i0)		       (0x00001e28 + 0x4*(i0))
+#define NV20_3D_BACK_MATERIAL_SHININESS__ESIZE			0x00000004
+#define NV20_3D_BACK_MATERIAL_SHININESS__LEN			0x00000006
+
+
+
+#define NV20_3D_LIGHT_FRONT_AMBIENT(i0)			       (0x00001000 + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_FRONT_AMBIENT_R(i0)		       (0x00001000 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_AMBIENT_G(i0)		       (0x00001004 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_AMBIENT_B(i0)		       (0x00001008 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_DIFFUSE(i0)			       (0x0000100c + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_FRONT_DIFFUSE_R(i0)		       (0x0000100c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_DIFFUSE_G(i0)		       (0x00001010 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_DIFFUSE_B(i0)		       (0x00001014 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_SPECULAR(i0)		       (0x00001018 + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_FRONT_SPECULAR_R(i0)		       (0x00001018 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_SPECULAR_G(i0)		       (0x0000101c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_FRONT_SPECULAR_B(i0)		       (0x00001020 + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_BACK_AMBIENT(i0)			       (0x00000c00 + 0x40*(i0))
+
+
+#define NV20_3D_LIGHT_BACK_AMBIENT_R(i0)		       (0x00000c00 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_AMBIENT_G(i0)		       (0x00000c04 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_AMBIENT_B(i0)		       (0x00000c08 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_DIFFUSE(i0)			       (0x00000c0c + 0x40*(i0))
+
+
+#define NV20_3D_LIGHT_BACK_DIFFUSE_R(i0)		       (0x00000c0c + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_DIFFUSE_G(i0)		       (0x00000c10 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_DIFFUSE_B(i0)		       (0x00000c14 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_SPECULAR(i0)			       (0x00000c18 + 0x40*(i0))
+
+
+#define NV20_3D_LIGHT_BACK_SPECULAR_R(i0)		       (0x00000c18 + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_SPECULAR_G(i0)		       (0x00000c1c + 0x40*(i0))
+
+#define NV20_3D_LIGHT_BACK_SPECULAR_B(i0)		       (0x00000c20 + 0x40*(i0))
+
+
+#define NV20_3D_LIGHT_HALF_VECTOR(i0)			       (0x00001028 + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_HALF_VECTOR_X(i0)			       (0x00001028 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_HALF_VECTOR_Y(i0)			       (0x0000102c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_HALF_VECTOR_Z(i0)			       (0x00001030 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_DIRECTION(i0)			       (0x00001034 + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_DIRECTION_X(i0)			       (0x00001034 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_DIRECTION_Y(i0)			       (0x00001038 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_DIRECTION_Z(i0)			       (0x0000103c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_SPOT_CUTOFF(i0, i1)		       (0x00001040 + 0x80*(i0) + 0x4*(i1))
+#define NV20_3D_LIGHT_SPOT_CUTOFF__ESIZE			0x00000004
+#define NV20_3D_LIGHT_SPOT_CUTOFF__LEN				0x00000007
+
+#define NV20_3D_LIGHT_POSITION(i0)			       (0x0000105c + 0x80*(i0))
+
+
+#define NV20_3D_LIGHT_POSITION_X(i0)			       (0x0000105c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_POSITION_Y(i0)			       (0x00001060 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_POSITION_Z(i0)			       (0x00001064 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_ATTENUATION(i0)			       (0x00001068 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_ATTENUATION_CONSTANT(i0)		       (0x00001068 + 0x80*(i0))
+
+#define NV20_3D_LIGHT_ATTENUATION_LINEAR(i0)		       (0x0000106c + 0x80*(i0))
+
+#define NV20_3D_LIGHT_ATTENUATION_QUADRATIC(i0)		       (0x00001070 + 0x80*(i0))
+
+
+#define NV20_3D_FOG_MODE					0x0000029c
+#define NV20_3D_FOG_MODE_LINEAR_UNSIGNED			0x00000804
+#define NV20_3D_FOG_MODE_LINEAR_SIGNED				0x00002601
+#define NV20_3D_FOG_MODE_EXP_UNSIGNED				0x00000802
+#define NV20_3D_FOG_MODE_EXP_SIGNED				0x00000800
+#define NV20_3D_FOG_MODE_EXP2_UNSIGNED				0x00000803
+#define NV20_3D_FOG_MODE_EXP2_SIGNED				0x00000801
+
+#define NV20_3D_FOG_COORD					0x000002a0
+#define NV20_3D_FOG_COORD_DIST_RADIAL				0x00000001
+#define NV20_3D_FOG_COORD_DIST_ORTHOGONAL			0x00000002
+#define NV20_3D_FOG_COORD_DIST_ORTHOGONAL_ABS			0x00000003
+#define NV20_3D_FOG_COORD_FOG					0x00000006
+
+#define NV20_3D_FOG_ENABLE					0x000002a4
+
+#define NV20_3D_FOG_COLOR					0x000002a8
+#define NV20_3D_FOG_COLOR_R__MASK				0x000000ff
+#define NV20_3D_FOG_COLOR_R__SHIFT				0
+#define NV20_3D_FOG_COLOR_G__MASK				0x0000ff00
+#define NV20_3D_FOG_COLOR_G__SHIFT				8
+#define NV20_3D_FOG_COLOR_B__MASK				0x00ff0000
+#define NV20_3D_FOG_COLOR_B__SHIFT				16
+#define NV20_3D_FOG_COLOR_A__MASK				0xff000000
+#define NV20_3D_FOG_COLOR_A__SHIFT				24
+
+#define NV20_3D_FOG_COEFF(i0)				       (0x000009c0 + 0x4*(i0))
+#define NV20_3D_FOG_COEFF__ESIZE				0x00000004
+#define NV20_3D_FOG_COEFF__LEN					0x00000003
+
+
+
+#define NV20_3D_TEX_GEN_MODE(i0, i1)			       (0x000003c0 + 0x10*(i0) + 0x4*(i1))
+#define NV20_3D_TEX_GEN_MODE__ESIZE				0x00000004
+#define NV20_3D_TEX_GEN_MODE__LEN				0x00000004
+#define NV20_3D_TEX_GEN_MODE_FALSE				0x00000000
+#define NV20_3D_TEX_GEN_MODE_EYE_LINEAR				0x00002400
+#define NV20_3D_TEX_GEN_MODE_OBJECT_LINEAR			0x00002401
+#define NV20_3D_TEX_GEN_MODE_SPHERE_MAP				0x00002402
+#define NV20_3D_TEX_GEN_MODE_NORMAL_MAP				0x00008511
+#define NV20_3D_TEX_GEN_MODE_REFLECTION_MAP			0x00008512
+
+
+#define NV20_3D_TEX_GEN_COEFF(i0, i1)			       (0x00000840 + 0x40*(i0) + 0x10*(i1))
+#define NV20_3D_TEX_GEN_COEFF__ESIZE				0x00000010
+#define NV20_3D_TEX_GEN_COEFF__LEN				0x00000004
+
+#define NV20_3D_TEX_GEN_COEFF_A(i0, i1)			       (0x00000840 + 0x40*(i0) + 0x10*(i1))
+
+#define NV20_3D_TEX_GEN_COEFF_B(i0, i1)			       (0x00000844 + 0x40*(i0) + 0x10*(i1))
+
+#define NV20_3D_TEX_GEN_COEFF_C(i0, i1)			       (0x00000848 + 0x40*(i0) + 0x10*(i1))
+
+#define NV20_3D_TEX_GEN_COEFF_D(i0, i1)			       (0x0000084c + 0x40*(i0) + 0x10*(i1))
+
+#define NV20_3D_TEX_MATRIX_ENABLE(i0)			       (0x00000420 + 0x4*(i0))
+#define NV20_3D_TEX_MATRIX_ENABLE__ESIZE			0x00000004
+#define NV20_3D_TEX_MATRIX_ENABLE__LEN				0x00000004
+
+
+#define NV20_3D_TEX_MATRIX(i0, i1)			       (0x000006c0 + 0x40*(i0) + 0x4*(i1))
+#define NV20_3D_TEX_MATRIX__ESIZE				0x00000004
+#define NV20_3D_TEX_MATRIX__LEN					0x00000010
+
+#define NV20_3D_TEX_SHADER_CULL_MODE				0x000017f8
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_S__MASK		0x00000001
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_S__SHIFT		0
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_S_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_S_LESS			0x00000001
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_T__MASK		0x00000002
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_T__SHIFT		1
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_T_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_T_LESS			0x00000002
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_R__MASK		0x00000004
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_R__SHIFT		2
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_R_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_R_LESS			0x00000004
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_Q__MASK		0x00000008
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_Q__SHIFT		3
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_Q_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX0_Q_LESS			0x00000008
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_S__MASK		0x00000010
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_S__SHIFT		4
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_S_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_S_LESS			0x00000010
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_T__MASK		0x00000020
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_T__SHIFT		5
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_T_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_T_LESS			0x00000020
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_R__MASK		0x00000040
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_R__SHIFT		6
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_R_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_R_LESS			0x00000040
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_Q__MASK		0x00000080
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_Q__SHIFT		7
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_Q_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX1_Q_LESS			0x00000080
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_S__MASK		0x00000100
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_S__SHIFT		8
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_S_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_S_LESS			0x00000100
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_T__MASK		0x00000200
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_T__SHIFT		9
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_T_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_T_LESS			0x00000200
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_R__MASK		0x00000400
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_R__SHIFT		10
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_R_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_R_LESS			0x00000400
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_Q__MASK		0x00000800
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_Q__SHIFT		11
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_Q_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX2_Q_LESS			0x00000800
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_S__MASK		0x00001000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_S__SHIFT		12
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_S_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_S_LESS			0x00001000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_T__MASK		0x00002000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_T__SHIFT		13
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_T_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_T_LESS			0x00002000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_R__MASK		0x00004000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_R__SHIFT		14
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_R_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_R_LESS			0x00004000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_Q__MASK		0x00008000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_Q__SHIFT		15
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_Q_GEQUAL		0x00000000
+#define NV20_3D_TEX_SHADER_CULL_MODE_TX3_Q_LESS			0x00008000
+
+#define NV20_3D_TEX_SHADER_CONST_EYE				0x0000181c
+
+
+#define NV20_3D_TEX_SHADER_CONST_EYE_X				0x0000181c
+
+#define NV20_3D_TEX_SHADER_CONST_EYE_Y				0x00001820
+
+#define NV20_3D_TEX_SHADER_CONST_EYE_Z				0x00001824
+
+
+#define NV20_3D_TEX_SHADER_OFFSET_MATRIX(i0, i1)	       (0x00001b28 + 0x40*(i0) + 0x4*(i1))
+#define NV20_3D_TEX_SHADER_OFFSET_MATRIX__ESIZE			0x00000004
+#define NV20_3D_TEX_SHADER_OFFSET_MATRIX__LEN			0x00000004
+
+#define NV20_3D_TEX_RCOMP					0x00001e6c
+#define NV20_3D_TEX_RCOMP_NEVER					0x00000000
+#define NV20_3D_TEX_RCOMP_GREATER				0x00000001
+#define NV20_3D_TEX_RCOMP_EQUAL					0x00000002
+#define NV20_3D_TEX_RCOMP_GEQUAL				0x00000003
+#define NV20_3D_TEX_RCOMP_LESS					0x00000004
+#define NV20_3D_TEX_RCOMP_NOTEQUAL				0x00000005
+#define NV20_3D_TEX_RCOMP_LEQUAL				0x00000006
+#define NV20_3D_TEX_RCOMP_ALWAYS				0x00000007
+
+#define NV20_3D_TEX_SHADER_OP					0x00001e70
+#define NV20_3D_TEX_SHADER_OP_TX0__MASK				0x0000001f
+#define NV20_3D_TEX_SHADER_OP_TX0__SHIFT			0
+#define NV20_3D_TEX_SHADER_OP_TX0_NONE				0x00000000
+#define NV20_3D_TEX_SHADER_OP_TX0_TEXTURE_2D			0x00000001
+#define NV20_3D_TEX_SHADER_OP_TX0_PASS_THROUGH			0x00000004
+#define NV20_3D_TEX_SHADER_OP_TX0_CULL_FRAGMENT			0x00000005
+#define NV20_3D_TEX_SHADER_OP_TX0_OFFSET_TEXTURE_2D		0x00000006
+#define NV20_3D_TEX_SHADER_OP_TX0_DOT_PRODUCT_TEXTURE_2D	0x00000009
+#define NV20_3D_TEX_SHADER_OP_TX0_DOT_PRODUCT_DEPTH_REPLACE	0x0000000a
+#define NV20_3D_TEX_SHADER_OP_TX0_DEPENDANT_AR_TEXTURE_2D	0x0000000f
+#define NV20_3D_TEX_SHADER_OP_TX0_DEPENDANT_GB_TEXTURE_2D	0x00000010
+#define NV20_3D_TEX_SHADER_OP_TX0_DOT_PRODUCT			0x00000011
+#define NV20_3D_TEX_SHADER_OP_TX1__MASK				0x000003e0
+#define NV20_3D_TEX_SHADER_OP_TX1__SHIFT			5
+#define NV20_3D_TEX_SHADER_OP_TX1_NONE				0x00000000
+#define NV20_3D_TEX_SHADER_OP_TX1_TEXTURE_2D			0x00000020
+#define NV20_3D_TEX_SHADER_OP_TX1_PASS_THROUGH			0x00000080
+#define NV20_3D_TEX_SHADER_OP_TX1_CULL_FRAGMENT			0x000000a0
+#define NV20_3D_TEX_SHADER_OP_TX1_OFFSET_TEXTURE_2D		0x000000c0
+#define NV20_3D_TEX_SHADER_OP_TX1_DOT_PRODUCT_TEXTURE_2D	0x00000120
+#define NV20_3D_TEX_SHADER_OP_TX1_DOT_PRODUCT_DEPTH_REPLACE	0x00000140
+#define NV20_3D_TEX_SHADER_OP_TX1_DEPENDANT_AR_TEXTURE_2D	0x000001e0
+#define NV20_3D_TEX_SHADER_OP_TX1_DEPENDANT_GB_TEXTURE_2D	0x00000200
+#define NV20_3D_TEX_SHADER_OP_TX1_DOT_PRODUCT			0x00000220
+#define NV20_3D_TEX_SHADER_OP_TX2__MASK				0x00007c00
+#define NV20_3D_TEX_SHADER_OP_TX2__SHIFT			10
+#define NV20_3D_TEX_SHADER_OP_TX2_NONE				0x00000000
+#define NV20_3D_TEX_SHADER_OP_TX2_TEXTURE_2D			0x00000400
+#define NV20_3D_TEX_SHADER_OP_TX2_PASS_THROUGH			0x00001000
+#define NV20_3D_TEX_SHADER_OP_TX2_CULL_FRAGMENT			0x00001400
+#define NV20_3D_TEX_SHADER_OP_TX2_OFFSET_TEXTURE_2D		0x00001800
+#define NV20_3D_TEX_SHADER_OP_TX2_DOT_PRODUCT_TEXTURE_2D	0x00002400
+#define NV20_3D_TEX_SHADER_OP_TX2_DOT_PRODUCT_DEPTH_REPLACE	0x00002800
+#define NV20_3D_TEX_SHADER_OP_TX2_DEPENDANT_AR_TEXTURE_2D	0x00003c00
+#define NV20_3D_TEX_SHADER_OP_TX2_DEPENDANT_GB_TEXTURE_2D	0x00004000
+#define NV20_3D_TEX_SHADER_OP_TX2_DOT_PRODUCT			0x00004400
+#define NV20_3D_TEX_SHADER_OP_TX3__MASK				0x000f8000
+#define NV20_3D_TEX_SHADER_OP_TX3__SHIFT			15
+#define NV20_3D_TEX_SHADER_OP_TX3_NONE				0x00000000
+#define NV20_3D_TEX_SHADER_OP_TX3_TEXTURE_2D			0x00008000
+#define NV20_3D_TEX_SHADER_OP_TX3_PASS_THROUGH			0x00020000
+#define NV20_3D_TEX_SHADER_OP_TX3_CULL_FRAGMENT			0x00028000
+#define NV20_3D_TEX_SHADER_OP_TX3_OFFSET_TEXTURE_2D		0x00030000
+#define NV20_3D_TEX_SHADER_OP_TX3_DOT_PRODUCT_TEXTURE_2D	0x00048000
+#define NV20_3D_TEX_SHADER_OP_TX3_DOT_PRODUCT_DEPTH_REPLACE	0x00050000
+#define NV20_3D_TEX_SHADER_OP_TX3_DEPENDANT_AR_TEXTURE_2D	0x00078000
+#define NV20_3D_TEX_SHADER_OP_TX3_DEPENDANT_GB_TEXTURE_2D	0x00080000
+#define NV20_3D_TEX_SHADER_OP_TX3_DOT_PRODUCT			0x00088000
+
+#define NV20_3D_TEX_SHADER_DOTMAPPING				0x00001e74
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX0__MASK			0x0000000f
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX0__SHIFT		0
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX1__MASK			0x000000f0
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX1__SHIFT		4
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX2__MASK			0x00000f00
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX2__SHIFT		8
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX3__MASK			0x0000f000
+#define NV20_3D_TEX_SHADER_DOTMAPPING_TX3__SHIFT		12
+
+#define NV20_3D_TEX_SHADER_PREVIOUS				0x00001e78
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX0__MASK			0x00000f00
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX0__SHIFT			8
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX1__MASK			0x0000f000
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX1__SHIFT			12
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX2__MASK			0x00030000
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX2__SHIFT			16
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX3__MASK			0x00300000
+#define NV20_3D_TEX_SHADER_PREVIOUS_TX3__SHIFT			20
+
+#define NV20_3D_TEX(i0)					       (0x00000000 + 0x40*(i0))
+#define NV20_3D_TEX__ESIZE					0x00000040
+#define NV20_3D_TEX__LEN					0x00000004
+
+#define NV20_3D_TEX_OFFSET(i0)				       (0x00001b00 + 0x40*(i0))
+
+#define NV20_3D_TEX_FORMAT(i0)				       (0x00001b04 + 0x40*(i0))
+#define NV20_3D_TEX_FORMAT_DMA0					0x00000001
+#define NV20_3D_TEX_FORMAT_DMA1					0x00000002
+#define NV20_3D_TEX_FORMAT_CUBIC				0x00000004
+#define NV20_3D_TEX_FORMAT_NO_BORDER				0x00000008
+#define NV20_3D_TEX_FORMAT_DIMS__MASK				0x000000f0
+#define NV20_3D_TEX_FORMAT_DIMS__SHIFT				4
+#define NV20_3D_TEX_FORMAT_DIMS_1D				0x00000010
+#define NV20_3D_TEX_FORMAT_DIMS_2D				0x00000020
+#define NV20_3D_TEX_FORMAT_DIMS_3D				0x00000030
+#define NV20_3D_TEX_FORMAT_FORMAT__MASK				0x0000ff00
+#define NV20_3D_TEX_FORMAT_FORMAT__SHIFT			8
+#define NV20_3D_TEX_FORMAT_FORMAT_L8				0x00000000
+#define NV20_3D_TEX_FORMAT_FORMAT_I8				0x00000100
+#define NV20_3D_TEX_FORMAT_FORMAT_A1R5G5B5			0x00000200
+#define NV20_3D_TEX_FORMAT_FORMAT_A4R4G4B4			0x00000400
+#define NV20_3D_TEX_FORMAT_FORMAT_R5G6B5			0x00000500
+#define NV20_3D_TEX_FORMAT_FORMAT_A8R8G8B8			0x00000600
+#define NV20_3D_TEX_FORMAT_FORMAT_X8R8G8B8			0x00000700
+#define NV20_3D_TEX_FORMAT_FORMAT_INDEX8			0x00000b00
+#define NV20_3D_TEX_FORMAT_FORMAT_DXT1				0x00000c00
+#define NV20_3D_TEX_FORMAT_FORMAT_DXT3				0x00000e00
+#define NV20_3D_TEX_FORMAT_FORMAT_DXT5				0x00000f00
+#define NV20_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT			0x00001000
+#define NV20_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT			0x00001100
+#define NV20_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT			0x00001200
+#define NV20_3D_TEX_FORMAT_FORMAT_L8_RECT			0x00001300
+#define NV20_3D_TEX_FORMAT_FORMAT_DSDT8_RECT			0x00001700
+#define NV20_3D_TEX_FORMAT_FORMAT_A8L8				0x00001a00
+#define NV20_3D_TEX_FORMAT_FORMAT_I8_RECT			0x00001b00
+#define NV20_3D_TEX_FORMAT_FORMAT_A4R4G4B4_RECT			0x00001d00
+#define NV20_3D_TEX_FORMAT_FORMAT_R8G8B8_RECT			0x00001e00
+#define NV20_3D_TEX_FORMAT_FORMAT_A8L8_RECT			0x00002000
+#define NV20_3D_TEX_FORMAT_FORMAT_Z24				0x00002a00
+#define NV20_3D_TEX_FORMAT_FORMAT_Z24_RECT			0x00002b00
+#define NV20_3D_TEX_FORMAT_FORMAT_Z16				0x00002c00
+#define NV20_3D_TEX_FORMAT_FORMAT_Z16_RECT			0x00002d00
+#define NV20_3D_TEX_FORMAT_FORMAT_DSDT8				0x00002800
+#define NV20_3D_TEX_FORMAT_FORMAT_HILO16			0x00003300
+#define NV20_3D_TEX_FORMAT_FORMAT_HILO16_RECT			0x00003600
+#define NV20_3D_TEX_FORMAT_FORMAT_HILO8				0x00004400
+#define NV20_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8			0x00004500
+#define NV20_3D_TEX_FORMAT_FORMAT_HILO8_RECT			0x00004600
+#define NV20_3D_TEX_FORMAT_FORMAT_SIGNED_HILO8_RECT		0x00004700
+#define NV20_3D_TEX_FORMAT_MIPMAP				0x00080000
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_U__MASK			0x00f00000
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_U__SHIFT			20
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_V__MASK			0x0f000000
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_V__SHIFT			24
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_W__MASK			0xf0000000
+#define NV20_3D_TEX_FORMAT_BASE_SIZE_W__SHIFT			28
+
+#define NV20_3D_TEX_WRAP(i0)				       (0x00001b08 + 0x40*(i0))
+#define NV20_3D_TEX_WRAP_S__MASK				0x000000ff
+#define NV20_3D_TEX_WRAP_S__SHIFT				0
+#define NV20_3D_TEX_WRAP_S_REPEAT				0x00000001
+#define NV20_3D_TEX_WRAP_S_MIRRORED_REPEAT			0x00000002
+#define NV20_3D_TEX_WRAP_S_CLAMP_TO_EDGE			0x00000003
+#define NV20_3D_TEX_WRAP_S_CLAMP_TO_BORDER			0x00000004
+#define NV20_3D_TEX_WRAP_S_CLAMP				0x00000005
+#define NV20_3D_TEX_WRAP_T__MASK				0x00000f00
+#define NV20_3D_TEX_WRAP_T__SHIFT				8
+#define NV20_3D_TEX_WRAP_T_REPEAT				0x00000100
+#define NV20_3D_TEX_WRAP_T_MIRRORED_REPEAT			0x00000200
+#define NV20_3D_TEX_WRAP_T_CLAMP_TO_EDGE			0x00000300
+#define NV20_3D_TEX_WRAP_T_CLAMP_TO_BORDER			0x00000400
+#define NV20_3D_TEX_WRAP_T_CLAMP				0x00000500
+#define NV20_3D_TEX_WRAP_R__MASK				0x000f0000
+#define NV20_3D_TEX_WRAP_R__SHIFT				16
+#define NV20_3D_TEX_WRAP_R_REPEAT				0x00010000
+#define NV20_3D_TEX_WRAP_R_MIRRORED_REPEAT			0x00020000
+#define NV20_3D_TEX_WRAP_R_CLAMP_TO_EDGE			0x00030000
+#define NV20_3D_TEX_WRAP_R_CLAMP_TO_BORDER			0x00040000
+#define NV20_3D_TEX_WRAP_R_CLAMP				0x00050000
+
+#define NV20_3D_TEX_ENABLE(i0)				       (0x00001b0c + 0x40*(i0))
+#define NV20_3D_TEX_ENABLE_ANISO__MASK				0x00000030
+#define NV20_3D_TEX_ENABLE_ANISO__SHIFT				4
+#define NV20_3D_TEX_ENABLE_ANISO_NONE				0x00000000
+#define NV20_3D_TEX_ENABLE_ANISO_2X				0x00000010
+#define NV20_3D_TEX_ENABLE_ANISO_4X				0x00000020
+#define NV20_3D_TEX_ENABLE_ANISO_8X				0x00000030
+#define NV20_3D_TEX_ENABLE_MIPMAP_MAX_LOD__MASK			0x0003c000
+#define NV20_3D_TEX_ENABLE_MIPMAP_MAX_LOD__SHIFT		14
+#define NV20_3D_TEX_ENABLE_MIPMAP_MIN_LOD__MASK			0x3c000000
+#define NV20_3D_TEX_ENABLE_MIPMAP_MIN_LOD__SHIFT		26
+#define NV20_3D_TEX_ENABLE_ENABLE				0x40000000
+
+#define NV20_3D_TEX_NPOT_PITCH(i0)			       (0x00001b10 + 0x40*(i0))
+#define NV20_3D_TEX_NPOT_PITCH_PITCH__MASK			0xffff0000
+#define NV20_3D_TEX_NPOT_PITCH_PITCH__SHIFT			16
+
+#define NV20_3D_TEX_FILTER(i0)				       (0x00001b14 + 0x40*(i0))
+#define NV20_3D_TEX_FILTER_LOD_BIAS__MASK			0x00000f00
+#define NV20_3D_TEX_FILTER_LOD_BIAS__SHIFT			8
+#define NV20_3D_TEX_FILTER_MINIFY__MASK				0x000f0000
+#define NV20_3D_TEX_FILTER_MINIFY__SHIFT			16
+#define NV20_3D_TEX_FILTER_MINIFY_NEAREST			0x00010000
+#define NV20_3D_TEX_FILTER_MINIFY_LINEAR			0x00020000
+#define NV20_3D_TEX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST	0x00030000
+#define NV20_3D_TEX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST		0x00040000
+#define NV20_3D_TEX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR		0x00050000
+#define NV20_3D_TEX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR		0x00060000
+#define NV20_3D_TEX_FILTER_MAGNIFY__MASK			0x0f000000
+#define NV20_3D_TEX_FILTER_MAGNIFY__SHIFT			24
+#define NV20_3D_TEX_FILTER_MAGNIFY_NEAREST			0x01000000
+#define NV20_3D_TEX_FILTER_MAGNIFY_LINEAR			0x02000000
+
+#define NV20_3D_TEX_NPOT_SIZE(i0)			       (0x00001b1c + 0x40*(i0))
+#define NV20_3D_TEX_NPOT_SIZE_H__MASK				0x0000ffff
+#define NV20_3D_TEX_NPOT_SIZE_H__SHIFT				0
+#define NV20_3D_TEX_NPOT_SIZE_W__MASK				0xffff0000
+#define NV20_3D_TEX_NPOT_SIZE_W__SHIFT				16
+
+#define NV20_3D_TEX_PALETTE_OFFSET(i0)			       (0x00001b20 + 0x40*(i0))
+
+#define NV20_3D_TEX_BORDER_COLOR(i0)			       (0x00001b24 + 0x40*(i0))
+#define NV20_3D_TEX_BORDER_COLOR_B__MASK			0x000000ff
+#define NV20_3D_TEX_BORDER_COLOR_B__SHIFT			0
+#define NV20_3D_TEX_BORDER_COLOR_G__MASK			0x0000ff00
+#define NV20_3D_TEX_BORDER_COLOR_G__SHIFT			8
+#define NV20_3D_TEX_BORDER_COLOR_R__MASK			0x00ff0000
+#define NV20_3D_TEX_BORDER_COLOR_R__SHIFT			16
+#define NV20_3D_TEX_BORDER_COLOR_A__MASK			0xff000000
+#define NV20_3D_TEX_BORDER_COLOR_A__SHIFT			24
+
+
+
+#define NV20_3D_RC_IN_ALPHA(i0)				       (0x00000260 + 0x4*(i0))
+#define NV20_3D_RC_IN_ALPHA_D_INPUT__MASK			0x0000000f
+#define NV20_3D_RC_IN_ALPHA_D_INPUT__SHIFT			0
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_ZERO			0x00000000
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_FOG				0x00000003
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_PRIMARY_COLOR		0x00000004
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_TEXTURE0			0x00000008
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_TEXTURE1			0x00000009
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_TEXTURE2			0x0000000a
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_TEXTURE3			0x0000000b
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_SPARE0			0x0000000c
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_SPARE1			0x0000000d
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV20_3D_RC_IN_ALPHA_D_INPUT_E_TIMES_F			0x0000000f
+#define NV20_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV20_3D_RC_IN_ALPHA_D_COMPONENT_USAGE__SHIFT		4
+#define NV20_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_BLUE		0x00000000
+#define NV20_3D_RC_IN_ALPHA_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING__MASK			0x000000e0
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING__SHIFT			5
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV20_3D_RC_IN_ALPHA_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV20_3D_RC_IN_ALPHA_C_INPUT__MASK			0x00000f00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT__SHIFT			8
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_ZERO			0x00000000
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_FOG				0x00000300
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_PRIMARY_COLOR		0x00000400
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_TEXTURE0			0x00000800
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_TEXTURE1			0x00000900
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_TEXTURE2			0x00000a00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_TEXTURE3			0x00000b00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_IN_ALPHA_C_INPUT_E_TIMES_F			0x00000f00
+#define NV20_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV20_3D_RC_IN_ALPHA_C_COMPONENT_USAGE__SHIFT		12
+#define NV20_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_BLUE		0x00000000
+#define NV20_3D_RC_IN_ALPHA_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING__MASK			0x0000e000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING__SHIFT			13
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV20_3D_RC_IN_ALPHA_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT__MASK			0x000f0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT__SHIFT			16
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_ZERO			0x00000000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_FOG				0x00030000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_PRIMARY_COLOR		0x00040000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_TEXTURE0			0x00080000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_TEXTURE1			0x00090000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_TEXTURE2			0x000a0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_TEXTURE3			0x000b0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_SPARE0			0x000c0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_SPARE1			0x000d0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV20_3D_RC_IN_ALPHA_B_INPUT_E_TIMES_F			0x000f0000
+#define NV20_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV20_3D_RC_IN_ALPHA_B_COMPONENT_USAGE__SHIFT		20
+#define NV20_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_BLUE		0x00000000
+#define NV20_3D_RC_IN_ALPHA_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING__MASK			0x00e00000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING__SHIFT			21
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV20_3D_RC_IN_ALPHA_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT__MASK			0x0f000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT__SHIFT			24
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_ZERO			0x00000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_FOG				0x03000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_PRIMARY_COLOR		0x04000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_TEXTURE0			0x08000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_TEXTURE1			0x09000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_TEXTURE2			0x0a000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_TEXTURE3			0x0b000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_SPARE0			0x0c000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_SPARE1			0x0d000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV20_3D_RC_IN_ALPHA_A_INPUT_E_TIMES_F			0x0f000000
+#define NV20_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV20_3D_RC_IN_ALPHA_A_COMPONENT_USAGE__SHIFT		28
+#define NV20_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_BLUE		0x00000000
+#define NV20_3D_RC_IN_ALPHA_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING__MASK			0xe0000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING__SHIFT			29
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV20_3D_RC_IN_ALPHA_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV20_3D_RC_IN_RGB(i0)				       (0x00000ac0 + 0x4*(i0))
+#define NV20_3D_RC_IN_RGB_D_INPUT__MASK				0x0000000f
+#define NV20_3D_RC_IN_RGB_D_INPUT__SHIFT			0
+#define NV20_3D_RC_IN_RGB_D_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV20_3D_RC_IN_RGB_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV20_3D_RC_IN_RGB_D_INPUT_FOG				0x00000003
+#define NV20_3D_RC_IN_RGB_D_INPUT_PRIMARY_COLOR			0x00000004
+#define NV20_3D_RC_IN_RGB_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV20_3D_RC_IN_RGB_D_INPUT_TEXTURE0			0x00000008
+#define NV20_3D_RC_IN_RGB_D_INPUT_TEXTURE1			0x00000009
+#define NV20_3D_RC_IN_RGB_D_INPUT_TEXTURE2			0x0000000a
+#define NV20_3D_RC_IN_RGB_D_INPUT_TEXTURE3			0x0000000b
+#define NV20_3D_RC_IN_RGB_D_INPUT_SPARE0			0x0000000c
+#define NV20_3D_RC_IN_RGB_D_INPUT_SPARE1			0x0000000d
+#define NV20_3D_RC_IN_RGB_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV20_3D_RC_IN_RGB_D_INPUT_E_TIMES_F			0x0000000f
+#define NV20_3D_RC_IN_RGB_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV20_3D_RC_IN_RGB_D_COMPONENT_USAGE__SHIFT		4
+#define NV20_3D_RC_IN_RGB_D_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_IN_RGB_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV20_3D_RC_IN_RGB_D_MAPPING__MASK			0x000000e0
+#define NV20_3D_RC_IN_RGB_D_MAPPING__SHIFT			5
+#define NV20_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_RGB_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV20_3D_RC_IN_RGB_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV20_3D_RC_IN_RGB_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV20_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV20_3D_RC_IN_RGB_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV20_3D_RC_IN_RGB_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV20_3D_RC_IN_RGB_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV20_3D_RC_IN_RGB_C_INPUT__MASK				0x00000f00
+#define NV20_3D_RC_IN_RGB_C_INPUT__SHIFT			8
+#define NV20_3D_RC_IN_RGB_C_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_IN_RGB_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_IN_RGB_C_INPUT_FOG				0x00000300
+#define NV20_3D_RC_IN_RGB_C_INPUT_PRIMARY_COLOR			0x00000400
+#define NV20_3D_RC_IN_RGB_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_IN_RGB_C_INPUT_TEXTURE0			0x00000800
+#define NV20_3D_RC_IN_RGB_C_INPUT_TEXTURE1			0x00000900
+#define NV20_3D_RC_IN_RGB_C_INPUT_TEXTURE2			0x00000a00
+#define NV20_3D_RC_IN_RGB_C_INPUT_TEXTURE3			0x00000b00
+#define NV20_3D_RC_IN_RGB_C_INPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_IN_RGB_C_INPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_IN_RGB_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_IN_RGB_C_INPUT_E_TIMES_F			0x00000f00
+#define NV20_3D_RC_IN_RGB_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV20_3D_RC_IN_RGB_C_COMPONENT_USAGE__SHIFT		12
+#define NV20_3D_RC_IN_RGB_C_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_IN_RGB_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV20_3D_RC_IN_RGB_C_MAPPING__MASK			0x0000e000
+#define NV20_3D_RC_IN_RGB_C_MAPPING__SHIFT			13
+#define NV20_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV20_3D_RC_IN_RGB_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV20_3D_RC_IN_RGB_B_INPUT__MASK				0x000f0000
+#define NV20_3D_RC_IN_RGB_B_INPUT__SHIFT			16
+#define NV20_3D_RC_IN_RGB_B_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV20_3D_RC_IN_RGB_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV20_3D_RC_IN_RGB_B_INPUT_FOG				0x00030000
+#define NV20_3D_RC_IN_RGB_B_INPUT_PRIMARY_COLOR			0x00040000
+#define NV20_3D_RC_IN_RGB_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV20_3D_RC_IN_RGB_B_INPUT_TEXTURE0			0x00080000
+#define NV20_3D_RC_IN_RGB_B_INPUT_TEXTURE1			0x00090000
+#define NV20_3D_RC_IN_RGB_B_INPUT_TEXTURE2			0x000a0000
+#define NV20_3D_RC_IN_RGB_B_INPUT_TEXTURE3			0x000b0000
+#define NV20_3D_RC_IN_RGB_B_INPUT_SPARE0			0x000c0000
+#define NV20_3D_RC_IN_RGB_B_INPUT_SPARE1			0x000d0000
+#define NV20_3D_RC_IN_RGB_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV20_3D_RC_IN_RGB_B_INPUT_E_TIMES_F			0x000f0000
+#define NV20_3D_RC_IN_RGB_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV20_3D_RC_IN_RGB_B_COMPONENT_USAGE__SHIFT		20
+#define NV20_3D_RC_IN_RGB_B_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_IN_RGB_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV20_3D_RC_IN_RGB_B_MAPPING__MASK			0x00e00000
+#define NV20_3D_RC_IN_RGB_B_MAPPING__SHIFT			21
+#define NV20_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV20_3D_RC_IN_RGB_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV20_3D_RC_IN_RGB_A_INPUT__MASK				0x0f000000
+#define NV20_3D_RC_IN_RGB_A_INPUT__SHIFT			24
+#define NV20_3D_RC_IN_RGB_A_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_FOG				0x03000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_PRIMARY_COLOR			0x04000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_TEXTURE0			0x08000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_TEXTURE1			0x09000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_TEXTURE2			0x0a000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_TEXTURE3			0x0b000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_SPARE0			0x0c000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_SPARE1			0x0d000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV20_3D_RC_IN_RGB_A_INPUT_E_TIMES_F			0x0f000000
+#define NV20_3D_RC_IN_RGB_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV20_3D_RC_IN_RGB_A_COMPONENT_USAGE__SHIFT		28
+#define NV20_3D_RC_IN_RGB_A_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_IN_RGB_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING__MASK			0xe0000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING__SHIFT			29
+#define NV20_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV20_3D_RC_IN_RGB_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV20_3D_RC_CONSTANT_COLOR0(i0)			       (0x00000a60 + 0x4*(i0))
+#define NV20_3D_RC_CONSTANT_COLOR0_B__MASK			0x000000ff
+#define NV20_3D_RC_CONSTANT_COLOR0_B__SHIFT			0
+#define NV20_3D_RC_CONSTANT_COLOR0_G__MASK			0x0000ff00
+#define NV20_3D_RC_CONSTANT_COLOR0_G__SHIFT			8
+#define NV20_3D_RC_CONSTANT_COLOR0_R__MASK			0x00ff0000
+#define NV20_3D_RC_CONSTANT_COLOR0_R__SHIFT			16
+#define NV20_3D_RC_CONSTANT_COLOR0_A__MASK			0xff000000
+#define NV20_3D_RC_CONSTANT_COLOR0_A__SHIFT			24
+
+#define NV20_3D_RC_CONSTANT_COLOR1(i0)			       (0x00000a80 + 0x4*(i0))
+#define NV20_3D_RC_CONSTANT_COLOR1_B__MASK			0x000000ff
+#define NV20_3D_RC_CONSTANT_COLOR1_B__SHIFT			0
+#define NV20_3D_RC_CONSTANT_COLOR1_G__MASK			0x0000ff00
+#define NV20_3D_RC_CONSTANT_COLOR1_G__SHIFT			8
+#define NV20_3D_RC_CONSTANT_COLOR1_R__MASK			0x00ff0000
+#define NV20_3D_RC_CONSTANT_COLOR1_R__SHIFT			16
+#define NV20_3D_RC_CONSTANT_COLOR1_A__MASK			0xff000000
+#define NV20_3D_RC_CONSTANT_COLOR1_A__SHIFT			24
+
+#define NV20_3D_RC_OUT_ALPHA(i0)			       (0x00000aa0 + 0x4*(i0))
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT__MASK			0x0000000f
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT__SHIFT			0
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR0		0x00000001
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_CONSTANT_COLOR1		0x00000002
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_FOG			0x00000003
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_PRIMARY_COLOR		0x00000004
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_SECONDARY_COLOR		0x00000005
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE0			0x00000008
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE1			0x00000009
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE2			0x0000000a
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_TEXTURE3			0x0000000b
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0			0x0000000c
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE1			0x0000000d
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV20_3D_RC_OUT_ALPHA_CD_OUTPUT_E_TIMES_F		0x0000000f
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT__MASK			0x000000f0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT__SHIFT			4
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR0		0x00000010
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_CONSTANT_COLOR1		0x00000020
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_FOG			0x00000030
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_PRIMARY_COLOR		0x00000040
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_SECONDARY_COLOR		0x00000050
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE0			0x00000080
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE1			0x00000090
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE2			0x000000a0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_TEXTURE3			0x000000b0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0			0x000000c0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE1			0x000000d0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000000e0
+#define NV20_3D_RC_OUT_ALPHA_AB_OUTPUT_E_TIMES_F		0x000000f0
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT__MASK			0x00000f00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT__SHIFT			8
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_FOG			0x00000300
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_PRIMARY_COLOR		0x00000400
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE0		0x00000800
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE1		0x00000900
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE2		0x00000a00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_TEXTURE3		0x00000b00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_OUT_ALPHA_SUM_OUTPUT_E_TIMES_F		0x00000f00
+#define NV20_3D_RC_OUT_ALPHA_CD_DOT_PRODUCT			0x00001000
+#define NV20_3D_RC_OUT_ALPHA_AB_DOT_PRODUCT			0x00002000
+#define NV20_3D_RC_OUT_ALPHA_MUX_SUM				0x00004000
+#define NV20_3D_RC_OUT_ALPHA_BIAS__MASK				0x00008000
+#define NV20_3D_RC_OUT_ALPHA_BIAS__SHIFT			15
+#define NV20_3D_RC_OUT_ALPHA_BIAS_NONE				0x00000000
+#define NV20_3D_RC_OUT_ALPHA_BIAS_BIAS_BY_NEGATIVE_ONE_HALF	0x00008000
+#define NV20_3D_RC_OUT_ALPHA_SCALE__MASK			0x00030000
+#define NV20_3D_RC_OUT_ALPHA_SCALE__SHIFT			16
+#define NV20_3D_RC_OUT_ALPHA_SCALE_NONE				0x00000000
+#define NV20_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_TWO			0x00010000
+#define NV20_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_FOUR		0x00020000
+#define NV20_3D_RC_OUT_ALPHA_SCALE_SCALE_BY_ONE_HALF		0x00030000
+
+#define NV20_3D_RC_OUT_RGB(i0)				       (0x00001e40 + 0x4*(i0))
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT__MASK			0x0000000f
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT__SHIFT			0
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR0		0x00000001
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_CONSTANT_COLOR1		0x00000002
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_FOG			0x00000003
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_PRIMARY_COLOR		0x00000004
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_SECONDARY_COLOR		0x00000005
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE0			0x00000008
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE1			0x00000009
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE2			0x0000000a
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_TEXTURE3			0x0000000b
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0			0x0000000c
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_SPARE1			0x0000000d
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV20_3D_RC_OUT_RGB_CD_OUTPUT_E_TIMES_F			0x0000000f
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT__MASK			0x000000f0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT__SHIFT			4
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR0		0x00000010
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_CONSTANT_COLOR1		0x00000020
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_FOG			0x00000030
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_PRIMARY_COLOR		0x00000040
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_SECONDARY_COLOR		0x00000050
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE0			0x00000080
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE1			0x00000090
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE2			0x000000a0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_TEXTURE3			0x000000b0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0			0x000000c0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_SPARE1			0x000000d0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000000e0
+#define NV20_3D_RC_OUT_RGB_AB_OUTPUT_E_TIMES_F			0x000000f0
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT__MASK			0x00000f00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT__SHIFT			8
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_ZERO			0x00000000
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_FOG			0x00000300
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_PRIMARY_COLOR		0x00000400
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE0			0x00000800
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE1			0x00000900
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE2			0x00000a00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_TEXTURE3			0x00000b00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_OUT_RGB_SUM_OUTPUT_E_TIMES_F			0x00000f00
+#define NV20_3D_RC_OUT_RGB_CD_DOT_PRODUCT			0x00001000
+#define NV20_3D_RC_OUT_RGB_AB_DOT_PRODUCT			0x00002000
+#define NV20_3D_RC_OUT_RGB_MUX_SUM				0x00004000
+#define NV20_3D_RC_OUT_RGB_BIAS__MASK				0x00008000
+#define NV20_3D_RC_OUT_RGB_BIAS__SHIFT				15
+#define NV20_3D_RC_OUT_RGB_BIAS_NONE				0x00000000
+#define NV20_3D_RC_OUT_RGB_BIAS_BIAS_BY_NEGATIVE_ONE_HALF	0x00008000
+#define NV20_3D_RC_OUT_RGB_SCALE__MASK				0x00030000
+#define NV20_3D_RC_OUT_RGB_SCALE__SHIFT				16
+#define NV20_3D_RC_OUT_RGB_SCALE_NONE				0x00000000
+#define NV20_3D_RC_OUT_RGB_SCALE_SCALE_BY_TWO			0x00010000
+#define NV20_3D_RC_OUT_RGB_SCALE_SCALE_BY_FOUR			0x00020000
+#define NV20_3D_RC_OUT_RGB_SCALE_SCALE_BY_ONE_HALF		0x00030000
+
+#define NV20_3D_RC_FINAL0					0x00000288
+#define NV20_3D_RC_FINAL0_D_INPUT__MASK				0x0000000f
+#define NV20_3D_RC_FINAL0_D_INPUT__SHIFT			0
+#define NV20_3D_RC_FINAL0_D_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR0		0x00000001
+#define NV20_3D_RC_FINAL0_D_INPUT_CONSTANT_COLOR1		0x00000002
+#define NV20_3D_RC_FINAL0_D_INPUT_FOG				0x00000003
+#define NV20_3D_RC_FINAL0_D_INPUT_PRIMARY_COLOR			0x00000004
+#define NV20_3D_RC_FINAL0_D_INPUT_SECONDARY_COLOR		0x00000005
+#define NV20_3D_RC_FINAL0_D_INPUT_TEXTURE0			0x00000008
+#define NV20_3D_RC_FINAL0_D_INPUT_TEXTURE1			0x00000009
+#define NV20_3D_RC_FINAL0_D_INPUT_TEXTURE2			0x0000000a
+#define NV20_3D_RC_FINAL0_D_INPUT_TEXTURE3			0x0000000b
+#define NV20_3D_RC_FINAL0_D_INPUT_SPARE0			0x0000000c
+#define NV20_3D_RC_FINAL0_D_INPUT_SPARE1			0x0000000d
+#define NV20_3D_RC_FINAL0_D_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0000000e
+#define NV20_3D_RC_FINAL0_D_INPUT_E_TIMES_F			0x0000000f
+#define NV20_3D_RC_FINAL0_D_COMPONENT_USAGE__MASK		0x00000010
+#define NV20_3D_RC_FINAL0_D_COMPONENT_USAGE__SHIFT		4
+#define NV20_3D_RC_FINAL0_D_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL0_D_COMPONENT_USAGE_ALPHA		0x00000010
+#define NV20_3D_RC_FINAL0_D_MAPPING__MASK			0x000000e0
+#define NV20_3D_RC_FINAL0_D_MAPPING__SHIFT			5
+#define NV20_3D_RC_FINAL0_D_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL0_D_MAPPING_UNSIGNED_INVERT		0x00000020
+#define NV20_3D_RC_FINAL0_D_MAPPING_EXPAND_NORMAL		0x00000040
+#define NV20_3D_RC_FINAL0_D_MAPPING_EXPAND_NEGATE		0x00000060
+#define NV20_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NORMAL		0x00000080
+#define NV20_3D_RC_FINAL0_D_MAPPING_HALF_BIAS_NEGATE		0x000000a0
+#define NV20_3D_RC_FINAL0_D_MAPPING_SIGNED_IDENTITY		0x000000c0
+#define NV20_3D_RC_FINAL0_D_MAPPING_SIGNED_NEGATE		0x000000e0
+#define NV20_3D_RC_FINAL0_C_INPUT__MASK				0x00000f00
+#define NV20_3D_RC_FINAL0_C_INPUT__SHIFT			8
+#define NV20_3D_RC_FINAL0_C_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_FINAL0_C_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_FINAL0_C_INPUT_FOG				0x00000300
+#define NV20_3D_RC_FINAL0_C_INPUT_PRIMARY_COLOR			0x00000400
+#define NV20_3D_RC_FINAL0_C_INPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_FINAL0_C_INPUT_TEXTURE0			0x00000800
+#define NV20_3D_RC_FINAL0_C_INPUT_TEXTURE1			0x00000900
+#define NV20_3D_RC_FINAL0_C_INPUT_TEXTURE2			0x00000a00
+#define NV20_3D_RC_FINAL0_C_INPUT_TEXTURE3			0x00000b00
+#define NV20_3D_RC_FINAL0_C_INPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_FINAL0_C_INPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_FINAL0_C_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_FINAL0_C_INPUT_E_TIMES_F			0x00000f00
+#define NV20_3D_RC_FINAL0_C_COMPONENT_USAGE__MASK		0x00001000
+#define NV20_3D_RC_FINAL0_C_COMPONENT_USAGE__SHIFT		12
+#define NV20_3D_RC_FINAL0_C_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL0_C_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV20_3D_RC_FINAL0_C_MAPPING__MASK			0x0000e000
+#define NV20_3D_RC_FINAL0_C_MAPPING__SHIFT			13
+#define NV20_3D_RC_FINAL0_C_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL0_C_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV20_3D_RC_FINAL0_C_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV20_3D_RC_FINAL0_C_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV20_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV20_3D_RC_FINAL0_C_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV20_3D_RC_FINAL0_C_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV20_3D_RC_FINAL0_C_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV20_3D_RC_FINAL0_B_INPUT__MASK				0x000f0000
+#define NV20_3D_RC_FINAL0_B_INPUT__SHIFT			16
+#define NV20_3D_RC_FINAL0_B_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV20_3D_RC_FINAL0_B_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV20_3D_RC_FINAL0_B_INPUT_FOG				0x00030000
+#define NV20_3D_RC_FINAL0_B_INPUT_PRIMARY_COLOR			0x00040000
+#define NV20_3D_RC_FINAL0_B_INPUT_SECONDARY_COLOR		0x00050000
+#define NV20_3D_RC_FINAL0_B_INPUT_TEXTURE0			0x00080000
+#define NV20_3D_RC_FINAL0_B_INPUT_TEXTURE1			0x00090000
+#define NV20_3D_RC_FINAL0_B_INPUT_TEXTURE2			0x000a0000
+#define NV20_3D_RC_FINAL0_B_INPUT_TEXTURE3			0x000b0000
+#define NV20_3D_RC_FINAL0_B_INPUT_SPARE0			0x000c0000
+#define NV20_3D_RC_FINAL0_B_INPUT_SPARE1			0x000d0000
+#define NV20_3D_RC_FINAL0_B_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV20_3D_RC_FINAL0_B_INPUT_E_TIMES_F			0x000f0000
+#define NV20_3D_RC_FINAL0_B_COMPONENT_USAGE__MASK		0x00100000
+#define NV20_3D_RC_FINAL0_B_COMPONENT_USAGE__SHIFT		20
+#define NV20_3D_RC_FINAL0_B_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL0_B_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV20_3D_RC_FINAL0_B_MAPPING__MASK			0x00e00000
+#define NV20_3D_RC_FINAL0_B_MAPPING__SHIFT			21
+#define NV20_3D_RC_FINAL0_B_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL0_B_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV20_3D_RC_FINAL0_B_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV20_3D_RC_FINAL0_B_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV20_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV20_3D_RC_FINAL0_B_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV20_3D_RC_FINAL0_B_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV20_3D_RC_FINAL0_B_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV20_3D_RC_FINAL0_A_INPUT__MASK				0x0f000000
+#define NV20_3D_RC_FINAL0_A_INPUT__SHIFT			24
+#define NV20_3D_RC_FINAL0_A_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV20_3D_RC_FINAL0_A_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV20_3D_RC_FINAL0_A_INPUT_FOG				0x03000000
+#define NV20_3D_RC_FINAL0_A_INPUT_PRIMARY_COLOR			0x04000000
+#define NV20_3D_RC_FINAL0_A_INPUT_SECONDARY_COLOR		0x05000000
+#define NV20_3D_RC_FINAL0_A_INPUT_TEXTURE0			0x08000000
+#define NV20_3D_RC_FINAL0_A_INPUT_TEXTURE1			0x09000000
+#define NV20_3D_RC_FINAL0_A_INPUT_TEXTURE2			0x0a000000
+#define NV20_3D_RC_FINAL0_A_INPUT_TEXTURE3			0x0b000000
+#define NV20_3D_RC_FINAL0_A_INPUT_SPARE0			0x0c000000
+#define NV20_3D_RC_FINAL0_A_INPUT_SPARE1			0x0d000000
+#define NV20_3D_RC_FINAL0_A_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV20_3D_RC_FINAL0_A_INPUT_E_TIMES_F			0x0f000000
+#define NV20_3D_RC_FINAL0_A_COMPONENT_USAGE__MASK		0x10000000
+#define NV20_3D_RC_FINAL0_A_COMPONENT_USAGE__SHIFT		28
+#define NV20_3D_RC_FINAL0_A_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL0_A_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV20_3D_RC_FINAL0_A_MAPPING__MASK			0xe0000000
+#define NV20_3D_RC_FINAL0_A_MAPPING__SHIFT			29
+#define NV20_3D_RC_FINAL0_A_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV20_3D_RC_FINAL0_A_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV20_3D_RC_FINAL1					0x0000028c
+#define NV20_3D_RC_FINAL1_COLOR_SUM_CLAMP			0x00000080
+#define NV20_3D_RC_FINAL1_G_INPUT__MASK				0x00000f00
+#define NV20_3D_RC_FINAL1_G_INPUT__SHIFT			8
+#define NV20_3D_RC_FINAL1_G_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR0		0x00000100
+#define NV20_3D_RC_FINAL1_G_INPUT_CONSTANT_COLOR1		0x00000200
+#define NV20_3D_RC_FINAL1_G_INPUT_FOG				0x00000300
+#define NV20_3D_RC_FINAL1_G_INPUT_PRIMARY_COLOR			0x00000400
+#define NV20_3D_RC_FINAL1_G_INPUT_SECONDARY_COLOR		0x00000500
+#define NV20_3D_RC_FINAL1_G_INPUT_TEXTURE0			0x00000800
+#define NV20_3D_RC_FINAL1_G_INPUT_TEXTURE1			0x00000900
+#define NV20_3D_RC_FINAL1_G_INPUT_TEXTURE2			0x00000a00
+#define NV20_3D_RC_FINAL1_G_INPUT_TEXTURE3			0x00000b00
+#define NV20_3D_RC_FINAL1_G_INPUT_SPARE0			0x00000c00
+#define NV20_3D_RC_FINAL1_G_INPUT_SPARE1			0x00000d00
+#define NV20_3D_RC_FINAL1_G_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x00000e00
+#define NV20_3D_RC_FINAL1_G_INPUT_E_TIMES_F			0x00000f00
+#define NV20_3D_RC_FINAL1_G_COMPONENT_USAGE__MASK		0x00001000
+#define NV20_3D_RC_FINAL1_G_COMPONENT_USAGE__SHIFT		12
+#define NV20_3D_RC_FINAL1_G_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL1_G_COMPONENT_USAGE_ALPHA		0x00001000
+#define NV20_3D_RC_FINAL1_G_MAPPING__MASK			0x0000e000
+#define NV20_3D_RC_FINAL1_G_MAPPING__SHIFT			13
+#define NV20_3D_RC_FINAL1_G_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL1_G_MAPPING_UNSIGNED_INVERT		0x00002000
+#define NV20_3D_RC_FINAL1_G_MAPPING_EXPAND_NORMAL		0x00004000
+#define NV20_3D_RC_FINAL1_G_MAPPING_EXPAND_NEGATE		0x00006000
+#define NV20_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NORMAL		0x00008000
+#define NV20_3D_RC_FINAL1_G_MAPPING_HALF_BIAS_NEGATE		0x0000a000
+#define NV20_3D_RC_FINAL1_G_MAPPING_SIGNED_IDENTITY		0x0000c000
+#define NV20_3D_RC_FINAL1_G_MAPPING_SIGNED_NEGATE		0x0000e000
+#define NV20_3D_RC_FINAL1_F_INPUT__MASK				0x000f0000
+#define NV20_3D_RC_FINAL1_F_INPUT__SHIFT			16
+#define NV20_3D_RC_FINAL1_F_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR0		0x00010000
+#define NV20_3D_RC_FINAL1_F_INPUT_CONSTANT_COLOR1		0x00020000
+#define NV20_3D_RC_FINAL1_F_INPUT_FOG				0x00030000
+#define NV20_3D_RC_FINAL1_F_INPUT_PRIMARY_COLOR			0x00040000
+#define NV20_3D_RC_FINAL1_F_INPUT_SECONDARY_COLOR		0x00050000
+#define NV20_3D_RC_FINAL1_F_INPUT_TEXTURE0			0x00080000
+#define NV20_3D_RC_FINAL1_F_INPUT_TEXTURE1			0x00090000
+#define NV20_3D_RC_FINAL1_F_INPUT_TEXTURE2			0x000a0000
+#define NV20_3D_RC_FINAL1_F_INPUT_TEXTURE3			0x000b0000
+#define NV20_3D_RC_FINAL1_F_INPUT_SPARE0			0x000c0000
+#define NV20_3D_RC_FINAL1_F_INPUT_SPARE1			0x000d0000
+#define NV20_3D_RC_FINAL1_F_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x000e0000
+#define NV20_3D_RC_FINAL1_F_INPUT_E_TIMES_F			0x000f0000
+#define NV20_3D_RC_FINAL1_F_COMPONENT_USAGE__MASK		0x00100000
+#define NV20_3D_RC_FINAL1_F_COMPONENT_USAGE__SHIFT		20
+#define NV20_3D_RC_FINAL1_F_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL1_F_COMPONENT_USAGE_ALPHA		0x00100000
+#define NV20_3D_RC_FINAL1_F_MAPPING__MASK			0x00e00000
+#define NV20_3D_RC_FINAL1_F_MAPPING__SHIFT			21
+#define NV20_3D_RC_FINAL1_F_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL1_F_MAPPING_UNSIGNED_INVERT		0x00200000
+#define NV20_3D_RC_FINAL1_F_MAPPING_EXPAND_NORMAL		0x00400000
+#define NV20_3D_RC_FINAL1_F_MAPPING_EXPAND_NEGATE		0x00600000
+#define NV20_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NORMAL		0x00800000
+#define NV20_3D_RC_FINAL1_F_MAPPING_HALF_BIAS_NEGATE		0x00a00000
+#define NV20_3D_RC_FINAL1_F_MAPPING_SIGNED_IDENTITY		0x00c00000
+#define NV20_3D_RC_FINAL1_F_MAPPING_SIGNED_NEGATE		0x00e00000
+#define NV20_3D_RC_FINAL1_E_INPUT__MASK				0x0f000000
+#define NV20_3D_RC_FINAL1_E_INPUT__SHIFT			24
+#define NV20_3D_RC_FINAL1_E_INPUT_ZERO				0x00000000
+#define NV20_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR0		0x01000000
+#define NV20_3D_RC_FINAL1_E_INPUT_CONSTANT_COLOR1		0x02000000
+#define NV20_3D_RC_FINAL1_E_INPUT_FOG				0x03000000
+#define NV20_3D_RC_FINAL1_E_INPUT_PRIMARY_COLOR			0x04000000
+#define NV20_3D_RC_FINAL1_E_INPUT_SECONDARY_COLOR		0x05000000
+#define NV20_3D_RC_FINAL1_E_INPUT_TEXTURE0			0x08000000
+#define NV20_3D_RC_FINAL1_E_INPUT_TEXTURE1			0x09000000
+#define NV20_3D_RC_FINAL1_E_INPUT_TEXTURE2			0x0a000000
+#define NV20_3D_RC_FINAL1_E_INPUT_TEXTURE3			0x0b000000
+#define NV20_3D_RC_FINAL1_E_INPUT_SPARE0			0x0c000000
+#define NV20_3D_RC_FINAL1_E_INPUT_SPARE1			0x0d000000
+#define NV20_3D_RC_FINAL1_E_INPUT_SPARE0_PLUS_SECONDARY_COLOR	0x0e000000
+#define NV20_3D_RC_FINAL1_E_INPUT_E_TIMES_F			0x0f000000
+#define NV20_3D_RC_FINAL1_E_COMPONENT_USAGE__MASK		0x10000000
+#define NV20_3D_RC_FINAL1_E_COMPONENT_USAGE__SHIFT		28
+#define NV20_3D_RC_FINAL1_E_COMPONENT_USAGE_RGB			0x00000000
+#define NV20_3D_RC_FINAL1_E_COMPONENT_USAGE_ALPHA		0x10000000
+#define NV20_3D_RC_FINAL1_E_MAPPING__MASK			0xe0000000
+#define NV20_3D_RC_FINAL1_E_MAPPING__SHIFT			29
+#define NV20_3D_RC_FINAL1_E_MAPPING_UNSIGNED_IDENTITY		0x00000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_UNSIGNED_INVERT		0x20000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_EXPAND_NORMAL		0x40000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_EXPAND_NEGATE		0x60000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NORMAL		0x80000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_HALF_BIAS_NEGATE		0xa0000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_SIGNED_IDENTITY		0xc0000000
+#define NV20_3D_RC_FINAL1_E_MAPPING_SIGNED_NEGATE		0xe0000000
+
+#define NV20_3D_RC_COLOR0					0x00001e20
+#define NV20_3D_RC_COLOR0_B__MASK				0x000000ff
+#define NV20_3D_RC_COLOR0_B__SHIFT				0
+#define NV20_3D_RC_COLOR0_G__MASK				0x0000ff00
+#define NV20_3D_RC_COLOR0_G__SHIFT				8
+#define NV20_3D_RC_COLOR0_R__MASK				0x00ff0000
+#define NV20_3D_RC_COLOR0_R__SHIFT				16
+#define NV20_3D_RC_COLOR0_A__MASK				0xff000000
+#define NV20_3D_RC_COLOR0_A__SHIFT				24
+
+#define NV20_3D_RC_COLOR1					0x00001e24
+#define NV20_3D_RC_COLOR1_B__MASK				0x000000ff
+#define NV20_3D_RC_COLOR1_B__SHIFT				0
+#define NV20_3D_RC_COLOR1_G__MASK				0x0000ff00
+#define NV20_3D_RC_COLOR1_G__SHIFT				8
+#define NV20_3D_RC_COLOR1_R__MASK				0x00ff0000
+#define NV20_3D_RC_COLOR1_R__SHIFT				16
+#define NV20_3D_RC_COLOR1_A__MASK				0xff000000
+#define NV20_3D_RC_COLOR1_A__SHIFT				24
+
+#define NV20_3D_RC_ENABLE					0x00001e60
+#define NV20_3D_RC_ENABLE_NUM_COMBINERS__MASK			0x0000000f
+#define NV20_3D_RC_ENABLE_NUM_COMBINERS__SHIFT			0
+
+
+#define NV20_3D_POINT_SIZE					0x0000043c
+
+#define NV20_3D_POINT_PARAMETER(i0)			       (0x00000a30 + 0x4*(i0))
+#define NV20_3D_POINT_PARAMETER__ESIZE				0x00000004
+#define NV20_3D_POINT_PARAMETER__LEN				0x00000008
+
+#define NV20_3D_POLYGON_STIPPLE_ENABLE				0x0000147c
+
+#define NV20_3D_POLYGON_STIPPLE_PATTERN(i0)		       (0x00001480 + 0x4*(i0))
+#define NV20_3D_POLYGON_STIPPLE_PATTERN__ESIZE			0x00000004
+#define NV20_3D_POLYGON_STIPPLE_PATTERN__LEN			0x00000020
+
+#define NV20_3D_COLOR_LOGIC_OP_ENABLE				0x000017bc
+
+#define NV20_3D_COLOR_LOGIC_OP_OP				0x000017c0
+#define NV20_3D_COLOR_LOGIC_OP_OP_CLEAR				0x00001500
+#define NV20_3D_COLOR_LOGIC_OP_OP_AND				0x00001501
+#define NV20_3D_COLOR_LOGIC_OP_OP_AND_REVERSE			0x00001502
+#define NV20_3D_COLOR_LOGIC_OP_OP_COPY				0x00001503
+#define NV20_3D_COLOR_LOGIC_OP_OP_AND_INVERTED			0x00001504
+#define NV20_3D_COLOR_LOGIC_OP_OP_NOOP				0x00001505
+#define NV20_3D_COLOR_LOGIC_OP_OP_XOR				0x00001506
+#define NV20_3D_COLOR_LOGIC_OP_OP_OR				0x00001507
+#define NV20_3D_COLOR_LOGIC_OP_OP_NOR				0x00001508
+#define NV20_3D_COLOR_LOGIC_OP_OP_EQUIV				0x00001509
+#define NV20_3D_COLOR_LOGIC_OP_OP_INVERT			0x0000150a
+#define NV20_3D_COLOR_LOGIC_OP_OP_OR_REVERSE			0x0000150b
+#define NV20_3D_COLOR_LOGIC_OP_OP_COPY_INVERTED			0x0000150c
+#define NV20_3D_COLOR_LOGIC_OP_OP_OR_INVERTED			0x0000150d
+#define NV20_3D_COLOR_LOGIC_OP_OP_NAND				0x0000150e
+#define NV20_3D_COLOR_LOGIC_OP_OP_SET				0x0000150f
+
+#define NV20_3D_DEPTH_CLAMP					0x00001d78
+
+#define NV20_3D_MULTISAMPLE_CONTROL				0x00001d7c
+
+
+#define NV20_3D_CLEAR_DEPTH_VALUE				0x00001d8c
+
+#define NV20_3D_CLEAR_VALUE					0x00001d90
+
+#define NV20_3D_CLEAR_BUFFERS					0x00001d94
+#define NV20_3D_CLEAR_BUFFERS_COLOR_A				0x00000080
+#define NV20_3D_CLEAR_BUFFERS_COLOR_B				0x00000040
+#define NV20_3D_CLEAR_BUFFERS_COLOR_G				0x00000020
+#define NV20_3D_CLEAR_BUFFERS_COLOR_R				0x00000010
+#define NV20_3D_CLEAR_BUFFERS_STENCIL				0x00000002
+#define NV20_3D_CLEAR_BUFFERS_DEPTH				0x00000001
+
+
+#define NV25_3D_DMA_HIERZ					0x000001b0
+
+#define NV25_3D_HIERZ_PITCH					0x0000022c
+
+#define NV25_3D_HIERZ_OFFSET					0x00000230
+
+#define NV20_3D_UNK09F8						0x000009f8
+
+#define NV20_3D_UNK09FC						0x000009fc
+
+#define NV20_3D_UNK17CC						0x000017cc
+
+#define NV20_3D_UNK17E0						0x000017e0
+
+#define NV20_3D_UNK17E4						0x000017e4
+
+#define NV20_3D_UNK17E8						0x000017e8
+
+#define NV20_3D_UNK17EC						0x000017ec
+
+#define NV20_3D_UNK17F0						0x000017f0
+
+#define NV20_3D_UNK17F4						0x000017f4
+
+#define NV20_3D_UNK1D80						0x00001d80
+
+#define NV20_3D_UNK1D84						0x00001d84
+
+#define NV20_3D_UNK1E68						0x00001e68
+
+#define NV20_3D_UNK1E98						0x00001e98
+
+
+#define NV25_3D_UNK01AC						0x000001ac
+
+#define NV25_3D_UNK0A1C						0x00000a1c
+
+#define NV25_3D_UNK1D88						0x00001d88
+
+#define NV25_3D_UNK1DA4						0x00001da4
+
+
+#endif /* NV20_3D_XML */
diff --git a/src/mesa/drivers/dri/nouveau/nv20_context.c b/src/mesa/drivers/dri/nouveau/nv20_context.c
index 89200fb70d..e0483b261e 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_context.c
@@ -28,7 +28,8 @@
 #include "nouveau_context.h"
 #include "nouveau_fbo.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv_object.xml.h"
+#include "nv20_3d.xml.h"
 #include "nv04_driver.h"
 #include "nv10_driver.h"
 #include "nv20_driver.h"
@@ -56,15 +57,15 @@ nv20_clear(struct gl_context *ctx, GLbitfield buffers)
 			fb->_ColorDrawBuffers[0])->surface;
 
 		if (ctx->Color.ColorMask[0][RCOMP])
-			clear |= NV20TCL_CLEAR_BUFFERS_COLOR_R;
+			clear |= NV20_3D_CLEAR_BUFFERS_COLOR_R;
 		if (ctx->Color.ColorMask[0][GCOMP])
-			clear |= NV20TCL_CLEAR_BUFFERS_COLOR_G;
+			clear |= NV20_3D_CLEAR_BUFFERS_COLOR_G;
 		if (ctx->Color.ColorMask[0][BCOMP])
-			clear |= NV20TCL_CLEAR_BUFFERS_COLOR_B;
+			clear |= NV20_3D_CLEAR_BUFFERS_COLOR_B;
 		if (ctx->Color.ColorMask[0][ACOMP])
-			clear |= NV20TCL_CLEAR_BUFFERS_COLOR_A;
+			clear |= NV20_3D_CLEAR_BUFFERS_COLOR_A;
 
-		BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_VALUE, 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_CLEAR_VALUE, 1);
 		OUT_RING(chan, pack_rgba_f(s->format, ctx->Color.ClearColor));
 
 		buffers &= ~BUFFER_BITS_COLOR;
@@ -75,18 +76,18 @@ nv20_clear(struct gl_context *ctx, GLbitfield buffers)
 			fb->_DepthBuffer->Wrapped)->surface;
 
 		if (buffers & BUFFER_BIT_DEPTH && ctx->Depth.Mask)
-			clear |= NV20TCL_CLEAR_BUFFERS_DEPTH;
+			clear |= NV20_3D_CLEAR_BUFFERS_DEPTH;
 		if (buffers & BUFFER_BIT_STENCIL && ctx->Stencil.WriteMask[0])
-			clear |= NV20TCL_CLEAR_BUFFERS_STENCIL;
+			clear |= NV20_3D_CLEAR_BUFFERS_STENCIL;
 
-		BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_DEPTH_VALUE, 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_CLEAR_DEPTH_VALUE, 1);
 		OUT_RING(chan, pack_zs_f(s->format, ctx->Depth.Clear,
 					 ctx->Stencil.Clear));
 
 		buffers &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_BUFFERS, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_CLEAR_BUFFERS, 1);
 	OUT_RING(chan, clear);
 
 	nouveau_clear(ctx, buffers);
@@ -100,38 +101,38 @@ nv20_hwctx_init(struct gl_context *ctx)
 	struct nouveau_hw_state *hw = &to_nouveau_context(ctx)->hw;
 	int i;
 
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_NOTIFY, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_NOTIFY, 1);
 	OUT_RING  (chan, hw->ntfy->handle);
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_TEXTURE0, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_TEXTURE0, 2);
 	OUT_RING  (chan, chan->vram->handle);
 	OUT_RING  (chan, chan->gart->handle);
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_COLOR, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_COLOR, 2);
 	OUT_RING  (chan, chan->vram->handle);
 	OUT_RING  (chan, chan->vram->handle);
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_VTXBUF0, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_VTXBUF0, 2);
 	OUT_RING(chan, chan->vram->handle);
 	OUT_RING(chan, chan->gart->handle);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_QUERY, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_QUERY, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RT_HORIZ, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_HORIZ(0), 1);
 	OUT_RING  (chan, 0xfff << 16 | 0x0);
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_VERT(0), 1);
 	OUT_RING  (chan, 0xfff << 16 | 0x0);
 
-	for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) {
-		BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1);
+	for (i = 1; i < NV20_3D_VIEWPORT_CLIP_HORIZ__LEN; i++) {
+		BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 		OUT_RING  (chan, 0);
-		BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_VERT(i), 1);
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_MODE, 1);
 	OUT_RING  (chan, 0);
 
 	BEGIN_RING(chan, kelvin, 0x17e0, 3);
@@ -140,13 +141,13 @@ nv20_hwctx_init(struct gl_context *ctx)
 	OUT_RINGf (chan, 1.0);
 
 	if (context_chipset(ctx) >= 0x25) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
-		OUT_RING  (chan, NV20TCL_TX_RCOMP_LEQUAL | 0xdb0);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_RCOMP, 1);
+		OUT_RING  (chan, NV20_3D_TEX_RCOMP_LEQUAL | 0xdb0);
 	} else {
 		BEGIN_RING(chan, kelvin, 0x1e68, 1);
 		OUT_RING  (chan, 0x4b800000); /* 16777216.000000 */
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_RCOMP, 1);
-		OUT_RING  (chan, NV20TCL_TX_RCOMP_LEQUAL);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_RCOMP, 1);
+		OUT_RING  (chan, NV20_3D_TEX_RCOMP_LEQUAL);
 	}
 
 	BEGIN_RING(chan, kelvin, 0x290, 1);
@@ -166,19 +167,19 @@ nv20_hwctx_init(struct gl_context *ctx)
 		BEGIN_RING(chan, kelvin, 0x1d88, 1);
 		OUT_RING  (chan, 3);
 
-		BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY9, 1);
+		BEGIN_RING(chan, kelvin, NV25_3D_DMA_HIERZ, 1);
 		OUT_RING  (chan, chan->vram->handle);
-		BEGIN_RING(chan, kelvin, NV25TCL_DMA_IN_MEMORY8, 1);
+		BEGIN_RING(chan, kelvin, NV25_3D_UNK01AC, 1);
 		OUT_RING  (chan, chan->vram->handle);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_DMA_FENCE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DMA_FENCE, 1);
 	OUT_RING  (chan, 0);
 
 	BEGIN_RING(chan, kelvin, 0x1e98, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_NOTIFY, 1);
+	BEGIN_RING(chan, kelvin, NV01_GRAPH_NOTIFY, 1);
 	OUT_RING  (chan, 0);
 
 	BEGIN_RING(chan, kelvin, 0x120, 3);
@@ -191,189 +192,189 @@ nv20_hwctx_init(struct gl_context *ctx)
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RT_HORIZ, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RT_HORIZ, 2);
 	OUT_RING  (chan, 0 << 16 | 0);
 	OUT_RING  (chan, 0 << 16 | 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_ALPHA_FUNC_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2);
-	OUT_RING  (chan, NV20TCL_ALPHA_FUNC_FUNC_ALWAYS);
+	BEGIN_RING(chan, kelvin, NV20_3D_ALPHA_FUNC_FUNC, 2);
+	OUT_RING  (chan, NV20_3D_ALPHA_FUNC_FUNC_ALWAYS);
 	OUT_RING  (chan, 0);
 
-	for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; i++) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
+	for (i = 0; i < NV20_3D_TEX__LEN; i++) {
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_ENABLE(i), 1);
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_OP, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_SHADER_OP, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_SHADER_CULL_MODE, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_ALPHA(0), 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_IN_ALPHA(0), 4);
 	OUT_RING  (chan, 0x30d410d0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_RGB(0), 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_OUT_RGB(0), 4);
 	OUT_RING  (chan, 0x00000c00);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_ENABLE, 1);
 	OUT_RING  (chan, 0x00011101);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_FINAL0, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_FINAL0, 2);
 	OUT_RING  (chan, 0x130e0300);
 	OUT_RING  (chan, 0x0c091c80);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_ALPHA(0), 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_OUT_ALPHA(0), 4);
 	OUT_RING  (chan, 0x00000c00);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_RGB(0), 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_IN_RGB(0), 4);
 	OUT_RING  (chan, 0x20c400c0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_COLOR0, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_COLOR0, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_CONSTANT_COLOR0(0), 4);
 	OUT_RING  (chan, 0x035125a0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0x40002000);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_MULTISAMPLE_CONTROL, 1);
 	OUT_RING  (chan, 0xffff0000);
-	BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_BLEND_FUNC_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_DITHER_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DITHER_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_STENCIL_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_BLEND_FUNC_SRC, 4);
-	OUT_RING  (chan, NV20TCL_BLEND_FUNC_SRC_ONE);
-	OUT_RING  (chan, NV20TCL_BLEND_FUNC_DST_ZERO);
+	BEGIN_RING(chan, kelvin, NV20_3D_BLEND_FUNC_SRC, 4);
+	OUT_RING  (chan, NV20_3D_BLEND_FUNC_SRC_ONE);
+	OUT_RING  (chan, NV20_3D_BLEND_FUNC_DST_ZERO);
 	OUT_RING  (chan, 0);
-	OUT_RING  (chan, NV20TCL_BLEND_EQUATION_FUNC_ADD);
-	BEGIN_RING(chan, kelvin, NV20TCL_STENCIL_MASK, 7);
+	OUT_RING  (chan, NV20_3D_BLEND_EQUATION_FUNC_ADD);
+	BEGIN_RING(chan, kelvin, NV20_3D_STENCIL_MASK, 7);
 	OUT_RING  (chan, 0xff);
-	OUT_RING  (chan, NV20TCL_STENCIL_FUNC_FUNC_ALWAYS);
+	OUT_RING  (chan, NV20_3D_STENCIL_FUNC_FUNC_ALWAYS);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0xff);
-	OUT_RING  (chan, NV20TCL_STENCIL_OP_FAIL_KEEP);
-	OUT_RING  (chan, NV20TCL_STENCIL_OP_ZFAIL_KEEP);
-	OUT_RING  (chan, NV20TCL_STENCIL_OP_ZPASS_KEEP);
+	OUT_RING  (chan, NV20_3D_STENCIL_OP_FAIL_KEEP);
+	OUT_RING  (chan, NV20_3D_STENCIL_OP_ZFAIL_KEEP);
+	OUT_RING  (chan, NV20_3D_STENCIL_OP_ZPASS_KEEP);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_COLOR_LOGIC_OP_ENABLE, 2);
 	OUT_RING  (chan, 0);
-	OUT_RING  (chan, NV20TCL_COLOR_LOGIC_OP_OP_COPY);
+	OUT_RING  (chan, NV20_3D_COLOR_LOGIC_OP_OP_COPY);
 	BEGIN_RING(chan, kelvin, 0x17cc, 1);
 	OUT_RING  (chan, 0);
 	if (context_chipset(ctx) >= 0x25) {
 		BEGIN_RING(chan, kelvin, 0x1d84, 1);
 		OUT_RING  (chan, 1);
 	}
-	BEGIN_RING(chan, kelvin, NV20TCL_LIGHTING_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LIGHTING_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL, 1);
-	OUT_RING  (chan, NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL);
-	BEGIN_RING(chan, kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_MODEL, 1);
+	OUT_RING  (chan, NV20_3D_LIGHT_MODEL_VIEWER_NONLOCAL);
+	BEGIN_RING(chan, kelvin, NV20_3D_SEPARATE_SPECULAR_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_ENABLED_LIGHTS, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_ENABLED_LIGHTS, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_NORMALIZE_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_NORMALIZE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0),
-		   NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE);
-	for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; i++) {
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_STIPPLE_PATTERN(0),
+		   NV20_3D_POLYGON_STIPPLE_PATTERN__LEN);
+	for (i = 0; i < NV20_3D_POLYGON_STIPPLE_PATTERN__LEN; i++) {
 		OUT_RING(chan, 0xffffffff);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3);
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_OFFSET_POINT_ENABLE, 3);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_FUNC, 1);
-	OUT_RING  (chan, NV20TCL_DEPTH_FUNC_LESS);
-	BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DEPTH_FUNC, 1);
+	OUT_RING  (chan, NV20_3D_DEPTH_FUNC_LESS);
+	BEGIN_RING(chan, kelvin, NV20_3D_DEPTH_WRITE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DEPTH_TEST_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_OFFSET_FACTOR, 2);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 0.0);
-	BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_UNK17D8, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_DEPTH_CLAMP, 1);
 	OUT_RING  (chan, 1);
 	if (context_chipset(ctx) < 0x25) {
 		BEGIN_RING(chan, kelvin, 0x1d84, 1);
 		OUT_RING  (chan, 3);
 	}
-	BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_POINT_SIZE, 1);
 	if (context_chipset(ctx) >= 0x25)
 		OUT_RINGf (chan, 1.0);
 	else
 		OUT_RING  (chan, 8);
 
 	if (context_chipset(ctx) >= 0x25) {
-		BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_POINT_PARAMETERS_ENABLE, 1);
 		OUT_RING  (chan, 0);
 		BEGIN_RING(chan, kelvin, 0x0a1c, 1);
 		OUT_RING  (chan, 0x800);
 	} else {
-		BEGIN_RING(chan, kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2);
+		BEGIN_RING(chan, kelvin, NV20_3D_POINT_PARAMETERS_ENABLE, 2);
 		OUT_RING  (chan, 0);
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_LINE_WIDTH, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LINE_WIDTH, 1);
 	OUT_RING  (chan, 8);
-	BEGIN_RING(chan, kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LINE_SMOOTH_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_MODE_FRONT, 2);
-	OUT_RING  (chan, NV20TCL_POLYGON_MODE_FRONT_FILL);
-	OUT_RING  (chan, NV20TCL_POLYGON_MODE_BACK_FILL);
-	BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE, 2);
-	OUT_RING  (chan, NV20TCL_CULL_FACE_BACK);
-	OUT_RING  (chan, NV20TCL_FRONT_FACE_CCW);
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_MODE_FRONT, 2);
+	OUT_RING  (chan, NV20_3D_POLYGON_MODE_FRONT_FILL);
+	OUT_RING  (chan, NV20_3D_POLYGON_MODE_BACK_FILL);
+	BEGIN_RING(chan, kelvin, NV20_3D_CULL_FACE, 2);
+	OUT_RING  (chan, NV20_3D_CULL_FACE_BACK);
+	OUT_RING  (chan, NV20_3D_FRONT_FACE_CCW);
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_SMOOTH_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_CULL_FACE_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_CULL_FACE_ENABLE, 1);
 	OUT_RING  (chan, 0);
-	BEGIN_RING(chan, kelvin, NV20TCL_SHADE_MODEL, 1);
-	OUT_RING  (chan, NV20TCL_SHADE_MODEL_SMOOTH);
-	BEGIN_RING(chan, kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_SHADE_MODEL, 1);
+	OUT_RING  (chan, NV20_3D_SHADE_MODEL_SMOOTH);
+	BEGIN_RING(chan, kelvin, NV20_3D_POLYGON_STIPPLE_ENABLE, 1);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_GEN_MODE_S(0),
-		   4 * NV20TCL_TX_GEN_MODE_S__SIZE);
-	for (i=0; i < 4 * NV20TCL_TX_GEN_MODE_S__SIZE; i++)
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_GEN_MODE(0,0),
+		   4 * NV20_3D_TEX_GEN_MODE__ESIZE);
+	for (i=0; i < 4 * NV20_3D_TEX_GEN_MODE__LEN; i++)
 		OUT_RING(chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
+	BEGIN_RING(chan, kelvin, NV20_3D_FOG_COEFF(0), 3);
 	OUT_RINGf (chan, 1.5);
 	OUT_RINGf (chan, -0.090168);
 	OUT_RINGf (chan, 0.0);
-	BEGIN_RING(chan, kelvin, NV20TCL_FOG_MODE, 2);
-	OUT_RING  (chan, NV20TCL_FOG_MODE_EXP_SIGNED);
-	OUT_RING  (chan, NV20TCL_FOG_COORD_FOG);
-	BEGIN_RING(chan, kelvin, NV20TCL_FOG_ENABLE, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_FOG_MODE, 2);
+	OUT_RING  (chan, NV20_3D_FOG_MODE_EXP_SIGNED);
+	OUT_RING  (chan, NV20_3D_FOG_COORD_FOG);
+	BEGIN_RING(chan, kelvin, NV20_3D_FOG_ENABLE, 2);
 	OUT_RING  (chan, 0);
 	OUT_RING  (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_ENGINE, 1);
-	OUT_RING  (chan, NV20TCL_ENGINE_FIXED);
+	BEGIN_RING(chan, kelvin, NV20_3D_ENGINE, 1);
+	OUT_RING  (chan, NV20_3D_ENGINE_FIXED);
 
-	for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; i++) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
+	for (i = 0; i < NV20_3D_TEX_MATRIX_ENABLE__LEN; i++) {
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_MATRIX_ENABLE(i), 1);
 		OUT_RING  (chan, 0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15);
+	BEGIN_RING(chan, kelvin, NV20_3D_VERTEX_ATTR_4F_X(1), 4 * 15);
 	OUT_RINGf(chan, 1.0);
 	OUT_RINGf(chan, 0.0);
 	OUT_RINGf(chan, 0.0);
@@ -393,24 +394,24 @@ nv20_hwctx_init(struct gl_context *ctx)
 		OUT_RINGf(chan, 1.0);
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_EDGEFLAG_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_EDGEFLAG_ENABLE, 1);
 	OUT_RING  (chan, 1);
-	BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MASK, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_COLOR_MASK, 1);
 	OUT_RING (chan, 0x00010101);
-	BEGIN_RING(chan, kelvin, NV20TCL_CLEAR_VALUE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_CLEAR_VALUE, 1);
 	OUT_RING (chan, 0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_DEPTH_RANGE_NEAR, 2);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 16777216.0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_TRANSLATE_X, 4);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 16777215.0);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_SCALE_X, 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_SCALE_X, 4);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 0.0);
 	OUT_RINGf (chan, 16777215.0 * 0.5);
@@ -469,9 +470,9 @@ nv20_context_create(struct nouveau_screen *screen, const struct gl_config *visua
 
 	/* 3D engine. */
 	if (context_chipset(ctx) >= 0x25)
-		kelvin_class = NV25TCL;
+		kelvin_class = NV25_3D;
 	else
-		kelvin_class = NV20TCL;
+		kelvin_class = NV20_3D;
 
 	ret = nouveau_grobj_alloc(context_chan(ctx), 0xbeef0001, kelvin_class,
 				  &nctx->hw.eng3d);
diff --git a/src/mesa/drivers/dri/nouveau/nv20_render.c b/src/mesa/drivers/dri/nouveau/nv20_render.c
index dbdb85da20..2bdc85cda4 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_render.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_render.c
@@ -26,7 +26,7 @@
 
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv20_driver.h"
 
 #define NUM_VERTEX_ATTRS 16
@@ -39,47 +39,47 @@ nv20_emit_material(struct gl_context *ctx, struct nouveau_array *a,
 static struct nouveau_attr_info nv20_vertex_attrs[VERT_ATTRIB_MAX] = {
 	[VERT_ATTRIB_POS] = {
 		.vbo_index = 0,
-		.imm_method = NV20TCL_VERTEX_POS_4F_X,
+		.imm_method = NV20_3D_VERTEX_POS_4F_X,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_NORMAL] = {
 		.vbo_index = 2,
-		.imm_method = NV20TCL_VERTEX_NOR_3F_X,
+		.imm_method = NV20_3D_VERTEX_NOR_3F_X,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_COLOR0] = {
 		.vbo_index = 3,
-		.imm_method = NV20TCL_VERTEX_COL_4F_X,
+		.imm_method = NV20_3D_VERTEX_COL_4F,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_COLOR1] = {
 		.vbo_index = 4,
-		.imm_method = NV20TCL_VERTEX_COL2_3F_X,
+		.imm_method = NV20_3D_VERTEX_COL2_3F,
 		.imm_fields = 3,
 	},
 	[VERT_ATTRIB_FOG] = {
 		.vbo_index = 5,
-		.imm_method = NV20TCL_VERTEX_FOG_1F,
+		.imm_method = NV20_3D_VERTEX_FOG_1F,
 		.imm_fields = 1,
 	},
 	[VERT_ATTRIB_TEX0] = {
 		.vbo_index = 9,
-		.imm_method = NV20TCL_VERTEX_TX0_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX0_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX1] = {
 		.vbo_index = 10,
-		.imm_method = NV20TCL_VERTEX_TX1_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX1_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX2] = {
 		.vbo_index = 11,
-		.imm_method = NV20TCL_VERTEX_TX2_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX2_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_TEX3] = {
 		.vbo_index = 12,
-		.imm_method = NV20TCL_VERTEX_TX3_4F_S,
+		.imm_method = NV20_3D_VERTEX_TX3_4F_S,
 		.imm_fields = 4,
 	},
 	[VERT_ATTRIB_GENERIC0] = {
@@ -119,11 +119,11 @@ get_hw_format(int type)
 {
 	switch (type) {
 	case GL_FLOAT:
-		return NV20TCL_VTXFMT_TYPE_FLOAT;
+		return NV20_3D_VTXBUF_FMT_TYPE_FLOAT;
 	case GL_UNSIGNED_SHORT:
-		return NV20TCL_VTXFMT_TYPE_USHORT;
+		return NV20_3D_VTXBUF_FMT_TYPE_USHORT;
 	case GL_UNSIGNED_BYTE:
-		return NV20TCL_VTXFMT_TYPE_UBYTE;
+		return NV20_3D_VTXBUF_FMT_TYPE_UBYTE;
 	default:
 		assert(0);
 	}
@@ -147,10 +147,10 @@ nv20_render_set_format(struct gl_context *ctx)
 
 		} else {
 			/* Unused attribute. */
-			hw_format = NV10TCL_VTXFMT_TYPE_FLOAT;
+			hw_format = NV20_3D_VTXBUF_FMT_TYPE_FLOAT;
 		}
 
-		BEGIN_RING(chan, kelvin, NV20TCL_VTXFMT(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_VTXBUF_FMT(i), 1);
 		OUT_RING(chan, hw_format);
 	}
 }
@@ -167,9 +167,9 @@ nv20_render_bind_vertices(struct gl_context *ctx)
 		struct nouveau_array *a = &render->attrs[attr];
 
 		nouveau_bo_mark(bctx, kelvin,
-				NV20TCL_VTXBUF_ADDRESS(i),
+				NV20_3D_VTXBUF_OFFSET(i),
 				a->bo, a->offset, 0,
-				0, NV20TCL_VTXBUF_ADDRESS_DMA1,
+				0, NV20_3D_VTXBUF_OFFSET_DMA1,
 				NOUVEAU_BO_LOW | NOUVEAU_BO_OR |
 				NOUVEAU_BO_GART | NOUVEAU_BO_RD);
 	}
@@ -180,33 +180,33 @@ nv20_render_bind_vertices(struct gl_context *ctx)
 	struct nouveau_grobj *kelvin = context_eng3d(ctx)
 
 #define BATCH_VALIDATE()						\
-	BEGIN_RING(chan, kelvin, NV20TCL_VTX_CACHE_INVALIDATE, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VTXBUF_VALIDATE, 1);	\
 	OUT_RING(chan, 0)
 
 #define BATCH_BEGIN(prim)					\
-	BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VERTEX_BEGIN_END, 1);	\
 	OUT_RING(chan, prim)
 #define BATCH_END()						\
-	BEGIN_RING(chan, kelvin, NV20TCL_VERTEX_BEGIN_END, 1);	\
+	BEGIN_RING(chan, kelvin, NV20_3D_VERTEX_BEGIN_END, 1);	\
 	OUT_RING(chan, 0)
 
 #define MAX_PACKET 0x400
 
 #define MAX_OUT_L 0x100
 #define BATCH_PACKET_L(n)						\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_VERTEX_BATCH, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_BATCH, n)
 #define BATCH_OUT_L(i, n)			\
 	OUT_RING(chan, ((n) - 1) << 24 | (i))
 
 #define MAX_OUT_I16 0x2
 #define BATCH_PACKET_I16(n)					\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_ELEMENT_U16, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_ELEMENT_U16, n)
 #define BATCH_OUT_I16(i0, i1)			\
 	OUT_RING(chan, (i1) << 16 | (i0))
 
 #define MAX_OUT_I32 0x1
 #define BATCH_PACKET_I32(n)					\
-	BEGIN_RING_NI(chan, kelvin, NV20TCL_VB_ELEMENT_U32, n)
+	BEGIN_RING_NI(chan, kelvin, NV20_3D_VTXBUF_ELEMENT_U32, n)
 #define BATCH_OUT_I32(i)			\
 	OUT_RING(chan, i)
 
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
index 854392f9ff..cbde74e4fc 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_fb.c
@@ -29,7 +29,7 @@
 #include "nouveau_fbo.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv20_driver.h"
 
 static inline unsigned
@@ -37,15 +37,15 @@ get_rt_format(gl_format format)
 {
 	switch (format) {
 	case MESA_FORMAT_XRGB8888:
-		return 0x05;
+		return NV20_3D_RT_FORMAT_COLOR_X8R8G8B8;
 	case MESA_FORMAT_ARGB8888:
-		return 0x08;
+		return NV20_3D_RT_FORMAT_COLOR_A8R8G8B8;
 	case MESA_FORMAT_RGB565:
-		return 0x03;
+		return NV20_3D_RT_FORMAT_COLOR_R5G6B5;
 	case MESA_FORMAT_Z16:
-		return 0x10;
+		return NV20_3D_RT_FORMAT_DEPTH_Z16;
 	case MESA_FORMAT_Z24_S8:
-		return 0x20;
+		return NV20_3D_RT_FORMAT_DEPTH_Z24S8;
 	default:
 		assert(0);
 	}
@@ -69,10 +69,10 @@ setup_hierz_buffer(struct gl_context *ctx)
 			       &nfb->hierz.bo);
 	}
 
-	BEGIN_RING(chan, kelvin, NV25TCL_HIERZ_PITCH, 1);
+	BEGIN_RING(chan, kelvin, NV25_3D_HIERZ_PITCH, 1);
 	OUT_RING(chan, pitch);
 
-	nouveau_bo_markl(bctx, kelvin, NV25TCL_HIERZ_OFFSET, nfb->hierz.bo,
+	nouveau_bo_markl(bctx, kelvin, NV25_3D_HIERZ_OFFSET, nfb->hierz.bo,
 			 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
 }
 
@@ -84,7 +84,7 @@ nv20_emit_framebuffer(struct gl_context *ctx, int emit)
 	struct nouveau_bo_context *bctx = context_bctx(ctx, FRAMEBUFFER);
 	struct gl_framebuffer *fb = ctx->DrawBuffer;
 	struct nouveau_surface *s;
-	unsigned rt_format = NV20TCL_RT_FORMAT_TYPE_LINEAR;
+	unsigned rt_format = NV20_3D_RT_FORMAT_TYPE_LINEAR;
 	unsigned rt_pitch = 0, zeta_pitch = 0;
 	unsigned bo_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
 
@@ -99,7 +99,7 @@ nv20_emit_framebuffer(struct gl_context *ctx, int emit)
 		rt_format |= get_rt_format(s->format);
 		rt_pitch = s->pitch;
 
-		nouveau_bo_markl(bctx, kelvin, NV20TCL_COLOR_OFFSET,
+		nouveau_bo_markl(bctx, kelvin, NV20_3D_COLOR_OFFSET,
 				 s->bo, 0, bo_flags);
 	}
 
@@ -111,7 +111,7 @@ nv20_emit_framebuffer(struct gl_context *ctx, int emit)
 		rt_format |= get_rt_format(s->format);
 		zeta_pitch = s->pitch;
 
-		nouveau_bo_markl(bctx, kelvin, NV20TCL_ZETA_OFFSET,
+		nouveau_bo_markl(bctx, kelvin, NV20_3D_ZETA_OFFSET,
 				 s->bo, 0, bo_flags);
 
 		if (context_chipset(ctx) >= 0x25)
@@ -121,7 +121,7 @@ nv20_emit_framebuffer(struct gl_context *ctx, int emit)
 		zeta_pitch = rt_pitch;
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RT_FORMAT, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RT_FORMAT, 2);
 	OUT_RING(chan, rt_format);
 	OUT_RING(chan, zeta_pitch << 16 | rt_pitch);
 
@@ -140,12 +140,12 @@ nv20_emit_viewport(struct gl_context *ctx, int emit)
 
 	get_viewport_translate(ctx, a);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_TRANSLATE_X, 4);
 	OUT_RINGp(chan, a, 4);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_HORIZ(0), 1);
 	OUT_RING(chan, (fb->Width - 1) << 16);
-	BEGIN_RING(chan, kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_VIEWPORT_CLIP_VERT(0), 1);
 	OUT_RING(chan, (fb->Height - 1) << 16);
 
 	context_dirty(ctx, PROJECTION);
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_frag.c b/src/mesa/drivers/dri/nouveau/nv20_state_frag.c
index f9212d8b39..0624de442b 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_frag.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_frag.c
@@ -26,7 +26,7 @@
 
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv10_driver.h"
 #include "nv20_driver.h"
 
@@ -40,15 +40,15 @@ nv20_emit_tex_env(struct gl_context *ctx, int emit)
 
 	nv10_get_general_combiner(ctx, i, &a_in, &a_out, &c_in, &c_out, &k);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_ALPHA(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_IN_ALPHA(i), 1);
 	OUT_RING(chan, a_in);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_ALPHA(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_OUT_ALPHA(i), 1);
 	OUT_RING(chan, a_out);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_IN_RGB(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_IN_RGB(i), 1);
 	OUT_RING(chan, c_in);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_OUT_RGB(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_OUT_RGB(i), 1);
 	OUT_RING(chan, c_out);
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_CONSTANT_COLOR0(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_CONSTANT_COLOR0(i), 1);
 	OUT_RING(chan, k);
 
 	context_dirty(ctx, FRAG);
@@ -64,10 +64,10 @@ nv20_emit_frag(struct gl_context *ctx, int emit)
 
 	nv10_get_final_combiner(ctx, &in, &n);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_FINAL0, 2);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_FINAL0, 2);
 	OUT_RING(chan, in);
 	OUT_RING(chan, in >> 32);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_RC_ENABLE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_RC_ENABLE, 1);
 	OUT_RING(chan, n);
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c b/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c
index a6e237f8c4..85f30dc4d4 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_polygon.c
@@ -27,7 +27,7 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv20_driver.h"
 
 void
@@ -36,7 +36,7 @@ nv20_emit_point_mode(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *kelvin = context_eng3d(ctx);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_POINT_SIZE, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_POINT_SIZE, 1);
 	if (context_chipset(ctx) >= 0x25)
 		OUT_RINGf(chan, ctx->Point.Size);
 	else
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_raster.c b/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
index 0fc7a3259d..3fb4ecae89 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_raster.c
@@ -27,7 +27,8 @@
 #include "nouveau_driver.h"
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
-#include "nouveau_class.h"
+#include "nouveau_util.h"
+#include "nv20_3d.xml.h"
 #include "nv20_driver.h"
 
 void
@@ -36,7 +37,7 @@ nv20_emit_logic_opcode(struct gl_context *ctx, int emit)
 	struct nouveau_channel *chan = context_chan(ctx);
 	struct nouveau_grobj *kelvin = context_eng3d(ctx);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2);
-	OUT_RING(chan, ctx->Color.ColorLogicOpEnabled ? 1 : 0);
+	BEGIN_RING(chan, kelvin, NV20_3D_COLOR_LOGIC_OP_ENABLE, 2);
+	OUT_RINGb(chan, ctx->Color.ColorLogicOpEnabled);
 	OUT_RING(chan, nvgl_logicop_func(ctx->Color.LogicOp));
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tex.c b/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
index cfff1fe839..c362aca0fd 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_tex.c
@@ -28,14 +28,10 @@
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_texture.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nouveau_util.h"
 #include "nv20_driver.h"
 
-#define TX_GEN_MODE(i, j) (NV20TCL_TX_GEN_MODE_S(i) + 4 * (j))
-#define TX_GEN_COEFF(i, j) (NV20TCL_TX_GEN_COEFF_S_A(i) + 16 * (j))
-#define TX_MATRIX(i) (NV20TCL_TX0_MATRIX(0) + 64 * (i))
-
 void
 nv20_emit_tex_gen(struct gl_context *ctx, int emit)
 {
@@ -52,15 +48,16 @@ nv20_emit_tex_gen(struct gl_context *ctx, int emit)
 			float *k = get_texgen_coeff(coord);
 
 			if (k) {
-				BEGIN_RING(chan, kelvin, TX_GEN_COEFF(i, j), 4);
+				BEGIN_RING(chan, kelvin,
+					   NV20_3D_TEX_GEN_COEFF(i, j), 4);
 				OUT_RINGp(chan, k, 4);
 			}
 
-			BEGIN_RING(chan, kelvin, TX_GEN_MODE(i, j), 1);
+			BEGIN_RING(chan, kelvin, NV20_3D_TEX_GEN_MODE(i, j), 1);
 			OUT_RING(chan, nvgl_texgen_mode(coord->Mode));
 
 		} else {
-			BEGIN_RING(chan, kelvin, TX_GEN_MODE(i, j), 1);
+			BEGIN_RING(chan, kelvin, NV20_3D_TEX_GEN_MODE(i, j), 1);
 			OUT_RING(chan, 0);
 		}
 	}
@@ -76,14 +73,14 @@ nv20_emit_tex_mat(struct gl_context *ctx, int emit)
 
 	if (nctx->fallback == HWTNL &&
 	    (ctx->Texture._TexMatEnabled & 1 << i)) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_MATRIX_ENABLE(i), 1);
 		OUT_RING(chan, 1);
 
-		BEGIN_RING(chan, kelvin, TX_MATRIX(i), 16);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_MATRIX(i,0), 16);
 		OUT_RINGm(chan, ctx->TextureMatrixStack[i].Top->m);
 
 	} else {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_MATRIX_ENABLE(i), 1);
 		OUT_RING(chan, 0);
 	}
 }
@@ -93,29 +90,29 @@ get_tex_format_pot(struct gl_texture_image *ti)
 {
 	switch (ti->TexFormat) {
 	case MESA_FORMAT_ARGB8888:
-		return NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8;
+		return NV20_3D_TEX_FORMAT_FORMAT_A8R8G8B8;
 
 	case MESA_FORMAT_ARGB1555:
-		return NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5;
+		return NV20_3D_TEX_FORMAT_FORMAT_A1R5G5B5;
 
 	case MESA_FORMAT_ARGB4444:
-		return NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4;
+		return NV20_3D_TEX_FORMAT_FORMAT_A4R4G4B4;
 
 	case MESA_FORMAT_XRGB8888:
-		return NV20TCL_TX_FORMAT_FORMAT_X8R8G8B8;
+		return NV20_3D_TEX_FORMAT_FORMAT_X8R8G8B8;
 
 	case MESA_FORMAT_RGB565:
-		return NV20TCL_TX_FORMAT_FORMAT_R5G6B5;
+		return NV20_3D_TEX_FORMAT_FORMAT_R5G6B5;
 
 	case MESA_FORMAT_A8:
 	case MESA_FORMAT_I8:
-		return NV20TCL_TX_FORMAT_FORMAT_A8;
+		return NV20_3D_TEX_FORMAT_FORMAT_I8;
 
 	case MESA_FORMAT_L8:
-		return NV20TCL_TX_FORMAT_FORMAT_L8;
+		return NV20_3D_TEX_FORMAT_FORMAT_L8;
 
 	case MESA_FORMAT_CI8:
-		return NV20TCL_TX_FORMAT_FORMAT_INDEX8;
+		return NV20_3D_TEX_FORMAT_FORMAT_INDEX8;
 
 	default:
 		assert(0);
@@ -127,26 +124,26 @@ get_tex_format_rect(struct gl_texture_image *ti)
 {
 	switch (ti->TexFormat) {
 	case MESA_FORMAT_ARGB8888:
-		return NV20TCL_TX_FORMAT_FORMAT_A8R8G8B8_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_A8R8G8B8_RECT;
 
 	case MESA_FORMAT_ARGB1555:
-		return NV20TCL_TX_FORMAT_FORMAT_A1R5G5B5_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_A1R5G5B5_RECT;
 
 	case MESA_FORMAT_ARGB4444:
-		return NV20TCL_TX_FORMAT_FORMAT_A4R4G4B4_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_A4R4G4B4_RECT;
 
 	case MESA_FORMAT_XRGB8888:
-		return NV20TCL_TX_FORMAT_FORMAT_R8G8B8_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_R8G8B8_RECT;
 
 	case MESA_FORMAT_RGB565:
-		return NV20TCL_TX_FORMAT_FORMAT_R5G6B5_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_R5G6B5_RECT;
 
 	case MESA_FORMAT_L8:
-		return NV20TCL_TX_FORMAT_FORMAT_L8_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_L8_RECT;
 
 	case MESA_FORMAT_A8:
 	case MESA_FORMAT_I8:
-		return NV20TCL_TX_FORMAT_FORMAT_A8_RECT;
+		return NV20_3D_TEX_FORMAT_FORMAT_I8_RECT;
 
 	default:
 		assert(0);
@@ -167,7 +164,7 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
 	uint32_t tx_format, tx_filter, tx_wrap, tx_enable;
 
 	if (!ctx->Texture.Unit[i]._ReallyEnabled) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_ENABLE(i), 1);
 		OUT_RING(chan, 0);
 
 		context_dirty(ctx, TEX_SHADER);
@@ -185,8 +182,8 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
 	tx_format = ti->DepthLog2 << 28
 		| ti->HeightLog2 << 24
 		| ti->WidthLog2 << 20
-		| NV20TCL_TX_FORMAT_DIMS_2D
-		| NV20TCL_TX_FORMAT_NO_BORDER
+		| NV20_3D_TEX_FORMAT_DIMS_2D
+		| NV20_3D_TEX_FORMAT_NO_BORDER
 		| 1 << 16;
 
 	tx_wrap = nvgl_wrap_mode(t->WrapR) << 16
@@ -197,13 +194,13 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
 		| nvgl_filter_mode(t->MinFilter) << 16
 		| 2 << 12;
 
-	tx_enable = NV20TCL_TX_ENABLE_ENABLE
+	tx_enable = NV20_3D_TEX_ENABLE_ENABLE
 		| log2i(t->MaxAnisotropy) << 4;
 
 	if (t->Target == GL_TEXTURE_RECTANGLE) {
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_NPOT_PITCH(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_NPOT_PITCH(i), 1);
 		OUT_RING(chan, s->pitch << 16);
-		BEGIN_RING(chan, kelvin, NV20TCL_TX_NPOT_SIZE(i), 1);
+		BEGIN_RING(chan, kelvin, NV20_3D_TEX_NPOT_SIZE(i), 1);
 		OUT_RING(chan, s->width << 16 | s->height);
 
 		tx_format |= get_tex_format_rect(ti);
@@ -222,29 +219,29 @@ nv20_emit_tex_obj(struct gl_context *ctx, int emit)
 		lod_min = CLAMP(lod_min, 0, 15);
 		lod_bias = CLAMP(lod_bias, 0, 15);
 
-		tx_format |= NV20TCL_TX_FORMAT_MIPMAP;
+		tx_format |= NV20_3D_TEX_FORMAT_MIPMAP;
 		tx_filter |= lod_bias << 8;
 		tx_enable |= lod_min << 26
 			| lod_max << 14;
 	}
 
 	/* Write it to the hardware. */
-	nouveau_bo_mark(bctx, kelvin, NV20TCL_TX_FORMAT(i),
+	nouveau_bo_mark(bctx, kelvin, NV20_3D_TEX_FORMAT(i),
 			s->bo, tx_format, 0,
-			NV20TCL_TX_FORMAT_DMA0,
-			NV20TCL_TX_FORMAT_DMA1,
+			NV20_3D_TEX_FORMAT_DMA0,
+			NV20_3D_TEX_FORMAT_DMA1,
 			bo_flags | NOUVEAU_BO_OR);
 
-	nouveau_bo_markl(bctx, kelvin, NV20TCL_TX_OFFSET(i),
+	nouveau_bo_markl(bctx, kelvin, NV20_3D_TEX_OFFSET(i),
 			 s->bo, s->offset, bo_flags);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_WRAP(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_WRAP(i), 1);
 	OUT_RING(chan, tx_wrap);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_FILTER(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_FILTER(i), 1);
 	OUT_RING(chan, tx_filter);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_ENABLE(i), 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_ENABLE(i), 1);
 	OUT_RING(chan, tx_enable);
 
 	context_dirty(ctx, TEX_SHADER);
@@ -262,9 +259,9 @@ nv20_emit_tex_shader(struct gl_context *ctx, int emit)
 		if (!ctx->Texture.Unit[i]._ReallyEnabled)
 			continue;
 
-		tx_shader_op |= NV20TCL_TX_SHADER_OP_TX0_TEXTURE_2D << 5 * i;
+		tx_shader_op |= NV20_3D_TEX_SHADER_OP_TX0_TEXTURE_2D << 5 * i;
 	}
 
-	BEGIN_RING(chan, kelvin, NV20TCL_TX_SHADER_OP, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_TEX_SHADER_OP, 1);
 	OUT_RING(chan, tx_shader_op);
 }
diff --git a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
index b65cd9ad87..4677198dd0 100644
--- a/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
+++ b/src/mesa/drivers/dri/nouveau/nv20_state_tnl.c
@@ -28,31 +28,31 @@
 #include "nouveau_context.h"
 #include "nouveau_gldefs.h"
 #include "nouveau_util.h"
-#include "nouveau_class.h"
+#include "nv20_3d.xml.h"
 #include "nv10_driver.h"
 #include "nv20_driver.h"
 
 #define LIGHT_MODEL_AMBIENT_R(side)			\
-	((side) ? NV20TCL_LIGHT_MODEL_BACK_AMBIENT_R :	\
-	 NV20TCL_LIGHT_MODEL_FRONT_AMBIENT_R)
+	((side) ? NV20_3D_LIGHT_MODEL_BACK_AMBIENT_R :	\
+	 NV20_3D_LIGHT_MODEL_FRONT_AMBIENT_R)
 #define LIGHT_AMBIENT_R(side, i)			\
-	((side) ? NV20TCL_LIGHT_BACK_AMBIENT_R(i) :	\
-	 NV20TCL_LIGHT_FRONT_AMBIENT_R(i))
+	((side) ? NV20_3D_LIGHT_BACK_AMBIENT_R(i) :	\
+	 NV20_3D_LIGHT_FRONT_AMBIENT_R(i))
 #define LIGHT_DIFFUSE_R(side, i)			\
-	((side) ? NV20TCL_LIGHT_BACK_DIFFUSE_R(i) :	\
-	 NV20TCL_LIGHT_FRONT_DIFFUSE_R(i))
+	((side) ? NV20_3D_LIGHT_BACK_DIFFUSE_R(i) :	\
+	 NV20_3D_LIGHT_FRONT_DIFFUSE_R(i))
 #define LIGHT_SPECULAR_R(side, i)			\
-	((side) ? NV20TCL_LIGHT_BACK_SPECULAR_R(i) :	\
-	 NV20TCL_LIGHT_FRONT_SPECULAR_R(i))
+	((side) ? NV20_3D_LIGHT_BACK_SPECULAR_R(i) :	\
+	 NV20_3D_LIGHT_FRONT_SPECULAR_R(i))
 #define MATERIAL_FACTOR_R(side)				\
-	((side) ? NV20TCL_MATERIAL_FACTOR_BACK_R :	\
-	 NV20TCL_MATERIAL_FACTOR_FRONT_R)
+	((side) ? NV20_3D_MATERIAL_FACTOR_BACK_R :	\
+	 NV20_3D_MATERIAL_FACTOR_FRONT_R)
 #define MATERIAL_FACTOR_A(side)				\
-	((side) ? NV20TCL_MATERIAL_FACTOR_BACK_A :	\
-	 NV20TCL_MATERIAL_FACTOR_FRONT_A)
+	((side) ? NV20_3D_MATERIAL_FACTOR_BACK_A :	\
+	 NV20_3D_MATERIAL_FACTOR_FRONT_A)
 #define MATERIAL_SHININESS(side)			\
-	((side) ? NV20TCL_BACK_MATERIAL_SHININESS(0) :	\
-	 NV20TCL_FRONT_MATERIAL_SHININESS(0))
+	((side) ? NV20_3D_BACK_MATERIAL_SHININESS(0) :	\
+	 NV20_3D_FRONT_MATERIAL_SHININESS(0))
 
 void
 nv20_emit_clip_plane(struct gl_context *ctx, int emit)
@@ -65,22 +65,22 @@ get_material_bitmask(unsigned m)
 	unsigned ret = 0;
 
 	if (m & MAT_BIT_FRONT_EMISSION)
-		ret |= NV20TCL_COLOR_MATERIAL_FRONT_EMISSION_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_FRONT_EMISSION_COL1;
 	if (m & MAT_BIT_FRONT_AMBIENT)
-		ret |= NV20TCL_COLOR_MATERIAL_FRONT_AMBIENT_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_FRONT_AMBIENT_COL1;
 	if (m & MAT_BIT_FRONT_DIFFUSE)
-		ret |= NV20TCL_COLOR_MATERIAL_FRONT_DIFFUSE_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_FRONT_DIFFUSE_COL1;
 	if (m & MAT_BIT_FRONT_SPECULAR)
-		ret |= NV20TCL_COLOR_MATERIAL_FRONT_SPECULAR_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_FRONT_SPECULAR_COL1;
 
 	if (m & MAT_BIT_BACK_EMISSION)
-		ret |= NV20TCL_COLOR_MATERIAL_BACK_EMISSION_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_BACK_EMISSION_COL1;
 	if (m & MAT_BIT_BACK_AMBIENT)
-		ret |= NV20TCL_COLOR_MATERIAL_BACK_AMBIENT_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_BACK_AMBIENT_COL1;
 	if (m & MAT_BIT_BACK_DIFFUSE)
-		ret |= NV20TCL_COLOR_MATERIAL_BACK_DIFFUSE_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_BACK_DIFFUSE_COL1;
 	if (m & MAT_BIT_BACK_SPECULAR)
-		ret |= NV20TCL_COLOR_MATERIAL_BACK_SPECULAR_COL1;
+		ret |= NV20_3D_COLOR_MATERIAL_BACK_SPECULAR_COL1;
 
 	return ret;
 }
@@ -92,7 +92,7 @@ nv20_emit_color_material(struct gl_context *ctx, int emit)
 	struct nouveau_grobj *kelvin = context_eng3d(ctx);
 	unsigned mask = get_material_bitmask(ctx->Light.ColorMaterialBitmask);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_COLOR_MATERIAL, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_COLOR_MATERIAL, 1);
 	OUT_RING(chan, ctx->Light.ColorMaterialEnabled ? mask : 0);
 }
 
@@ -101,11 +101,11 @@ get_fog_mode_signed(unsigned mode)
 {
 	switch (mode) {
 	case GL_LINEAR:
-		return NV20TCL_FOG_MODE_LINEAR_SIGNED;
+		return NV20_3D_FOG_MODE_LINEAR_SIGNED;
 	case GL_EXP:
-		return NV20TCL_FOG_MODE_EXP_SIGNED;
+		return NV20_3D_FOG_MODE_EXP_SIGNED;
 	case GL_EXP2:
-		return NV20TCL_FOG_MODE_EXP2_SIGNED;
+		return NV20_3D_FOG_MODE_EXP2_SIGNED;
 	default:
 		assert(0);
 	}
@@ -116,11 +116,11 @@ get_fog_mode_unsigned(unsigned mode)
 {
 	switch (mode) {
 	case GL_LINEAR:
-		return NV20TCL_FOG_MODE_LINEAR_UNSIGNED;
+		return NV20_3D_FOG_MODE_LINEAR_UNSIGNED;
 	case GL_EXP:
-		return NV20TCL_FOG_MODE_EXP_UNSIGNED;
+		return NV20_3D_FOG_MODE_EXP_UNSIGNED;
 	case GL_EXP2:
-		return NV20TCL_FOG_MODE_EXP2_UNSIGNED;
+		return NV20_3D_FOG_MODE_EXP2_UNSIGNED;
 	default:
 		assert(0);
 	}
@@ -131,9 +131,9 @@ get_fog_source(unsigned source)
 {
 	switch (source) {
 	case GL_FOG_COORDINATE_EXT:
-		return NV20TCL_FOG_COORD_FOG;
+		return NV20_3D_FOG_COORD_FOG;
 	case GL_FRAGMENT_DEPTH_EXT:
-		return NV20TCL_FOG_COORD_DIST_ORTHOGONAL_ABS;
+		return NV20_3D_FOG_COORD_DIST_ORTHOGONAL_ABS;
 	default:
 		assert(0);
 	}
@@ -152,15 +152,15 @@ nv20_emit_fog(struct gl_context *ctx, int emit)
 
 	nv10_get_fog_coeff(ctx, k);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_FOG_MODE, 4);
+	BEGIN_RING(chan, kelvin, NV20_3D_FOG_MODE, 4);
 	OUT_RING(chan, (source == GL_FOG_COORDINATE_EXT ?
 			get_fog_mode_signed(f->Mode) :
 			get_fog_mode_unsigned(f->Mode)));
 	OUT_RING(chan, get_fog_source(source));
-	OUT_RING(chan, f->Enabled ? 1 : 0);
+	OUT_RINGb(chan, f->Enabled);
 	OUT_RING(chan, pack_rgba_f(MESA_FORMAT_RGBA8888_REV, f->Color));
 
-	BEGIN_RING(chan, kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3);
+	BEGIN_RING(chan, kelvin, NV20_3D_FOG_COEFF(0), 3);
 	OUT_RINGp(chan, k, 3);
 }
 
@@ -171,19 +171,19 @@ nv20_emit_light_model(struct gl_context *ctx, int emit)
 	struct nouveau_grobj *kelvin = context_eng3d(ctx);
 	struct gl_lightmodel *m = &ctx->Light.Model;
 
-	BEGIN_RING(chan, kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1);
-	OUT_RING(chan, m->ColorControl == GL_SEPARATE_SPECULAR_COLOR ? 1 : 0);
+	BEGIN_RING(chan, kelvin, NV20_3D_SEPARATE_SPECULAR_ENABLE, 1);
+	OUT_RINGb(chan, m->ColorControl == GL_SEPARATE_SPECULAR_COLOR);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL, 1);
+	BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_MODEL, 1);
 	OUT_RING(chan, ((m->LocalViewer ?
-			 NV20TCL_LIGHT_MODEL_VIEWER_LOCAL :
-			 NV20TCL_LIGHT_MODEL_VIEWER_NONLOCAL) |
+			 NV20_3D_LIGHT_MODEL_VIEWER_LOCAL :
+			 NV20_3D_LIGHT_MODEL_VIEWER_NONLOCAL) |
 			(NEED_SECONDARY_COLOR(ctx) ?
-			 NV20TCL_LIGHT_MODEL_SEPARATE_SPECULAR :
+			 NV20_3D_LIGHT_MODEL_SEPARATE_SPECULAR :
 			 0)));
 
-	BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
-	OUT_RING(chan, ctx->Light.Model.TwoSide ? 1 : 0);
+	BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_MODEL_TWO_SIDE_ENABLE, 1);
+	OUT_RINGb(chan, ctx->Light.Model.TwoSide);
 }
 
 void
@@ -195,19 +195,19 @@ nv20_emit_light_source(struct gl_context *ctx, int emit)
 	struct gl_light *l = &ctx->Light.Light[i];
 
 	if (l->_Flags & LIGHT_POSITIONAL) {
-		BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_POSITION_X(i), 3);
+		BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_POSITION_X(i), 3);
 		OUT_RINGp(chan, l->_Position, 3);
 
-		BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_ATTENUATION_CONSTANT(i), 3);
+		BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_ATTENUATION_CONSTANT(i), 3);
 		OUT_RINGf(chan, l->ConstantAttenuation);
 		OUT_RINGf(chan, l->LinearAttenuation);
 		OUT_RINGf(chan, l->QuadraticAttenuation);
 
 	} else {
-		BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_DIRECTION_X(i), 3);
+		BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_DIRECTION_X(i), 3);
 		OUT_RINGp(chan, l->_VP_inf_norm, 3);
 
-		BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_HALF_VECTOR_X(i), 3);
+		BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_HALF_VECTOR_X(i), 3);
 		OUT_RINGp(chan, l->_h_inf_norm, 3);
 	}
 
@@ -216,7 +216,7 @@ nv20_emit_light_source(struct gl_context *ctx, int emit)
 
 		nv10_get_spot_coeff(l, k);
 
-		BEGIN_RING(chan, kelvin, NV20TCL_LIGHT_SPOT_CUTOFF_A(i), 7);
+		BEGIN_RING(chan, kelvin, NV20_3D_LIGHT_SPOT_CUTOFF(i, 0), 7);
 		OUT_RINGp(chan, k, 7);
 	}
 }
@@ -340,7 +340,7 @@ nv20_emit_modelview(struct gl_context *ctx, int emit)
 
 	if (ctx->Light._NeedEyeCoords || ctx->Fog.Enabled ||
 	    (ctx->Texture._GenFlags & TEXGEN_NEED_EYE_COORD)) {
-		BEGIN_RING(chan, kelvin, NV20TCL_MODELVIEW0_MATRIX(0), 16);
+		BEGIN_RING(chan, kelvin, NV20_3D_MODELVIEW_MATRIX(0, 0), 16);
 		OUT_RINGm(chan, m->m);
 	}
 
@@ -349,7 +349,7 @@ nv20_emit_modelview(struct gl_context *ctx, int emit)
 		int i, j;
 
 		BEGIN_RING(chan, kelvin,
-			   NV20TCL_INVERSE_MODELVIEW0_MATRIX(0), 12);
+			   NV20_3D_INVERSE_MODELVIEW_MATRIX(0, 0), 12);
 		for (i = 0; i < 3; i++)
 			for (j = 0; j < 4; j++)
 				OUT_RINGf(chan, m->inv[4*i + j]);
@@ -370,7 +370,7 @@ nv20_emit_projection(struct gl_context *ctx, int emit)
 	if (nctx->fallback == HWTNL)
 		_math_matrix_mul_matrix(&m, &m, &ctx->_ModelProjectMatrix);
 
-	BEGIN_RING(chan, kelvin, NV20TCL_PROJECTION_MATRIX(0), 16);
+	BEGIN_RING(chan, kelvin, NV20_3D_PROJECTION_MATRIX(0), 16);
 	OUT_RINGm(chan, m.m);
 
 	_math_matrix_dtr(&m);
diff --git a/src/mesa/drivers/dri/nouveau/nv_m2mf.xml.h b/src/mesa/drivers/dri/nouveau/nv_m2mf.xml.h
new file mode 100644
index 0000000000..e370a1ca06
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv_m2mf.xml.h
@@ -0,0 +1,155 @@
+#ifndef NV_M2MF_XML
+#define NV_M2MF_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv_m2mf.xml    (   2710 bytes, from 2010-11-01 00:28:46)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+
+#define NV04_M2MF_DMA_NOTIFY					0x00000180
+
+#define NV04_M2MF_DMA_BUFFER_IN					0x00000184
+
+#define NV04_M2MF_DMA_BUFFER_OUT				0x00000188
+
+
+#define NV50_M2MF_LINEAR_IN					0x00000200
+
+#define NV50_M2MF_TILING_MODE_IN				0x00000204
+
+#define NV50_M2MF_TILING_PITCH_IN				0x00000208
+
+#define NV50_M2MF_TILING_HEIGHT_IN				0x0000020c
+
+#define NV50_M2MF_TILING_DEPTH_IN				0x00000210
+
+#define NV50_M2MF_TILING_POSITION_IN_Z				0x00000214
+
+#define NV50_M2MF_TILING_POSITION_IN				0x00000218
+#define NV50_M2MF_TILING_POSITION_IN_X__MASK			0x0000ffff
+#define NV50_M2MF_TILING_POSITION_IN_X__SHIFT			0
+#define NV50_M2MF_TILING_POSITION_IN_Y__MASK			0xffff0000
+#define NV50_M2MF_TILING_POSITION_IN_Y__SHIFT			16
+
+#define NV50_M2MF_LINEAR_OUT					0x0000021c
+
+#define NV50_M2MF_TILING_MODE_OUT				0x00000220
+
+#define NV50_M2MF_TILING_PITCH_OUT				0x00000224
+
+#define NV50_M2MF_TILING_HEIGHT_OUT				0x00000228
+
+#define NV50_M2MF_TILING_DEPTH_OUT				0x0000022c
+
+#define NV50_M2MF_TILING_POSITION_OUT_Z				0x00000230
+
+#define NV50_M2MF_TILING_POSITION_OUT				0x00000234
+#define NV50_M2MF_TILING_POSITION_OUT_X__MASK			0x0000ffff
+#define NV50_M2MF_TILING_POSITION_OUT_X__SHIFT			0
+#define NV50_M2MF_TILING_POSITION_OUT_Y__MASK			0xffff0000
+#define NV50_M2MF_TILING_POSITION_OUT_Y__SHIFT			16
+
+#define NV50_M2MF_OFFSET_IN_HIGH				0x00000238
+
+#define NV50_M2MF_OFFSET_OUT_HIGH				0x0000023c
+
+#define NV04_M2MF_OFFSET_IN					0x0000030c
+
+#define NV04_M2MF_OFFSET_OUT					0x00000310
+
+#define NV04_M2MF_PITCH_IN					0x00000314
+
+#define NV04_M2MF_PITCH_OUT					0x00000318
+
+#define NV04_M2MF_LINE_LENGTH_IN				0x0000031c
+
+#define NV04_M2MF_LINE_COUNT					0x00000320
+
+#define NV04_M2MF_FORMAT					0x00000324
+#define NV04_M2MF_FORMAT_INPUT_INC__MASK			0x000000ff
+#define NV04_M2MF_FORMAT_INPUT_INC__SHIFT			0
+#define NV04_M2MF_FORMAT_INPUT_INC_1				0x00000001
+#define NV04_M2MF_FORMAT_INPUT_INC_2				0x00000002
+#define NV04_M2MF_FORMAT_INPUT_INC_4				0x00000004
+#define NV50_M2MF_FORMAT_INPUT_INC_8				0x00000008
+#define NV50_M2MF_FORMAT_INPUT_INC_16				0x00000010
+#define NV04_M2MF_FORMAT_OUTPUT_INC__MASK			0x0000ff00
+#define NV04_M2MF_FORMAT_OUTPUT_INC__SHIFT			8
+#define NV04_M2MF_FORMAT_OUTPUT_INC_1				0x00000100
+#define NV04_M2MF_FORMAT_OUTPUT_INC_2				0x00000200
+#define NV04_M2MF_FORMAT_OUTPUT_INC_4				0x00000400
+#define NV50_M2MF_FORMAT_OUTPUT_INC_8				0x00000800
+#define NV50_M2MF_FORMAT_OUTPUT_INC_16				0x00001000
+
+#define NV04_M2MF_BUF_NOTIFY					0x00000328
+
+
+#endif /* NV_M2MF_XML */
diff --git a/src/mesa/drivers/dri/nouveau/nv_object.xml.h b/src/mesa/drivers/dri/nouveau/nv_object.xml.h
new file mode 100644
index 0000000000..d5ed4bceb5
--- /dev/null
+++ b/src/mesa/drivers/dri/nouveau/nv_object.xml.h
@@ -0,0 +1,268 @@
+#ifndef NV_OBJECT_XML
+#define NV_OBJECT_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- nv_object.xml  (  11547 bytes, from 2010-11-13 23:32:57)
+- copyright.xml  (   6452 bytes, from 2010-11-15 15:10:58)
+- nvchipsets.xml (   3074 bytes, from 2010-11-13 23:32:57)
+- nv_defs.xml    (   4437 bytes, from 2010-11-01 00:28:46)
+
+Copyright (C) 2006-2010 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- imirkin <imirkin@users.sf.net> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define NV01_ROOT						0x00000001
+#define NV01_CONTEXT_DMA					0x00000002
+#define NV01_DEVICE						0x00000003
+#define NV01_TIMER						0x00000004
+#define NV01_NULL						0x00000030
+#define NV01_MEMORY_LOCAL_BANKED				0x0000003d
+#define NV01_MAPPING_SYSTEM					0x0000003e
+#define NV03_MEMORY_LOCAL_CURSOR				0x0000003f
+#define NV01_MEMORY_LOCAL_LINEAR				0x00000040
+#define NV01_MAPPING_LOCAL					0x00000041
+#define NV03_VIDEO_LUT_CURSOR_DAC				0x00000046
+#define NV03_CHANNEL_PIO					0x0000006a
+#define NV03_CHANNEL_DMA					0x0000006b
+#define NV10_VIDEO_DISPLAY					0x0000007c
+#define NV01_CONTEXT_BETA1					0x00000012
+#define NV04_BETA_SOLID						0x00000072
+#define NV01_CONTEXT_COLOR_KEY					0x00000017
+#define NV04_CONTEXT_COLOR_KEY					0x00000057
+#define NV01_CONTEXT_PATTERN					0x00000018
+#define NV01_CONTEXT_CLIP_RECTANGLE				0x00000019
+#define NV03_CONTEXT_ROP					0x00000043
+#define NV04_IMAGE_PATTERN					0x00000044
+#define NV01_RENDER_SOLID_LINE					0x0000001c
+#define NV04_RENDER_SOLID_LINE					0x0000005c
+#define NV30_RENDER_SOLID_LINE					0x0000035c
+#define NV40_RENDER_SOLID_LINE					0x0000305c
+#define NV01_RENDER_SOLID_TRIANGLE				0x0000001d
+#define NV04_RENDER_SOLID_TRIANGLE				0x0000005d
+#define NV01_RENDER_SOLID_RECTANGLE				0x0000001e
+#define NV04_RENDER_SOLID_RECTANGLE				0x0000005e
+#define NV01_IMAGE_BLIT						0x0000001f
+#define NV04_IMAGE_BLIT						0x0000005f
+#define NV11_IMAGE_BLIT						0x0000009f
+#define NV01_IMAGE_FROM_CPU					0x00000021
+#define NV04_IMAGE_FROM_CPU					0x00000061
+#define NV05_IMAGE_FROM_CPU					0x00000065
+#define NV10_IMAGE_FROM_CPU					0x0000008a
+#define NV30_IMAGE_FROM_CPU					0x0000038a
+#define NV40_IMAGE_FROM_CPU					0x0000308a
+#define NV03_STRETCHED_IMAGE_FROM_CPU				0x00000036
+#define NV04_STRETCHED_IMAGE_FROM_CPU				0x00000076
+#define NV05_STRETCHED_IMAGE_FROM_CPU				0x00000066
+#define NV30_STRETCHED_IMAGE_FROM_CPU				0x00000366
+#define NV40_STRETCHED_IMAGE_FROM_CPU				0x00003066
+#define NV03_SCALED_IMAGE_FROM_MEMORY				0x00000037
+#define NV04_SCALED_IMAGE_FROM_MEMORY				0x00000077
+#define NV05_SCALED_IMAGE_FROM_MEMORY				0x00000063
+#define NV10_SCALED_IMAGE_FROM_MEMORY				0x00000089
+#define NV30_SCALED_IMAGE_FROM_MEMORY				0x00000389
+#define NV40_SCALED_IMAGE_FROM_MEMORY				0x00003089
+#define NV50_SCALED_IMAGE_FROM_MEMORY				0x00005089
+#define NV04_DVD_SUBPICTURE					0x00000038
+#define NV10_DVD_SUBPICTURE					0x00000088
+#define NV03_GDI_RECTANGLE_TEXT					0x0000004b
+#define NV04_GDI_RECTANGLE_TEXT					0x0000004a
+#define NV04_SWIZZLED_SURFACE					0x00000052
+#define NV20_SWIZZLED_SURFACE					0x0000009e
+#define NV30_SWIZZLED_SURFACE					0x0000039e
+#define NV40_SWIZZLED_SURFACE					0x0000309e
+#define NV03_CONTEXT_SURFACE_DST				0x00000058
+#define NV03_CONTEXT_SURFACE_SRC				0x00000059
+#define NV04_CONTEXT_SURFACES_2D				0x00000042
+#define NV10_CONTEXT_SURFACES_2D				0x00000062
+#define NV30_CONTEXT_SURFACES_2D				0x00000362
+#define NV40_CONTEXT_SURFACES_2D				0x00003062
+#define NV50_CONTEXT_SURFACES_2D				0x00005062
+#define NV04_INDEXED_IMAGE_FROM_CPU				0x00000060
+#define NV05_INDEXED_IMAGE_FROM_CPU				0x00000064
+#define NV30_INDEXED_IMAGE_FROM_CPU				0x00000364
+#define NV40_INDEXED_IMAGE_FROM_CPU				0x00003064
+#define NV10_TEXTURE_FROM_CPU					0x0000007b
+#define NV30_TEXTURE_FROM_CPU					0x0000037b
+#define NV40_TEXTURE_FROM_CPU					0x0000307b
+#define NV04_M2MF						0x00000039
+#define NV50_M2MF						0x00005039
+#define NVC0_M2MF						0x00009039
+#define NV03_TEXTURED_TRIANGLE					0x00000048
+#define NV04_TEXTURED_TRIANGLE					0x00000054
+#define NV10_TEXTURED_TRIANGLE					0x00000094
+#define NV04_MULTITEX_TRIANGLE					0x00000055
+#define NV10_MULTITEX_TRIANGLE					0x00000095
+#define NV03_CONTEXT_SURFACE_COLOR				0x0000005a
+#define NV03_CONTEXT_SURFACE_ZETA				0x0000005b
+#define NV04_CONTEXT_SURFACES_3D				0x00000053
+#define NV10_CONTEXT_SURFACES_3D				0x00000093
+#define NV10_3D							0x00000056
+#define NV11_3D							0x00000096
+#define NV17_3D							0x00000099
+#define NV20_3D							0x00000097
+#define NV25_3D							0x00000597
+#define NV30_3D							0x00000397
+#define NV35_3D							0x00000497
+#define NV34_3D							0x00000697
+#define NV40_3D							0x00004097
+#define NV44_3D							0x00004497
+#define NV50_3D							0x00005097
+#define NV84_3D							0x00008297
+#define NVA0_3D							0x00008397
+#define NVA3_3D							0x00008597
+#define NVAF_3D							0x00008697
+#define NVC0_3D							0x00009097
+#define NV50_2D							0x0000502d
+#define NVC0_2D							0x0000902d
+#define NV50_COMPUTE						0x000050c0
+#define NVA3_COMPUTE						0x000085c0
+#define NVC0_COMPUTE						0x000090c0
+#define NV84_CRYPT						0x000074c1
+#define NV01_SUBCHAN__SIZE					0x00002000
+#define NV01_SUBCHAN						0x00000000
+
+#define NV01_SUBCHAN_OBJECT					0x00000000
+
+
+#define NV84_SUBCHAN_QUERY_ADDRESS_HIGH				0x00000010
+
+#define NV84_SUBCHAN_QUERY_ADDRESS_LOW				0x00000014
+
+#define NV84_SUBCHAN_QUERY_COUNTER				0x00000018
+
+#define NV84_SUBCHAN_QUERY_GET					0x0000001c
+
+#define NV84_SUBCHAN_QUERY_INTR					0x00000020
+
+#define NV84_SUBCHAN_WRCACHE_FLUSH				0x00000024
+
+#define NV10_SUBCHAN_REF_CNT					0x00000050
+
+
+#define NV11_SUBCHAN_DMA_SEMAPHORE				0x00000060
+
+#define NV11_SUBCHAN_SEMAPHORE_OFFSET				0x00000064
+
+#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE				0x00000068
+
+#define NV11_SUBCHAN_SEMAPHORE_RELEASE				0x0000006c
+
+#define NV40_SUBCHAN_YIELD					0x00000080
+
+#define NV01_GRAPH						0x00000000
+
+#define NV04_GRAPH_NOP						0x00000100
+
+#define NV01_GRAPH_NOTIFY					0x00000104
+#define NV01_GRAPH_NOTIFY_WRITE					0x00000000
+#define NV01_GRAPH_NOTIFY_WRITE_AND_AWAKEN			0x00000001
+
+#define NV50_GRAPH_WAIT_FOR_IDLE				0x00000110
+
+#define NVA3_GRAPH_UNK0120					0x00000120
+
+#define NVA3_GRAPH_UNK0124					0x00000124
+
+#define NV40_GRAPH_PM_TRIGGER					0x00000140
+
+#define NVC0_SUBCHAN__SIZE					0x00008000
+#define NVC0_SUBCHAN						0x00000000
+
+#define NVC0_SUBCHAN_OBJECT					0x00000000
+
+
+#define NVC0_SUBCHAN_QUERY_ADDRESS_HIGH				0x00000010
+
+#define NVC0_SUBCHAN_QUERY_ADDRESS_LOW				0x00000014
+
+#define NVC0_SUBCHAN_QUERY_SEQUENCE				0x00000018
+
+#define NVC0_SUBCHAN_QUERY_GET					0x0000001c
+
+#define NVC0_SUBCHAN_REF_CNT					0x00000050
+
+#define NVC0_GRAPH						0x00000000
+
+#define NVC0_GRAPH_NOP						0x00000100
+
+#define NVC0_GRAPH_NOTIFY_ADDRESS_HIGH				0x00000104
+
+#define NVC0_GRAPH_NOTIFY_ADDRESS_LOW				0x00000108
+
+#define NVC0_GRAPH_NOTIFY					0x0000010c
+#define NVC0_GRAPH_NOTIFY_WRITE					0x00000000
+#define NVC0_GRAPH_NOTIFY_WRITE_AND_AWAKEN			0x00000001
+
+#define NVC0_GRAPH_SERIALIZE					0x00000110
+
+#define NVC0_GRAPH_MACRO_UPLOAD_POS				0x00000114
+
+#define NVC0_GRAPH_MACRO_UPLOAD_DATA				0x00000118
+
+#define NVC0_GRAPH_MACRO_ID					0x0000011c
+
+#define NVC0_GRAPH_MACRO_POS					0x00000120
+
+
+#endif /* NV_OBJECT_XML */
diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
index 8a047e6419..b62290231b 100644
--- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c
+++ b/src/mesa/drivers/dri/r200/r200_maos_arrays.c
@@ -200,6 +200,7 @@ void r200EmitArrays( struct gl_context *ctx, GLubyte *vimap_rev )
 	    }
 	 default:
 	    assert(0);
+	    emitsize = 0;
 	 }
 	 if (!rmesa->radeon.tcl.aos[nr].bo) {
 	   rcommon_emit_vector( ctx,
diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c
index 690bec640b..24fb031ecb 100644
--- a/src/mesa/drivers/dri/r200/r200_texstate.c
+++ b/src/mesa/drivers/dri/r200/r200_texstate.c
@@ -778,6 +778,7 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 	uint32_t internalFormat, type, format;
+	gl_format texFormat;
 
 	type = GL_BGRA;
 	format = GL_UNSIGNED_BYTE;
@@ -817,10 +818,6 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	radeon_miptree_unreference(&t->mt);
 	radeon_miptree_unreference(&rImage->mt);
 
-	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
-				   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
-	texImage->RowStride = rb->pitch / rb->cpp;
-
 	rImage->bo = rb->bo;
 	radeon_bo_ref(rImage->bo);
 	t->bo = rb->bo;
@@ -832,22 +829,35 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	pitch_val = rb->pitch;
 	switch (rb->cpp) {
 	case 4:
-		if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
+		if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
+			texFormat = MESA_FORMAT_RGB888;
 			t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format;
-		else
+		}
+		else {
+			texFormat = MESA_FORMAT_ARGB8888;
 			t->pp_txformat = tx_table_le[MESA_FORMAT_ARGB8888].format;
+		}
 		t->pp_txfilter |= tx_table_le[MESA_FORMAT_ARGB8888].filter;
 		break;
 	case 3:
 	default:
+		texFormat = MESA_FORMAT_RGB888;
 		t->pp_txformat = tx_table_le[MESA_FORMAT_RGB888].format;
 		t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB888].filter;
 		break;
 	case 2:
+		texFormat = MESA_FORMAT_RGB565;
 		t->pp_txformat = tx_table_le[MESA_FORMAT_RGB565].format;
 		t->pp_txfilter |= tx_table_le[MESA_FORMAT_RGB565].filter;
 		break;
 	}
+
+	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+				   rb->base.Width, rb->base.Height, 1, 0,
+				   rb->cpp, texFormat);
+	texImage->RowStride = rb->pitch / rb->cpp;
+
+
         t->pp_txsize = ((rb->base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
 		   | ((rb->base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
         t->pp_txformat |= R200_TXFORMAT_NON_POWER2;
diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
index 8be32ea91f..1db8678e89 100644
--- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_emit.c
@@ -76,6 +76,9 @@ static void use_temporary(struct r300_fragment_program_code *code, unsigned int
 
 static unsigned int use_source(struct r300_fragment_program_code* code, struct rc_pair_instruction_source src)
 {
+	if (!src.Used)
+		return 0;
+
 	if (src.File == RC_FILE_CONSTANT) {
 		return src.Index | (1 << 5);
 	} else if (src.File == RC_FILE_TEMPORARY) {
diff --git a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c
index 2d28b06539..05d3da8a10 100644
--- a/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c
+++ b/src/mesa/drivers/dri/r300/compiler/r300_fragprog_swizzle.c
@@ -94,6 +94,7 @@ static const struct swizzle_data* lookup_native_swizzle(unsigned int swizzle)
  */
 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
 {
+	const struct swizzle_data* sd;
 	unsigned int relevant;
 	int j;
 
@@ -127,7 +128,8 @@ static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg)
 	if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
 		return 0;
 
-	if (!lookup_native_swizzle(reg.Swizzle))
+	sd = lookup_native_swizzle(reg.Swizzle);
+	if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
 		return 0;
 
 	return 1;
@@ -201,7 +203,7 @@ unsigned int r300FPTranslateRGBSwizzle(unsigned int src, unsigned int swizzle)
 {
 	const struct swizzle_data* sd = lookup_native_swizzle(swizzle);
 
-	if (!sd) {
+	if (!sd || (src == RC_PAIR_PRESUB_SRC && sd->srcp_stride == 0)) {
 		fprintf(stderr, "Not a native swizzle: %08x\n", swizzle);
 		return 0;
 	}
diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c
index 2f130198d3..e0d349b98c 100644
--- a/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c
@@ -24,6 +24,7 @@
 
 #include <stdio.h>
 
+#include "radeon_compiler_util.h"
 #include "radeon_dataflow.h"
 #include "radeon_emulate_branches.h"
 #include "radeon_emulate_loops.h"
@@ -54,6 +55,8 @@ static void rc_rewrite_depth_out(struct radeon_compiler *cc, void *user)
 
 	for (rci = c->Base.Program.Instructions.Next; rci != &c->Base.Program.Instructions; rci = rci->Next) {
 		struct rc_sub_instruction * inst = &rci->U.I;
+		unsigned i;
+		const struct rc_opcode_info *info = rc_get_opcode_info(inst->Opcode);
 
 		if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
 			continue;
@@ -65,27 +68,12 @@ static void rc_rewrite_depth_out(struct radeon_compiler *cc, void *user)
 			continue;
 		}
 
-		switch (inst->Opcode) {
-			case RC_OPCODE_FRC:
-			case RC_OPCODE_MOV:
-				inst->SrcReg[0] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[0]);
-				break;
-			case RC_OPCODE_ADD:
-			case RC_OPCODE_MAX:
-			case RC_OPCODE_MIN:
-			case RC_OPCODE_MUL:
-				inst->SrcReg[0] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[0]);
-				inst->SrcReg[1] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[1]);
-				break;
-			case RC_OPCODE_CMP:
-			case RC_OPCODE_MAD:
-				inst->SrcReg[0] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[0]);
-				inst->SrcReg[1] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[1]);
-				inst->SrcReg[2] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[2]);
-				break;
-			default:
-				// Scalar instructions needn't be reswizzled
-				break;
+		if (!info->IsComponentwise) {
+			continue;
+		}
+
+		for (i = 0; i < info->NumSrcRegs; i++) {
+			inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
 		}
 	}
 }
@@ -93,7 +81,6 @@ static void rc_rewrite_depth_out(struct radeon_compiler *cc, void *user)
 void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
 {
 	int is_r500 = c->Base.is_r500;
-	int kill_consts = c->Base.remove_unused_constants;
 	int opt = !c->Base.disable_optimizations;
 
 	/* Lists of instruction transformations. */
@@ -133,11 +120,11 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
 		{"emulate loops",		1, !is_r500,	rc_emulate_loops,		NULL},
 		{"dataflow optimize",		1, opt,		rc_optimize,			NULL},
 		{"dataflow swizzles",		1, 1,		rc_dataflow_swizzles,		NULL},
-		{"dead constants",		1, kill_consts, rc_remove_unused_constants,	&c->code->constants_remap_table},
+		{"dead constants",		1, 1,		rc_remove_unused_constants,	&c->code->constants_remap_table},
 		/* This pass makes it easier for the scheduler to group TEX
 		 * instructions and reduces the chances of creating too
 		 * many texture indirections.*/
-		{"register rename",		1, !is_r500,	rc_rename_regs,			NULL},
+		{"register rename",		1, !is_r500 || opt, rc_rename_regs,		NULL},
 		{"pair translate",		1, 1,		rc_pair_translate,		NULL},
 		{"pair scheduling",		1, 1,		rc_pair_schedule,		NULL},
 		{"register allocation",		1, opt,		rc_pair_regalloc,		NULL},
@@ -150,9 +137,10 @@ void r3xx_compile_fragment_program(struct r300_fragment_program_compiler* c)
 		{NULL, 0, 0, NULL, NULL}
 	};
 
+	c->Base.type = RC_FRAGMENT_PROGRAM;
 	c->Base.SwizzleCaps = c->Base.is_r500 ? &r500_swizzle_caps : &r300_swizzle_caps;
 
-	rc_run_compiler(&c->Base, fs_list, "Fragment Program");
+	rc_run_compiler(&c->Base, fs_list);
 
 	rc_constants_copy(&c->code->constants, &c->Base.Program.Constants);
 }
diff --git a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
index bf8341f017..472029f63d 100644
--- a/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
@@ -26,6 +26,7 @@
 
 #include "../r300_reg.h"
 
+#include "radeon_compiler_util.h"
 #include "radeon_dataflow.h"
 #include "radeon_program_alu.h"
 #include "radeon_swizzle.h"
@@ -790,19 +791,14 @@ static void allocate_temporary_registers(struct radeon_compiler *c, void *user)
 						if (!hwtemps[j])
 							break;
 					}
-					if (j >= c->max_temp_regs) {
-						rc_error(c, "Too many temporaries\n");
-						return;
+					ta[orig].Allocated = 1;
+					if (last_inst_src_reladdr &&
+					    last_inst_src_reladdr->IP > inst->IP) {
+						ta[orig].HwTemp = orig;
 					} else {
-						ta[orig].Allocated = 1;
-						if (last_inst_src_reladdr &&
-						    last_inst_src_reladdr->IP > inst->IP) {
-							ta[orig].HwTemp = orig;
-						} else {
-							ta[orig].HwTemp = j;
-						}
-						hwtemps[ta[orig].HwTemp] = 1;
+						ta[orig].HwTemp = j;
 					}
+					hwtemps[ta[orig].HwTemp] = 1;
 				}
 
 				inst->U.I.DstReg.Index = ta[orig].HwTemp;
@@ -1018,7 +1014,6 @@ static struct rc_swizzle_caps r300_vertprog_swizzle_caps = {
 void r3xx_compile_vertex_program(struct r300_vertex_program_compiler *c)
 {
 	int is_r500 = c->Base.is_r500;
-	int kill_consts = c->Base.remove_unused_constants;
 	int opt = !c->Base.disable_optimizations;
 
 	/* Lists of instruction transformations. */
@@ -1062,18 +1057,18 @@ void r3xx_compile_vertex_program(struct r300_vertex_program_compiler *c)
 		{"dataflow optimize",		1, opt,		rc_optimize,			NULL},
 		/* This pass must be done after optimizations. */
 		{"source conflict resolve",	1, 1,		rc_local_transform,		resolve_src_conflicts},
-		{"dataflow swizzles",		1, 1,		rc_dataflow_swizzles,		NULL},
 		{"register allocation",		1, opt,		allocate_temporary_registers,	NULL},
-		{"dead constants",		1, kill_consts, rc_remove_unused_constants,	&c->code->constants_remap_table},
+		{"dead constants",		1, 1,		rc_remove_unused_constants,	&c->code->constants_remap_table},
 		{"final code validation",	0, 1,		rc_validate_final_shader,	NULL},
 		{"machine code generation",	0, 1,		translate_vertex_program,	NULL},
 		{"dump machine code",		0, c->Base.Debug & RC_DBG_LOG, r300_vertex_program_dump,	NULL},
 		{NULL, 0, 0, NULL, NULL}
 	};
 
+	c->Base.type = RC_VERTEX_PROGRAM;
 	c->Base.SwizzleCaps = &r300_vertprog_swizzle_caps;
 
-	rc_run_compiler(&c->Base, vs_list, "Vertex Program");
+	rc_run_compiler(&c->Base, vs_list);
 
 	c->code->InputsRead = c->Base.Program.InputsRead;
 	c->code->OutputsWritten = c->Base.Program.OutputsWritten;
diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
index 289bb87ae5..ef81be48f7 100644
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
@@ -29,6 +29,7 @@
 
 #include <stdio.h>
 
+#include "radeon_compiler_util.h"
 #include "../r300_reg.h"
 
 /**
diff --git a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
index 6f101c68eb..5da82d90f6 100644
--- a/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
+++ b/src/mesa/drivers/dri/r300/compiler/r500_fragprog_emit.c
@@ -45,9 +45,6 @@
 
 #include "radeon_program_pair.h"
 
-#define MAX_BRANCH_DEPTH_FULL 32
-#define MAX_BRANCH_DEPTH_PARTIAL 4
-
 #define PROG_CODE \
 	struct r500_fragment_program_code *code = &c->code->code.r500
 
@@ -200,6 +197,9 @@ static void use_temporary(struct r500_fragment_program_code* code, unsigned int
 
 static unsigned int use_source(struct r500_fragment_program_code* code, struct rc_pair_instruction_source src)
 {
+	if (!src.Used)
+		return 0;
+
 	if (src.File == RC_FILE_CONSTANT) {
 		return src.Index | 0x100;
 	} else if (src.File == RC_FILE_TEMPORARY) {
@@ -506,7 +506,7 @@ static void emit_flowcontrol(struct emit_state * s, struct rc_instruction * inst
 		break;
 	}
 	case RC_OPCODE_IF:
-		if ( s->CurrentBranchDepth >= MAX_BRANCH_DEPTH_FULL) {
+		if ( s->CurrentBranchDepth >= R500_PFS_MAX_BRANCH_DEPTH_FULL) {
 			rc_error(s->C, "Branch depth exceeds hardware limit");
 			return;
 		}
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_code.h b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
index cfb6df2cd7..b69e81698a 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_code.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_code.h
@@ -34,6 +34,8 @@
 #define R500_PFS_MAX_INST         512
 #define R500_PFS_NUM_TEMP_REGS    128
 #define R500_PFS_NUM_CONST_REGS   256
+#define R500_PFS_MAX_BRANCH_DEPTH_FULL 32
+#define R500_PFS_MAX_BRANCH_DEPTH_PARTIAL 4
 
 
 #define STATE_R300_WINDOW_DIMENSION (STATE_INTERNAL_DRIVER+0)
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
index 4286baed0c..65548604bc 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
@@ -29,6 +29,7 @@
 #include "radeon_dataflow.h"
 #include "radeon_program.h"
 #include "radeon_program_pair.h"
+#include "radeon_compiler_util.h"
 
 
 void rc_init(struct radeon_compiler * c)
@@ -356,66 +357,92 @@ void rc_transform_fragment_face(struct radeon_compiler *c, unsigned face)
 static void reg_count_callback(void * userdata, struct rc_instruction * inst,
 		rc_register_file file, unsigned int index, unsigned int mask)
 {
-	unsigned int * max_reg = userdata;
+	int *max_reg = userdata;
 	if (file == RC_FILE_TEMPORARY)
-		index > *max_reg ? *max_reg = index : 0;
+		(int)index > *max_reg ? *max_reg = index : 0;
 }
 
-static void print_stats(struct radeon_compiler * c)
+void rc_get_stats(struct radeon_compiler *c, struct rc_program_stats *s)
 {
+	int max_reg = -1;
 	struct rc_instruction * tmp;
-	unsigned max_reg, insts, fc, tex, alpha, rgb, presub;
-	max_reg = insts = fc = tex = alpha = rgb = presub = 0;
+	memset(s, 0, sizeof(*s));
+
 	for(tmp = c->Program.Instructions.Next; tmp != &c->Program.Instructions;
 							tmp = tmp->Next){
 		const struct rc_opcode_info * info;
 		rc_for_all_reads_mask(tmp, reg_count_callback, &max_reg);
 		if (tmp->Type == RC_INSTRUCTION_NORMAL) {
 			if (tmp->U.I.PreSub.Opcode != RC_PRESUB_NONE)
-				presub++;
+				s->num_presub_ops++;
 			info = rc_get_opcode_info(tmp->U.I.Opcode);
 		} else {
 			if (tmp->U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Used)
-				presub++;
+				s->num_presub_ops++;
 			if (tmp->U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Used)
-				presub++;
+				s->num_presub_ops++;
 			/* Assuming alpha will never be a flow control or
 			 * a tex instruction. */
 			if (tmp->U.P.Alpha.Opcode != RC_OPCODE_NOP)
-				alpha++;
+				s->num_alpha_insts++;
 			if (tmp->U.P.RGB.Opcode != RC_OPCODE_NOP)
-				rgb++;
+				s->num_rgb_insts++;
 			info = rc_get_opcode_info(tmp->U.P.RGB.Opcode);
 		}
 		if (info->IsFlowControl)
-			fc++;
+			s->num_fc_insts++;
 		if (info->HasTexture)
-			tex++;
-		insts++;
+			s->num_tex_insts++;
+		s->num_insts++;
 	}
-	if (insts < 4)
-		return;
-	fprintf(stderr,"~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n"
-		       "~%4u Instructions\n"
-		       "~%4u Vector Instructions (RGB)\n"
-		       "~%4u Scalar Instructions (Alpha)\n"
-		       "~%4u Flow Control Instructions\n"
-		       "~%4u Texture Instructions\n"
-		       "~%4u Presub Operations\n"
-		       "~%4u Temporary Registers\n"
-		       "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n",
-		       insts, rgb, alpha, fc, tex, presub, max_reg + 1);
+	s->num_temp_regs = max_reg + 1;
 }
 
-/* Executes a list of compiler passes given in the parameter 'list'. */
-void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list,
-		     const char *shader_name)
+static void print_stats(struct radeon_compiler * c)
 {
-	if (c->Debug & RC_DBG_LOG) {
-		fprintf(stderr, "%s: before compilation\n", shader_name);
-		rc_print_program(&c->Program);
+	struct rc_program_stats s;
+
+	rc_get_stats(c, &s);
+
+	if (s.num_insts < 4)
+		return;
+
+	switch (c->type) {
+	case RC_VERTEX_PROGRAM:
+		fprintf(stderr,"~~~~~~~~~ VERTEX PROGRAM ~~~~~~~~\n"
+			       "~%4u Instructions\n"
+			       "~%4u Flow Control Instructions\n"
+			       "~%4u Temporary Registers\n"
+			       "~~~~~~~~~~~~~~ END ~~~~~~~~~~~~~~\n",
+			       s.num_insts, s.num_fc_insts, s.num_temp_regs);
+		break;
+
+	case RC_FRAGMENT_PROGRAM:
+		fprintf(stderr,"~~~~~~~~ FRAGMENT PROGRAM ~~~~~~~\n"
+			       "~%4u Instructions\n"
+			       "~%4u Vector Instructions (RGB)\n"
+			       "~%4u Scalar Instructions (Alpha)\n"
+			       "~%4u Flow Control Instructions\n"
+			       "~%4u Texture Instructions\n"
+			       "~%4u Presub Operations\n"
+			       "~%4u Temporary Registers\n"
+			       "~~~~~~~~~~~~~~ END ~~~~~~~~~~~~~~\n",
+			       s.num_insts, s.num_rgb_insts, s.num_alpha_insts,
+			       s.num_fc_insts, s.num_tex_insts, s.num_presub_ops,
+			       s.num_temp_regs);
+		break;
+	default:
+		assert(0);
 	}
+}
 
+static const char *shader_name[RC_NUM_PROGRAM_TYPES] = {
+	"Vertex Program",
+	"Fragment Program"
+};
+
+void rc_run_compiler_passes(struct radeon_compiler *c, struct radeon_compiler_pass *list)
+{
 	for (unsigned i = 0; list[i].name; i++) {
 		if (list[i].predicate) {
 			list[i].run(c, list[i].user);
@@ -424,11 +451,23 @@ void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *lis
 				return;
 
 			if ((c->Debug & RC_DBG_LOG) && list[i].dump) {
-				fprintf(stderr, "%s: after '%s'\n", shader_name, list[i].name);
+				fprintf(stderr, "%s: after '%s'\n", shader_name[c->type], list[i].name);
 				rc_print_program(&c->Program);
 			}
 		}
 	}
+}
+
+/* Executes a list of compiler passes given in the parameter 'list'. */
+void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list)
+{
+	if (c->Debug & RC_DBG_LOG) {
+		fprintf(stderr, "%s: before compilation\n", shader_name[c->type]);
+		rc_print_program(&c->Program);
+	}
+
+	rc_run_compiler_passes(c, list);
+
 	if (c->Debug & RC_DBG_STATS)
 		print_stats(c);
 }
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h
index 31fd469a04..e663339589 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler.h
@@ -35,9 +35,16 @@
 
 struct rc_swizzle_caps;
 
+enum rc_program_type {
+	RC_VERTEX_PROGRAM,
+	RC_FRAGMENT_PROGRAM,
+	RC_NUM_PROGRAM_TYPES
+};
+
 struct radeon_compiler {
 	struct memory_pool Pool;
 	struct rc_program Program;
+	enum rc_program_type type;
 	unsigned Debug:2;
 	unsigned Error:1;
 	char * ErrorMsg;
@@ -140,9 +147,21 @@ struct radeon_compiler_pass {
 	void *user;		/* Optional parameter which is passed to the run function. */
 };
 
+struct rc_program_stats {
+	unsigned num_insts;
+	unsigned num_fc_insts;
+	unsigned num_tex_insts;
+	unsigned num_rgb_insts;
+	unsigned num_alpha_insts;
+	unsigned num_presub_ops;
+	unsigned num_temp_regs;
+};
+
+void rc_get_stats(struct radeon_compiler *c, struct rc_program_stats *s);
+
 /* Executes a list of compiler passes given in the parameter 'list'. */
-void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list,
-		     const char *shader_name);
+void rc_run_compiler_passes(struct radeon_compiler *c, struct radeon_compiler_pass *list);
+void rc_run_compiler(struct radeon_compiler *c, struct radeon_compiler_pass *list);
 void rc_validate_final_shader(struct radeon_compiler *c, void *user);
 
 #endif /* RADEON_COMPILER_H */
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c
index 97f4c75849..bf393a9fb1 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.c
@@ -31,6 +31,8 @@
 
 #include "radeon_compiler_util.h"
 
+#include "radeon_compiler.h"
+#include "radeon_dataflow.h"
 /**
  */
 unsigned int rc_swizzle_to_writemask(unsigned int swz)
@@ -46,6 +48,91 @@ unsigned int rc_swizzle_to_writemask(unsigned int swz)
 	return mask;
 }
 
+rc_swizzle get_swz(unsigned int swz, rc_swizzle idx)
+{
+	if (idx & 0x4)
+		return idx;
+	return GET_SWZ(swz, idx);
+}
+
+unsigned int combine_swizzles4(unsigned int src,
+		rc_swizzle swz_x, rc_swizzle swz_y, rc_swizzle swz_z, rc_swizzle swz_w)
+{
+	unsigned int ret = 0;
+
+	ret |= get_swz(src, swz_x);
+	ret |= get_swz(src, swz_y) << 3;
+	ret |= get_swz(src, swz_z) << 6;
+	ret |= get_swz(src, swz_w) << 9;
+
+	return ret;
+}
+
+unsigned int combine_swizzles(unsigned int src, unsigned int swz)
+{
+	unsigned int ret = 0;
+
+	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_X));
+	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_Y)) << 3;
+	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_Z)) << 6;
+	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_W)) << 9;
+
+	return ret;
+}
+
+/**
+ * @param mask Must be either RC_MASK_X, RC_MASK_Y, RC_MASK_Z, or RC_MASK_W
+ */
+rc_swizzle rc_mask_to_swizzle(unsigned int mask)
+{
+	switch (mask) {
+	case RC_MASK_X: return RC_SWIZZLE_X;
+	case RC_MASK_Y: return RC_SWIZZLE_Y;
+	case RC_MASK_Z: return RC_SWIZZLE_Z;
+	case RC_MASK_W: return RC_SWIZZLE_W;
+	}
+	return RC_SWIZZLE_UNUSED;
+}
+
+/* Reorder mask bits according to swizzle. */
+unsigned swizzle_mask(unsigned swizzle, unsigned mask)
+{
+	unsigned ret = 0;
+	for (unsigned chan = 0; chan < 4; ++chan) {
+		unsigned swz = GET_SWZ(swizzle, chan);
+		if (swz < 4)
+			ret |= GET_BIT(mask, swz) << chan;
+	}
+	return ret;
+}
+
+/**
+ * Left multiplication of a register with a swizzle
+ */
+struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg)
+{
+	struct rc_src_register tmp = srcreg;
+	int i;
+	tmp.Swizzle = 0;
+	tmp.Negate = 0;
+	for(i = 0; i < 4; ++i) {
+		rc_swizzle swz = GET_SWZ(swizzle, i);
+		if (swz < 4) {
+			tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3);
+			tmp.Negate |= GET_BIT(srcreg.Negate, swz) << i;
+		} else {
+			tmp.Swizzle |= swz << (i*3);
+		}
+	}
+	return tmp;
+}
+
+void reset_srcreg(struct rc_src_register* reg)
+{
+	memset(reg, 0, sizeof(struct rc_src_register));
+	reg->Swizzle = RC_SWIZZLE_XYZW;
+}
+
 unsigned int rc_src_reads_dst_mask(
 		rc_register_file src_file,
 		unsigned int src_idx,
@@ -59,3 +146,123 @@ unsigned int rc_src_reads_dst_mask(
 	}
 	return dst_mask & rc_swizzle_to_writemask(src_swz);
 }
+
+unsigned int rc_source_type_swz(unsigned int swizzle, unsigned int channels)
+{
+	unsigned int chan;
+	unsigned int swz = RC_SWIZZLE_UNUSED;
+	unsigned int ret = RC_SOURCE_NONE;
+
+	for(chan = 0; chan < channels; chan++) {
+		swz = GET_SWZ(swizzle, chan);
+		if (swz == RC_SWIZZLE_W) {
+			ret |= RC_SOURCE_ALPHA;
+		} else if (swz == RC_SWIZZLE_X || swz == RC_SWIZZLE_Y
+						|| swz == RC_SWIZZLE_Z) {
+			ret |= RC_SOURCE_RGB;
+		}
+	}
+	return ret;
+}
+
+unsigned int rc_source_type_mask(unsigned int mask)
+{
+	unsigned int ret = RC_SOURCE_NONE;
+
+	if (mask & RC_MASK_XYZ)
+		ret |= RC_SOURCE_RGB;
+
+	if (mask & RC_MASK_W)
+		ret |= RC_SOURCE_ALPHA;
+
+	return ret;
+}
+
+struct can_use_presub_data {
+	struct rc_src_register RemoveSrcs[3];
+	unsigned int RGBCount;
+	unsigned int AlphaCount;
+};
+
+static void can_use_presub_read_cb(
+	void * userdata,
+	struct rc_instruction * inst,
+	rc_register_file file,
+	unsigned int index,
+	unsigned int mask)
+{
+	struct can_use_presub_data * d = userdata;
+	unsigned int src_type = rc_source_type_mask(mask);
+	unsigned int i;
+
+	if (file == RC_FILE_NONE)
+		return;
+
+	for(i = 0; i < 3; i++) {
+		if (d->RemoveSrcs[i].File == file
+		    && d->RemoveSrcs[i].Index == index) {
+			src_type &=
+				~rc_source_type_swz(d->RemoveSrcs[i].Swizzle, 4);
+		}
+	}
+
+	if (src_type & RC_SOURCE_RGB)
+		d->RGBCount++;
+
+	if (src_type & RC_SOURCE_ALPHA)
+		d->AlphaCount++;
+}
+
+unsigned int rc_inst_can_use_presub(
+	struct rc_instruction * inst,
+	rc_presubtract_op presub_op,
+	unsigned int presub_writemask,
+	struct rc_src_register replace_reg,
+	struct rc_src_register presub_src0,
+	struct rc_src_register presub_src1)
+{
+	struct can_use_presub_data d;
+	unsigned int num_presub_srcs;
+	unsigned int presub_src_type = rc_source_type_mask(presub_writemask);
+	const struct rc_opcode_info * info =
+					rc_get_opcode_info(inst->U.I.Opcode);
+
+	if (presub_op == RC_PRESUB_NONE) {
+		return 1;
+	}
+
+	if (info->HasTexture) {
+		return 0;
+	}
+
+	/* We can't use more than one presubtract value in an
+	 * instruction, unless the two prsubtract operations
+	 * are the same and read from the same registers.
+	 * XXX For now we will limit instructions to only one presubtract
+	 * value.*/
+	if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) {
+		return 0;
+	}
+
+	memset(&d, 0, sizeof(d));
+	d.RemoveSrcs[0] = replace_reg;
+	d.RemoveSrcs[1] = presub_src0;
+	d.RemoveSrcs[2] = presub_src1;
+
+	rc_for_all_reads_mask(inst, can_use_presub_read_cb, &d);
+
+	num_presub_srcs = rc_presubtract_src_reg_count(presub_op);
+
+	if ((presub_src_type & RC_SOURCE_RGB)
+					&& d.RGBCount + num_presub_srcs > 3) {
+		return 0;
+	}
+
+	if ((presub_src_type & RC_SOURCE_ALPHA)
+					&& d.AlphaCount + num_presub_srcs > 3) {
+		return 0;
+	}
+
+	return 1;
+}
+
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h
index 1a14e7cb0e..461ab9ffb1 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_compiler_util.h
@@ -3,8 +3,27 @@
 #ifndef RADEON_PROGRAM_UTIL_H
 #define RADEON_PROGRAM_UTIL_H
 
+struct rc_instruction;
+struct rc_src_register;
+
 unsigned int rc_swizzle_to_writemask(unsigned int swz);
 
+rc_swizzle get_swz(unsigned int swz, rc_swizzle idx);
+
+unsigned int combine_swizzles4(unsigned int src,
+			       rc_swizzle swz_x, rc_swizzle swz_y,
+			       rc_swizzle swz_z, rc_swizzle swz_w);
+
+unsigned int combine_swizzles(unsigned int src, unsigned int swz);
+
+rc_swizzle rc_mask_to_swizzle(unsigned int mask);
+
+unsigned swizzle_mask(unsigned swizzle, unsigned mask);
+
+struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg);
+
+void reset_srcreg(struct rc_src_register* reg);
+
 unsigned int rc_src_reads_dst_mask(
 		rc_register_file src_file,
 		unsigned int src_idx,
@@ -13,4 +32,16 @@ unsigned int rc_src_reads_dst_mask(
 		unsigned int dst_idx,
 		unsigned int dst_mask);
 
+unsigned int rc_source_type_swz(unsigned int swizzle, unsigned int channels);
+
+unsigned int rc_source_type_mask(unsigned int mask);
+
+unsigned int rc_inst_can_use_presub(
+	struct rc_instruction * inst,
+	rc_presubtract_op presub_op,
+	unsigned int presub_writemask,
+	struct rc_src_register replace_reg,
+	struct rc_src_register presub_src0,
+	struct rc_src_register presub_src1);
+
 #endif /* RADEON_PROGRAM_UTIL_H */
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
index fd94194dc3..d0a64d936e 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
@@ -139,7 +139,46 @@ static void pair_sub_for_all_args(
 	const struct rc_opcode_info * info = rc_get_opcode_info(sub->Opcode);
 
 	for(i = 0; i < info->NumSrcRegs; i++) {
-		cb(userdata, fullinst, &sub->Arg[i]);
+		unsigned int src_type;
+		unsigned int channels = 0;
+		if (&fullinst->U.P.RGB == sub)
+			channels = 3;
+		else if (&fullinst->U.P.Alpha == sub)
+			channels = 1;
+
+		assert(channels > 0);
+		src_type = rc_source_type_swz(sub->Arg[i].Swizzle, channels);
+
+		if (src_type == RC_SOURCE_NONE)
+			continue;
+
+		if (sub->Arg[i].Source == RC_PAIR_PRESUB_SRC) {
+			unsigned int presub_type;
+			unsigned int presub_src_count;
+			struct rc_pair_instruction_source * src_array;
+			unsigned int j;
+			if (src_type & RC_SOURCE_RGB) {
+				presub_type = fullinst->
+					U.P.RGB.Src[RC_PAIR_PRESUB_SRC].Index;
+				src_array = fullinst->U.P.RGB.Src;
+			} else {
+				presub_type = fullinst->
+					U.P.Alpha.Src[RC_PAIR_PRESUB_SRC].Index;
+				src_array = fullinst->U.P.Alpha.Src;
+			}
+			presub_src_count
+				= rc_presubtract_src_reg_count(presub_type);
+			for(j = 0; j < presub_src_count; j++) {
+				cb(userdata, fullinst, &sub->Arg[i],
+								&src_array[j]);
+			}
+		} else {
+			struct rc_pair_instruction_source * src =
+				rc_pair_get_src(&fullinst->U.P, &sub->Arg[i]);
+			if (src) {
+				cb(userdata, fullinst, &sub->Arg[i], src);
+			}
+		}
 	}
 }
 
@@ -308,6 +347,7 @@ static void remap_normal_instruction(struct rc_instruction * fullinst,
 {
 	struct rc_sub_instruction * inst = &fullinst->U.I;
 	const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->Opcode);
+	unsigned int remapped_presub = 0;
 
 	if (opcode->HasDstReg) {
 		rc_register_file file = inst->DstReg.File;
@@ -327,6 +367,12 @@ static void remap_normal_instruction(struct rc_instruction * fullinst,
 			unsigned int i;
 			unsigned int srcp_srcs = rc_presubtract_src_reg_count(
 						inst->PreSub.Opcode);
+			/* Make sure we only remap presubtract sources once in
+			 * case more than one source register reads the
+			 * presubtract result. */
+			if (remapped_presub)
+				continue;
+
 			for(i = 0; i < srcp_srcs; i++) {
 				file = inst->PreSub.SrcReg[i].File;
 				index = inst->PreSub.SrcReg[i].Index;
@@ -334,7 +380,7 @@ static void remap_normal_instruction(struct rc_instruction * fullinst,
 				inst->PreSub.SrcReg[i].File = file;
 				inst->PreSub.SrcReg[i].Index = index;
 			}
-
+			remapped_presub = 1;
 		}
 		else {
 			cb(userdata, fullinst, &file, &index);
@@ -430,12 +476,29 @@ static rc_opcode get_flow_control_inst(struct rc_instruction * inst)
 
 }
 
+struct branch_write_mask {
+	unsigned int IfWriteMask:4;
+	unsigned int ElseWriteMask:4;
+	unsigned int HasElse:1;
+};
+
+union get_readers_read_cb {
+	rc_read_src_fn I;
+	rc_pair_read_arg_fn P;
+};
+
 struct get_readers_callback_data {
 	struct radeon_compiler * C;
 	struct rc_reader_data * ReaderData;
-	rc_read_src_fn ReadCB;
+	rc_read_src_fn ReadNormalCB;
+	rc_pair_read_arg_fn ReadPairCB;
 	rc_read_write_mask_fn WriteCB;
+	rc_register_file DstFile;
+	unsigned int DstIndex;
+	unsigned int DstMask;
 	unsigned int AliveWriteMask;
+	/*  For convenience, this is indexed starting at 1 */
+	struct branch_write_mask BranchMasks[R500_PFS_MAX_BRANCH_DEPTH_FULL + 1];
 };
 
 static void add_reader(
@@ -443,7 +506,7 @@ static void add_reader(
 	struct rc_reader_data * data,
 	struct rc_instruction * inst,
 	unsigned int mask,
-	struct rc_src_register * src)
+	void * arg_or_src)
 {
 	struct rc_reader * new;
 	memory_pool_array_reserve(pool, struct rc_reader, data->Readers,
@@ -451,7 +514,74 @@ static void add_reader(
 	new = &data->Readers[data->ReaderCount++];
 	new->Inst = inst;
 	new->WriteMask = mask;
-	new->Src = src;
+	if (inst->Type == RC_INSTRUCTION_NORMAL) {
+		new->U.Src = arg_or_src;
+	} else {
+		new->U.Arg = arg_or_src;
+	}
+}
+
+static unsigned int get_readers_read_callback(
+	struct get_readers_callback_data * cb_data,
+	unsigned int has_rel_addr,
+	rc_register_file file,
+	unsigned int index,
+	unsigned int swizzle)
+{
+	unsigned int shared_mask, read_mask;
+
+	if (has_rel_addr) {
+		cb_data->ReaderData->Abort = 1;
+		return RC_MASK_NONE;
+	}
+
+	shared_mask = rc_src_reads_dst_mask(file, index, swizzle,
+		cb_data->DstFile, cb_data->DstIndex, cb_data->AliveWriteMask);
+
+	if (shared_mask == RC_MASK_NONE)
+		return shared_mask;
+
+	/* If we make it this far, it means that this source reads from the
+	 * same register written to by d->ReaderData->Writer. */
+
+	read_mask = rc_swizzle_to_writemask(swizzle);
+	if (cb_data->ReaderData->AbortOnRead & read_mask) {
+		cb_data->ReaderData->Abort = 1;
+		return shared_mask;
+	}
+
+	/* XXX The behavior in this case should be configurable. */
+	if ((read_mask & cb_data->AliveWriteMask) != read_mask) {
+		cb_data->ReaderData->Abort = 1;
+		return shared_mask;
+	}
+
+	return shared_mask;
+}
+
+static void get_readers_pair_read_callback(
+	void * userdata,
+	struct rc_instruction * inst,
+	struct rc_pair_instruction_arg * arg,
+	struct rc_pair_instruction_source * src)
+{
+	unsigned int shared_mask;
+	struct get_readers_callback_data * d = userdata;
+
+	shared_mask = get_readers_read_callback(d,
+				0 /*Pair Instructions don't use RelAddr*/,
+				src->File, src->Index, arg->Swizzle);
+
+	if (shared_mask == RC_MASK_NONE)
+		return;
+
+	if (d->ReadPairCB)
+		d->ReadPairCB(d->ReaderData, inst, arg, src);
+
+	if (d->ReaderData->Abort)
+		return;
+
+	add_reader(&d->C->Pool, d->ReaderData, inst, shared_mask, arg);
 }
 
 /**
@@ -464,37 +594,18 @@ static void get_readers_normal_read_callback(
 	struct rc_src_register * src)
 {
 	struct get_readers_callback_data * d = userdata;
-	unsigned int read_mask;
 	unsigned int shared_mask;
 
-	if (src->RelAddr)
-		d->ReaderData->Abort = 1;
-
-	shared_mask = rc_src_reads_dst_mask(src->File, src->Index,
-		src->Swizzle,
-		d->ReaderData->Writer->U.I.DstReg.File,
-		d->ReaderData->Writer->U.I.DstReg.Index,
-		d->AliveWriteMask);
+	shared_mask = get_readers_read_callback(d,
+			src->RelAddr, src->File, src->Index, src->Swizzle);
 
 	if (shared_mask == RC_MASK_NONE)
 		return;
+	/* The callback function could potentially clear d->ReaderData->Abort,
+	 * so we need to call it before we return. */
+	if (d->ReadNormalCB)
+		d->ReadNormalCB(d->ReaderData, inst, src);
 
-	/* If we make it this far, it means that this source reads from the
-	 * same register written to by d->ReaderData->Writer. */
-
-	if (d->ReaderData->AbortOnRead) {
-		d->ReaderData->Abort = 1;
-		return;
-	}
-
-	read_mask = rc_swizzle_to_writemask(src->Swizzle);
-	/* XXX The behavior in this case should be configurable. */
-	if ((read_mask & d->AliveWriteMask) != read_mask) {
-		d->ReaderData->Abort = 1;
-		return;
-	}
-
-	d->ReadCB(d->ReaderData, inst, src);
 	if (d->ReaderData->Abort)
 		return;
 
@@ -515,29 +626,132 @@ static void get_readers_write_callback(
 {
 	struct get_readers_callback_data * d = userdata;
 
-	if (index == d->ReaderData->Writer->U.I.DstReg.Index
-		&& file == d->ReaderData->Writer->U.I.DstReg.File) {
-			unsigned int shared_mask = mask
-				& d->ReaderData->Writer->U.I.DstReg.WriteMask;
-		if (d->ReaderData->InElse) {
-			if (shared_mask & d->AliveWriteMask) {
-				/* We set AbortOnRead here because the
-				 * destination register of d->ReaderData->Writer
-				 * is written to in both the IF and the
-				 * ELSE block of this IF/ELSE statement.
-				 * This means that readers of this
-				 * destination register that follow this IF/ELSE
-				 * statement use the value of different
-				 * instructions depending on the control flow
-				 * decisions made by the program. */
-				d->ReaderData->AbortOnRead = 1;
+	if (index == d->DstIndex && file == d->DstFile) {
+		unsigned int shared_mask = mask & d->DstMask;
+		d->ReaderData->AbortOnRead &= ~shared_mask;
+		d->AliveWriteMask &= ~shared_mask;
+	}
+
+	if(d->WriteCB)
+		d->WriteCB(d->ReaderData, inst, file, index, mask);
+}
+
+static void get_readers_for_single_write(
+	void * userdata,
+	struct rc_instruction * writer,
+	rc_register_file dst_file,
+	unsigned int dst_index,
+	unsigned int dst_mask)
+{
+	struct rc_instruction * tmp;
+	unsigned int branch_depth = 0;
+	struct get_readers_callback_data * d = userdata;
+
+	d->ReaderData->Writer = writer;
+	d->ReaderData->AbortOnRead = 0;
+	d->ReaderData->InElse = 0;
+	d->DstFile = dst_file;
+	d->DstIndex = dst_index;
+	d->DstMask = dst_mask;
+	d->AliveWriteMask = dst_mask;
+	memset(d->BranchMasks, 0, sizeof(d->BranchMasks));
+
+	if (!dst_mask)
+		return;
+
+	for(tmp = writer->Next; tmp != &d->C->Program.Instructions;
+							tmp = tmp->Next){
+		rc_opcode opcode = get_flow_control_inst(tmp);
+		switch(opcode) {
+		case RC_OPCODE_BGNLOOP:
+			/* XXX We can do better when we see a BGNLOOP if we
+			 * add a flag called AbortOnWrite to struct
+			 * rc_reader_data and leave it set until the next
+			 * ENDLOOP. */
+		case RC_OPCODE_ENDLOOP:
+			/* XXX We can do better when we see an ENDLOOP by
+			 * searching backwards from writer and looking for
+			 * readers of writer's destination index.  If we find a
+			 * reader before we get to the BGNLOOP, we must abort
+			 * unless there is another writer between that reader
+			 * and the BGNLOOP. */
+		case RC_OPCODE_BRK:
+		case RC_OPCODE_CONT:
+			d->ReaderData->Abort = 1;
+			return;
+		case RC_OPCODE_IF:
+			branch_depth++;
+			if (branch_depth > R500_PFS_MAX_BRANCH_DEPTH_FULL) {
+				d->ReaderData->Abort = 1;
+				return;
+			}
+			d->BranchMasks[branch_depth].IfWriteMask =
+							d->AliveWriteMask;
+			break;
+		case RC_OPCODE_ELSE:
+			if (branch_depth == 0) {
+				d->ReaderData->InElse = 1;
+			} else {
+				unsigned int temp_mask = d->AliveWriteMask;
+				d->AliveWriteMask =
+					d->BranchMasks[branch_depth].IfWriteMask;
+				d->BranchMasks[branch_depth].ElseWriteMask =
+								temp_mask;
+				d->BranchMasks[branch_depth].HasElse = 1;
 			}
+			break;
+		case RC_OPCODE_ENDIF:
+			if (branch_depth == 0) {
+				d->ReaderData->AbortOnRead = d->AliveWriteMask;
+				d->ReaderData->InElse = 0;
+			}
+			else {
+				struct branch_write_mask * masks =
+					&d->BranchMasks[branch_depth];
+
+				if (masks->HasElse) {
+					d->ReaderData->AbortOnRead |=
+						masks->IfWriteMask
+							& ~masks->ElseWriteMask;
+					d->AliveWriteMask = masks->IfWriteMask
+						^ ((masks->IfWriteMask ^
+							masks->ElseWriteMask)
+						& (masks->IfWriteMask
+							^ d->AliveWriteMask));
+				} else {
+					d->ReaderData->AbortOnRead |=
+						masks->IfWriteMask
+							& ~d->AliveWriteMask;
+					d->AliveWriteMask = masks->IfWriteMask;
+
+				}
+				memset(masks, 0,
+					sizeof(struct branch_write_mask));
+				branch_depth--;
+			}
+			break;
+		default:
+			break;
+		}
+
+		if (d->ReaderData->InElse)
+			continue;
+
+		if (tmp->Type == RC_INSTRUCTION_NORMAL) {
+			rc_for_all_reads_src(tmp,
+				get_readers_normal_read_callback, d);
 		} else {
-			d->AliveWriteMask &= ~shared_mask;
+			rc_pair_for_all_reads_arg(tmp,
+				get_readers_pair_read_callback, d);
 		}
-	}
+		rc_for_all_writes_mask(tmp, get_readers_write_callback, d);
 
-	d->WriteCB(d->ReaderData, inst, file, index, mask);
+		if (d->ReaderData->Abort)
+			return;
+
+		if (branch_depth == 0 && !d->AliveWriteMask)
+			return;
+	}
 }
 
 /**
@@ -578,83 +792,26 @@ static void get_readers_write_callback(
  * @param write_cb This function will be called for every instruction after
  * writer.
  */
-void  rc_get_readers_normal(
+void rc_get_readers(
 	struct radeon_compiler * c,
 	struct rc_instruction * writer,
 	struct rc_reader_data * data,
-	rc_read_src_fn read_cb,
+	rc_read_src_fn read_normal_cb,
+	rc_pair_read_arg_fn read_pair_cb,
 	rc_read_write_mask_fn write_cb)
 {
-	struct rc_instruction * tmp;
 	struct get_readers_callback_data d;
-	unsigned int branch_depth = 0;
 
-	data->Writer = writer;
 	data->Abort = 0;
-	data->AbortOnRead = 0;
-	data->InElse = 0;
 	data->ReaderCount = 0;
 	data->ReadersReserved = 0;
 	data->Readers = NULL;
 
 	d.C = c;
-	d.AliveWriteMask = writer->U.I.DstReg.WriteMask;
 	d.ReaderData = data;
-	d.ReadCB = read_cb;
+	d.ReadNormalCB = read_normal_cb;
+	d.ReadPairCB = read_pair_cb;
 	d.WriteCB = write_cb;
 
-	if (!writer->U.I.DstReg.WriteMask)
-		return;
-
-	for(tmp = writer->Next; tmp != &c->Program.Instructions;
-							tmp = tmp->Next){
-		rc_opcode opcode = get_flow_control_inst(tmp);
-		switch(opcode) {
-		case RC_OPCODE_BGNLOOP:
-			/* XXX We can do better when we see a BGNLOOP if we
-			 * add a flag called AbortOnWrite to struct
-			 * rc_reader_data and leave it set until the next
-			 * ENDLOOP. */
-		case RC_OPCODE_ENDLOOP:
-			/* XXX We can do better when we see an ENDLOOP by
-			 * searching backwards from writer and looking for
-			 * readers of writer's destination index.  If we find a
-			 * reader before we get to the BGNLOOP, we must abort
-			 * unless there is another writer between that reader
-			 * and the BGNLOOP. */
-			data->Abort = 1;
-			return;
-		case RC_OPCODE_IF:
-			/* XXX We can do better here, but this will have to
-			 * do until this dataflow analysis is more mature. */
-			data->Abort = 1;
-			branch_depth++;
-			break;
-		case RC_OPCODE_ELSE:
-			if (branch_depth == 0)
-				data->InElse = 1;
-			break;
-		case RC_OPCODE_ENDIF:
-			if (branch_depth == 0) {
-				data->AbortOnRead = 1;
-				data->InElse = 0;
-			}
-			else {
-				branch_depth--;
-			}
-			break;
-		default:
-			break;
-		}
-
-		if (!data->InElse)
-			rc_for_all_reads_src(tmp, get_readers_normal_read_callback, &d);
-		rc_for_all_writes_mask(tmp, get_readers_write_callback, &d);
-
-		if (data->Abort)
-			return;
-
-		if (!d.AliveWriteMask)
-			return;
-	}
+	rc_for_all_writes_mask(writer, get_readers_for_single_write, &d);
 }
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h
index 7de6b98f76..ef971c5b23 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.h
@@ -36,6 +36,7 @@ struct rc_instruction;
 struct rc_swizzle_caps;
 struct rc_src_register;
 struct rc_pair_instruction_arg;
+struct rc_pair_instruction_source;
 struct rc_compiler;
 
 
@@ -59,7 +60,8 @@ void rc_for_all_reads_src(struct rc_instruction * inst, rc_read_src_fn cb,
 			void * userdata);
 
 typedef void (*rc_pair_read_arg_fn)(void * userdata,
-	struct rc_instruction * inst, struct rc_pair_instruction_arg * arg);
+	struct rc_instruction * inst, struct rc_pair_instruction_arg * arg,
+	struct rc_pair_instruction_source * src);
 void rc_pair_for_all_reads_arg(struct rc_instruction * inst,
 					rc_pair_read_arg_fn cb, void * userdata);
 
@@ -71,7 +73,10 @@ void rc_remap_registers(struct rc_instruction * inst, rc_remap_register_fn cb, v
 struct rc_reader {
 	struct rc_instruction * Inst;
 	unsigned int WriteMask;
-	struct rc_src_register * Src;
+	union {
+		struct rc_src_register * Src;
+		struct rc_pair_instruction_arg * Arg;
+	} U;
 };
 
 struct rc_reader_data {
@@ -87,14 +92,13 @@ struct rc_reader_data {
 	void * CbData;
 };
 
-void rc_get_readers_normal(
+void rc_get_readers(
 	struct radeon_compiler * c,
-	struct rc_instruction * inst,
+	struct rc_instruction * writer,
 	struct rc_reader_data * data,
-	/*XXX: These should be their own function types. */
-	rc_read_src_fn read_cb,
+	rc_read_src_fn read_normal_cb,
+	rc_pair_read_arg_fn read_pair_cb,
 	rc_read_write_mask_fn write_cb);
-
 /**
  * Compiler passes based on dataflow analysis.
  */
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c
index a0f7bd8174..133a9f72ec 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c
@@ -56,6 +56,7 @@ static void rewrite_source(struct radeon_compiler * c,
 		mov->U.I.DstReg.Index = tempreg;
 		mov->U.I.DstReg.WriteMask = split.Phase[phase];
 		mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
+		mov->U.I.PreSub = inst->U.I.PreSub;
 
 		phase_refmask = 0;
 		for(unsigned int chan = 0; chan < 4; ++chan) {
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index da495a3afa..25afd272be 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -67,6 +67,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.IsComponentwise = 1
 	},
 	{
+		.Opcode = RC_OPCODE_CLAMP,
+		.Name = "CLAMP",
+		.NumSrcRegs = 3,
+		.HasDstReg = 1,
+		.IsComponentwise = 1
+	},
+	{
 		.Opcode = RC_OPCODE_CMP,
 		.Name = "CMP",
 		.NumSrcRegs = 3,
@@ -453,6 +460,7 @@ void rc_compute_sources_for_writemask(
 			srcmasks[1] |= RC_MASK_XY;
 			break;
 		case RC_OPCODE_DP3:
+		case RC_OPCODE_XPD:
 			srcmasks[0] |= RC_MASK_XYZ;
 			srcmasks[1] |= RC_MASK_XYZ;
 			break;
@@ -460,6 +468,10 @@ void rc_compute_sources_for_writemask(
 			srcmasks[0] |= RC_MASK_XYZW;
 			srcmasks[1] |= RC_MASK_XYZW;
 			break;
+		case RC_OPCODE_DPH:
+			srcmasks[0] |= RC_MASK_XYZ;
+			srcmasks[1] |= RC_MASK_XYZW;
+			break;
 		case RC_OPCODE_TXB:
 		case RC_OPCODE_TXP:
 			srcmasks[0] |= RC_MASK_W;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
index d3f639c870..7e66610127 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
@@ -50,6 +50,9 @@ typedef enum {
 	/** vec4 instruction: dst.c = ceil(src0.c) */
 	RC_OPCODE_CEIL,
 
+	/** vec4 instruction: dst.c = clamp(src0.c, src1.c, src2.c) */
+	RC_OPCODE_CLAMP,
+
 	/** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
 	RC_OPCODE_CMP,
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
index 15b9c5e7dc..44f4c0fbdc 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
@@ -54,12 +54,7 @@ static struct rc_src_register chain_srcregs(struct rc_src_register outer, struct
 		combine.Negate = outer.Negate;
 	} else {
 		combine.Abs = inner.Abs;
-		combine.Negate = 0;
-		for(unsigned int chan = 0; chan < 4; ++chan) {
-			unsigned int swz = GET_SWZ(outer.Swizzle, chan);
-			if (swz < 4)
-				combine.Negate |= GET_BIT(inner.Negate, swz) << chan;
-		}
+		combine.Negate = swizzle_mask(outer.Swizzle, inner.Negate);
 		combine.Negate ^= outer.Negate;
 	}
 	combine.Swizzle = combine_swizzles(inner.Swizzle, outer.Swizzle);
@@ -71,12 +66,13 @@ static void copy_propagate_scan_read(void * data, struct rc_instruction * inst,
 {
 	rc_register_file file = src->File;
 	struct rc_reader_data * reader_data = data;
-	const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode);
 
-	/* It is possible to do copy propigation in this situation,
-	 * just not right now, see peephole_add_presub_inv() */
-	if (reader_data->Writer->U.I.PreSub.Opcode != RC_PRESUB_NONE &&
-			(info->NumSrcRegs > 2 || info->HasTexture)) {
+	if(!rc_inst_can_use_presub(inst,
+				reader_data->Writer->U.I.PreSub.Opcode,
+				rc_swizzle_to_writemask(src->Swizzle),
+				*src,
+				reader_data->Writer->U.I.PreSub.SrcReg[0],
+				reader_data->Writer->U.I.PreSub.SrcReg[1])) {
 		reader_data->Abort = 1;
 		return;
 	}
@@ -112,11 +108,11 @@ static void src_clobbered_reads_cb(
 	    && src->Index == sc_data->Index
 	    && (rc_swizzle_to_writemask(src->Swizzle) & sc_data->Mask)) {
 
-		sc_data->ReaderData->AbortOnRead = 1;
+		sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW;
 	}
 
 	if (src->RelAddr && sc_data->File == RC_FILE_ADDRESS) {
-		sc_data->ReaderData->AbortOnRead = 1;
+		sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW;
 	}
 }
 
@@ -149,8 +145,9 @@ static void copy_propagate(struct radeon_compiler * c, struct rc_instruction * i
 		return;
 
 	/* Get a list of all the readers of this MOV instruction. */
-	rc_get_readers_normal(c, inst_mov, &reader_data,
-			copy_propagate_scan_read, is_src_clobbered_scan_write);
+	rc_get_readers(c, inst_mov, &reader_data,
+		       copy_propagate_scan_read, NULL,
+		       is_src_clobbered_scan_write);
 
 	if (reader_data.Abort || reader_data.ReaderCount == 0)
 		return;
@@ -158,7 +155,7 @@ static void copy_propagate(struct radeon_compiler * c, struct rc_instruction * i
 	/* Propagate the MOV instruction. */
 	for (i = 0; i < reader_data.ReaderCount; i++) {
 		struct rc_instruction * inst = reader_data.Readers[i].Inst;
-		*reader_data.Readers[i].Src = chain_srcregs(*reader_data.Readers[i].Src, inst_mov->U.I.SrcReg[0]);
+		*reader_data.Readers[i].U.Src = chain_srcregs(*reader_data.Readers[i].U.Src, inst_mov->U.I.SrcReg[0]);
 
 		if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB)
 			inst->U.I.PreSub = inst_mov->U.I.PreSub;
@@ -423,24 +420,13 @@ static void presub_scan_read(
 	struct rc_src_register * src)
 {
 	struct rc_reader_data * reader_data = data;
-	const struct rc_opcode_info * info =
-					rc_get_opcode_info(inst->U.I.Opcode);
-	/* XXX: There are some situations where instructions
-	 * with more than 2 src registers can use the
-	 * presubtract select, but to keep things simple we
-	 * will disable presubtract on these instructions for
-	 * now. */
-	if (info->NumSrcRegs > 2 || info->HasTexture) {
-		reader_data->Abort = 1;
-		return;
-	}
+	rc_presubtract_op * presub_opcode = reader_data->CbData;
 
-	/* We can't use more than one presubtract value in an
-	 * instruction, unless the two prsubtract operations
-	 * are the same and read from the same registers.
-	 * XXX For now we will limit instructions to only one presubtract
-	 * value.*/
-	if (inst->U.I.PreSub.Opcode != RC_PRESUB_NONE) {
+	if (!rc_inst_can_use_presub(inst, *presub_opcode,
+			reader_data->Writer->U.I.DstReg.WriteMask,
+			*src,
+			reader_data->Writer->U.I.SrcReg[0],
+			reader_data->Writer->U.I.SrcReg[1])) {
 		reader_data->Abort = 1;
 		return;
 	}
@@ -454,8 +440,10 @@ static int presub_helper(
 {
 	struct rc_reader_data reader_data;
 	unsigned int i;
+	rc_presubtract_op cb_op = presub_opcode;
 
-	rc_get_readers_normal(c, inst_add, &reader_data, presub_scan_read,
+	reader_data.CbData = &cb_op;
+	rc_get_readers(c, inst_add, &reader_data, presub_scan_read, NULL,
 						is_src_clobbered_scan_write);
 
 	if (reader_data.Abort || reader_data.ReaderCount == 0)
@@ -468,7 +456,7 @@ static int presub_helper(
 				rc_get_opcode_info(reader.Inst->U.I.Opcode);
 
 		for (src_index = 0; src_index < info->NumSrcRegs; src_index++) {
-			if (&reader.Inst->U.I.SrcReg[src_index] == reader.Src)
+			if (&reader.Inst->U.I.SrcReg[src_index] == reader.U.Src)
 				presub_replace(inst_add, reader.Inst, src_index);
 		}
 	}
@@ -505,7 +493,9 @@ static void presub_replace_add(
 	inst_reader->U.I.SrcReg[src_index].Index = presub_opcode;
 }
 
-static int is_presub_candidate(struct rc_instruction * inst)
+static int is_presub_candidate(
+	struct radeon_compiler * c,
+	struct rc_instruction * inst)
 {
 	const struct rc_opcode_info * info = rc_get_opcode_info(inst->U.I.Opcode);
 	unsigned int i;
@@ -514,7 +504,12 @@ static int is_presub_candidate(struct rc_instruction * inst)
 		return 0;
 
 	for(i = 0; i < info->NumSrcRegs; i++) {
-		if (src_reads_dst_mask(inst->U.I.SrcReg[i], inst->U.I.DstReg))
+		struct rc_src_register src = inst->U.I.SrcReg[i];
+		if (src_reads_dst_mask(src, inst->U.I.DstReg))
+			return 0;
+
+		src.File = RC_FILE_PRESUB;
+		if (!c->SwizzleCaps->IsNative(inst->U.I.Opcode, src))
 			return 0;
 	}
 	return 1;
@@ -528,7 +523,7 @@ static int peephole_add_presub_add(
 	struct rc_src_register * src1 = NULL;
 	unsigned int i;
 
-	if (!is_presub_candidate(inst_add))
+	if (!is_presub_candidate(c, inst_add))
 		return 0;
 
 	if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle)
@@ -592,7 +587,7 @@ static int peephole_add_presub_inv(
 {
 	unsigned int i, swz, mask;
 
-	if (!is_presub_candidate(inst_add))
+	if (!is_presub_candidate(c, inst_add))
 		return 0;
 
 	mask = inst_add->U.I.DstReg.WriteMask;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c
index 91524f5ec6..d53181e1f7 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_regalloc.c
@@ -66,10 +66,13 @@ struct regalloc_state {
 	struct hardware_register * HwTemporary;
 	unsigned int NumHwTemporaries;
 	/**
-	 * If an instruction is inside of a loop, end_loop will be the
-	 * IP of the ENDLOOP instruction, otherwise end_loop will be 0
+	 * If an instruction is inside of a loop, EndLoop will be the
+	 * IP of the ENDLOOP instruction, and BeginLoop will be the IP
+	 * of the BGNLOOP instruction.  Otherwise, EndLoop and BeginLoop
+	 * will be -1.
 	 */
-	int end_loop;
+	int EndLoop;
+	int BeginLoop;
 };
 
 static void print_live_intervals(struct live_intervals * src)
@@ -180,11 +183,13 @@ static void scan_callback(void * data, struct rc_instruction * inst,
 		reg->Used = 1;
 		if (file == RC_FILE_INPUT)
 			reg->Live.Start = -1;
+		else if (s->BeginLoop >= 0)
+			reg->Live.Start = s->BeginLoop;
 		else
 			reg->Live.Start = inst->IP;
 		reg->Live.End = inst->IP;
-	} else if (s->end_loop)
-		reg->Live.End = s->end_loop;
+	} else if (s->EndLoop >= 0)
+		reg->Live.End = s->EndLoop;
 	else if (inst->IP > reg->Live.End)
 		reg->Live.End = inst->IP;
 }
@@ -195,6 +200,8 @@ static void compute_live_intervals(struct radeon_compiler *c,
 	memset(s, 0, sizeof(*s));
 	s->C = c;
 	s->NumHwTemporaries = c->max_temp_regs;
+	s->BeginLoop = -1;
+	s->EndLoop = -1;
 	s->HwTemporary =
 		memory_pool_malloc(&c->Pool,
 				   s->NumHwTemporaries * sizeof(struct hardware_register));
@@ -207,10 +214,12 @@ static void compute_live_intervals(struct radeon_compiler *c,
 	    inst = inst->Next) {
 
 		/* For all instructions inside of a loop, the ENDLOOP
-		 * instruction is used as the end of the live interval. */
-		if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP && !s->end_loop) {
+		 * instruction is used as the end of the live interval and
+		 * the BGNLOOP instruction is used as the beginning. */
+		if (inst->U.I.Opcode == RC_OPCODE_BGNLOOP && s->EndLoop < 0) {
 			int loops = 1;
 			struct rc_instruction * tmp;
+			s->BeginLoop = inst->IP;
 			for(tmp = inst->Next;
 					tmp != &s->C->Program.Instructions;
 					tmp = tmp->Next) {
@@ -219,15 +228,17 @@ static void compute_live_intervals(struct radeon_compiler *c,
 				} else if (tmp->U.I.Opcode
 							== RC_OPCODE_ENDLOOP) {
 					if(!--loops) {
-						s->end_loop = tmp->IP;
+						s->EndLoop = tmp->IP;
 						break;
 					}
 				}
 			}
 		}
 
-		if (inst->IP == s->end_loop)
-			s->end_loop = 0;
+		if (inst->IP == s->EndLoop) {
+			s->EndLoop = -1;
+			s->BeginLoop = -1;
+		}
 
 		rc_for_all_reads_mask(inst, scan_callback, s);
 		rc_for_all_writes_mask(inst, scan_callback, s);
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c
index 553e9dcf7c..9beb5d6357 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_schedule.c
@@ -30,6 +30,7 @@
 #include <stdio.h>
 
 #include "radeon_compiler.h"
+#include "radeon_compiler_util.h"
 #include "radeon_dataflow.h"
 
 
@@ -54,6 +55,11 @@ struct schedule_instruction {
 	 * this instruction can be scheduled.
 	 */
 	unsigned int NumDependencies:5;
+
+	/** List of all readers (see rc_get_readers() for the definition of
+	 * "all readers"), even those outside the basic block this instruction
+	 * lives in. */
+	struct rc_reader_data GlobalReaders;
 };
 
 
@@ -94,6 +100,16 @@ struct register_state {
 	struct reg_value * Values[4];
 };
 
+struct remap_reg {
+	struct rc_instruciont * Inst;
+	unsigned int OldIndex:(RC_REGISTER_INDEX_BITS+1);
+	unsigned int OldSwizzle:3;
+	unsigned int NewIndex:(RC_REGISTER_INDEX_BITS+1);
+	unsigned int NewSwizzle:3;
+	unsigned int OnlyTexReads:1;
+	struct remap_reg * Next;
+};
+
 struct schedule_state {
 	struct radeon_compiler * C;
 	struct schedule_instruction * Current;
@@ -126,15 +142,6 @@ static struct reg_value ** get_reg_valuep(struct schedule_state * s,
 	return &s->Temporary[index].Values[chan];
 }
 
-static struct reg_value * get_reg_value(struct schedule_state * s,
-		rc_register_file file, unsigned int index, unsigned int chan)
-{
-	struct reg_value ** pv = get_reg_valuep(s, file, index, chan);
-	if (!pv)
-		return 0;
-	return *pv;
-}
-
 static void add_inst_to_list(struct schedule_instruction ** list, struct schedule_instruction * inst)
 {
 	inst->NextReady = *list;
@@ -295,12 +302,12 @@ static int merge_presub_sources(
 	assert(dst_full->Alpha.Opcode == RC_OPCODE_NOP);
 
 	switch(type) {
-	case RC_PAIR_SOURCE_RGB:
+	case RC_SOURCE_RGB:
 		is_rgb = 1;
 		is_alpha = 0;
 		dst_sub = &dst_full->RGB;
 		break;
-	case RC_PAIR_SOURCE_ALPHA:
+	case RC_SOURCE_ALPHA:
 		is_rgb = 0;
 		is_alpha = 1;
 		dst_sub = &dst_full->Alpha;
@@ -341,6 +348,8 @@ static int merge_presub_sources(
 				continue;
 			free_source = rc_pair_alloc_source(dst_full, is_rgb,
 					is_alpha, temp.File, temp.Index);
+			if (free_source < 0)
+				return 0;
 			one_way = 1;
 		} else {
 			dst_sub->Src[free_source] = temp;
@@ -356,11 +365,11 @@ static int merge_presub_sources(
 		for(arg = 0; arg < info->NumSrcRegs; arg++) {
 			/*If this arg does not read from an rgb source,
 			 * do nothing. */
-			if (!(rc_source_type_that_arg_reads(
-				dst_full->RGB.Arg[arg].Source,
-				dst_full->RGB.Arg[arg].Swizzle) & type)) {
+			if (!(rc_source_type_swz(dst_full->RGB.Arg[arg].Swizzle,
+								3) & type)) {
 				continue;
 			}
+
 			if (dst_full->RGB.Arg[arg].Source == srcp_src)
 				dst_full->RGB.Arg[arg].Source = free_source;
 			/* We need to do this just in case register
@@ -392,13 +401,13 @@ static int destructive_merge_instructions(
 
 	/* Merge the rgb presubtract registers. */
 	if (alpha->RGB.Src[RC_PAIR_PRESUB_SRC].Used) {
-		if (!merge_presub_sources(rgb, alpha->RGB, RC_PAIR_SOURCE_RGB)) {
+		if (!merge_presub_sources(rgb, alpha->RGB, RC_SOURCE_RGB)) {
 			return 0;
 		}
 	}
 	/* Merge the alpha presubtract registers */
 	if (alpha->Alpha.Src[RC_PAIR_PRESUB_SRC].Used) {
-		if(!merge_presub_sources(rgb,  alpha->Alpha, RC_PAIR_SOURCE_ALPHA)){
+		if(!merge_presub_sources(rgb,  alpha->Alpha, RC_SOURCE_ALPHA)){
 			return 0;
 		}
 	}
@@ -525,6 +534,222 @@ static void presub_nop(struct rc_instruction * emitted) {
 		}
 	}
 }
+
+static void rgb_to_alpha_remap (
+	struct rc_instruction * inst,
+	struct rc_pair_instruction_arg * arg,
+	rc_register_file old_file,
+	rc_swizzle old_swz,
+	unsigned int new_index)
+{
+	int new_src_index;
+	unsigned int i;
+	struct rc_pair_instruction_source * old_src =
+					rc_pair_get_src(&inst->U.P, arg);
+	if (!old_src) {
+		return;
+	}
+
+	for (i = 0; i < 3; i++) {
+		if (get_swz(arg->Swizzle, i) == old_swz) {
+			SET_SWZ(arg->Swizzle, i, RC_SWIZZLE_W);
+		}
+	}
+	memset(old_src, 0, sizeof(struct rc_pair_instruction_source));
+	new_src_index = rc_pair_alloc_source(&inst->U.P, 0, 1,
+							old_file, new_index);
+	/* This conversion is not possible, we must have made a mistake in
+	 * is_rgb_to_alpha_possible. */
+	if (new_src_index < 0) {
+		assert(0);
+		return;
+	}
+
+	arg->Source = new_src_index;
+}
+
+static int can_remap(unsigned int opcode)
+{
+	switch(opcode) {
+	case RC_OPCODE_DDX:
+	case RC_OPCODE_DDY:
+		return 0;
+	default:
+		return 1;
+	}
+}
+
+static int can_convert_opcode_to_alpha(unsigned int opcode)
+{
+	switch(opcode) {
+	case RC_OPCODE_DDX:
+	case RC_OPCODE_DDY:
+	case RC_OPCODE_DP2:
+	case RC_OPCODE_DP3:
+	case RC_OPCODE_DP4:
+	case RC_OPCODE_DPH:
+		return 0;
+	default:
+		return 1;
+	}
+}
+
+static void is_rgb_to_alpha_possible(
+	void * userdata,
+	struct rc_instruction * inst,
+	struct rc_pair_instruction_arg * arg,
+	struct rc_pair_instruction_source * src)
+{
+	unsigned int chan_count = 0;
+	unsigned int alpha_sources = 0;
+	unsigned int i;
+	struct rc_reader_data * reader_data = userdata;
+
+	if (!can_remap(inst->U.P.RGB.Opcode)
+	    || !can_remap(inst->U.P.Alpha.Opcode)) {
+		reader_data->Abort = 1;
+		return;
+	}
+
+	if (!src)
+		return;
+
+	/* XXX There are some cases where we can still do the conversion if
+	 * a reader reads from a presubtract source, but for now we'll prevent
+	 * it. */
+	if (arg->Source == RC_PAIR_PRESUB_SRC) {
+		reader_data->Abort = 1;
+		return;
+	}
+
+	/* Make sure the source only reads from one component.
+	 * XXX We should allow the source to read from the same component twice.
+	 * XXX If the index we will be converting to is the same as the
+	 * current index, then it is OK to read from more than one component.
+	 */
+	for (i = 0; i < 3; i++) {
+		rc_swizzle swz = get_swz(arg->Swizzle, i);
+		switch(swz) {
+		case RC_SWIZZLE_X:
+		case RC_SWIZZLE_Y:
+		case RC_SWIZZLE_Z:
+		case RC_SWIZZLE_W:
+			chan_count++;
+			break;
+		default:
+			break;
+		}
+	}
+	if (chan_count > 1) {
+		reader_data->Abort = 1;
+		return;
+	}
+
+	/* Make sure there are enough alpha sources.
+	 * XXX If we know what register all the readers are going
+	 * to be remapped to, then in some situations we can still do
+	 * the subsitution, even if all 3 alpha sources are being used.*/
+	for (i = 0; i < 3; i++) {
+		if (inst->U.P.Alpha.Src[i].Used) {
+			alpha_sources++;
+		}
+	}
+	if (alpha_sources > 2) {
+		reader_data->Abort = 1;
+		return;
+	}
+}
+
+static int convert_rgb_to_alpha(
+	struct schedule_state * s,
+	struct schedule_instruction * sched_inst)
+{
+	struct rc_pair_instruction * pair_inst = &sched_inst->Instruction->U.P;
+	unsigned int old_mask = pair_inst->RGB.WriteMask;
+	unsigned int old_swz = rc_mask_to_swizzle(old_mask);
+	const struct rc_opcode_info * info =
+				rc_get_opcode_info(pair_inst->RGB.Opcode);
+	int new_index = -1;
+	unsigned int i;
+
+	if (sched_inst->GlobalReaders.Abort)
+		return 0;
+
+	if (!pair_inst->RGB.WriteMask)
+		return 0;
+
+	if (!can_convert_opcode_to_alpha(pair_inst->RGB.Opcode)
+	    || !can_convert_opcode_to_alpha(pair_inst->Alpha.Opcode)) {
+		return 0;
+	}
+
+	assert(sched_inst->NumWriteValues == 1);
+
+	if (!sched_inst->WriteValues[0]) {
+		assert(0);
+		return 0;
+	}
+
+	/* We start at the old index, because if we can reuse the same
+	 * register and just change the swizzle then it is more likely we
+	 * will be able to convert all the readers. */
+	for (i = pair_inst->RGB.DestIndex; i < RC_REGISTER_MAX_INDEX; i++) {
+		struct reg_value ** new_regvalp = get_reg_valuep(
+						s, RC_FILE_TEMPORARY, i, 3);
+		if (!*new_regvalp) {
+			struct reg_value ** old_regvalp =
+				get_reg_valuep(s,
+					RC_FILE_TEMPORARY,
+					pair_inst->RGB.DestIndex,
+					rc_mask_to_swizzle(old_mask));
+			new_index = i;
+			*new_regvalp = *old_regvalp;
+			*old_regvalp = NULL;
+			new_regvalp = get_reg_valuep(s, RC_FILE_TEMPORARY, i, 3);
+			break;
+		}
+	}
+	if (new_index < 0) {
+		return 0;
+	}
+
+	pair_inst->Alpha.Opcode = pair_inst->RGB.Opcode;
+	pair_inst->Alpha.DestIndex = new_index;
+	pair_inst->Alpha.WriteMask = 1;
+	pair_inst->Alpha.Target = pair_inst->RGB.Target;
+	pair_inst->Alpha.OutputWriteMask = pair_inst->RGB.OutputWriteMask;
+	pair_inst->Alpha.DepthWriteMask = pair_inst->RGB.DepthWriteMask;
+	pair_inst->Alpha.Saturate = pair_inst->RGB.Saturate;
+	memcpy(pair_inst->Alpha.Arg, pair_inst->RGB.Arg,
+						sizeof(pair_inst->Alpha.Arg));
+	/* Move the swizzles into the first chan */
+	for (i = 0; i < info->NumSrcRegs; i++) {
+		unsigned int j;
+		for (j = 0; j < 3; j++) {
+			unsigned int swz = get_swz(pair_inst->Alpha.Arg[i].Swizzle, j);
+			if (swz != RC_SWIZZLE_UNUSED) {
+				pair_inst->Alpha.Arg[i].Swizzle = swz;
+				break;
+			}
+		}
+	}
+	pair_inst->RGB.Opcode = RC_OPCODE_NOP;
+	pair_inst->RGB.DestIndex = 0;
+	pair_inst->RGB.WriteMask = 0;
+	pair_inst->RGB.Target = 0;
+	pair_inst->RGB.OutputWriteMask = 0;
+	pair_inst->RGB.DepthWriteMask = 0;
+	pair_inst->RGB.Saturate = 0;
+	memset(pair_inst->RGB.Arg, 0, sizeof(pair_inst->RGB.Arg));
+
+	for(i = 0; i < sched_inst->GlobalReaders.ReaderCount; i++) {
+		struct rc_reader reader = sched_inst->GlobalReaders.Readers[i];
+		rgb_to_alpha_remap(reader.Inst, reader.U.Arg,
+					RC_FILE_TEMPORARY, old_swz, new_index);
+	}
+	return 1;
+}
+
 /**
  * Find a good ALU instruction or pair of ALU instruction and emit it.
  *
@@ -536,24 +761,16 @@ static void emit_one_alu(struct schedule_state *s, struct rc_instruction * befor
 {
 	struct schedule_instruction * sinst;
 
-	if (s->ReadyFullALU || !(s->ReadyRGB && s->ReadyAlpha)) {
-		if (s->ReadyFullALU) {
-			sinst = s->ReadyFullALU;
-			s->ReadyFullALU = s->ReadyFullALU->NextReady;
-		} else if (s->ReadyRGB) {
-			sinst = s->ReadyRGB;
-			s->ReadyRGB = s->ReadyRGB->NextReady;
-		} else {
-			sinst = s->ReadyAlpha;
-			s->ReadyAlpha = s->ReadyAlpha->NextReady;
-		}
-
+	if (s->ReadyFullALU) {
+		sinst = s->ReadyFullALU;
+		s->ReadyFullALU = s->ReadyFullALU->NextReady;
 		rc_insert_instruction(before->Prev, sinst->Instruction);
 		commit_alu_instruction(s, sinst);
 	} else {
 		struct schedule_instruction **prgb;
 		struct schedule_instruction **palpha;
-
+		struct schedule_instruction *prev;
+pair:
 		/* Some pairings might fail because they require too
 		 * many source slots; try all possible pairings if necessary */
 		for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) {
@@ -572,10 +789,43 @@ static void emit_one_alu(struct schedule_state *s, struct rc_instruction * befor
 				goto success;
 			}
 		}
-
-		/* No success in pairing; just take the first RGB instruction */
-		sinst = s->ReadyRGB;
-		s->ReadyRGB = s->ReadyRGB->NextReady;
+		prev = NULL;
+		/* No success in pairing, now try to convert one of the RGB
+		 * instructions to an Alpha so we can pair it with another RGB.
+		 */
+		if (s->ReadyRGB && s->ReadyRGB->NextReady) {
+		for(prgb = &s->ReadyRGB; *prgb; prgb = &(*prgb)->NextReady) {
+			if ((*prgb)->NumWriteValues == 1) {
+				struct schedule_instruction * prgb_next;
+				if (!convert_rgb_to_alpha(s, *prgb))
+					goto cont_loop;
+				prgb_next = (*prgb)->NextReady;
+				/* Add instruction to the Alpha ready list. */
+				(*prgb)->NextReady = s->ReadyAlpha;
+				s->ReadyAlpha = *prgb;
+				/* Remove instruction from the RGB ready list.*/
+				if (prev)
+					prev->NextReady = prgb_next;
+				else
+					s->ReadyRGB = prgb_next;
+				goto pair;
+			}
+cont_loop:
+			prev = *prgb;
+		}
+		}
+		/* Still no success in pairing, just take the first RGB
+		 * or alpha instruction. */
+		if (s->ReadyRGB) {
+			sinst = s->ReadyRGB;
+			s->ReadyRGB = s->ReadyRGB->NextReady;
+		} else if (s->ReadyAlpha) {
+			sinst = s->ReadyAlpha;
+			s->ReadyAlpha = s->ReadyAlpha->NextReady;
+		} else {
+			/*XXX Something real bad has happened. */
+			assert(0);
+		}
 
 		rc_insert_instruction(before->Prev, sinst->Instruction);
 		commit_alu_instruction(s, sinst);
@@ -591,13 +841,13 @@ static void scan_read(void * data, struct rc_instruction * inst,
 		rc_register_file file, unsigned int index, unsigned int chan)
 {
 	struct schedule_state * s = data;
-	struct reg_value * v = get_reg_value(s, file, index, chan);
+	struct reg_value ** v = get_reg_valuep(s, file, index, chan);
 	struct reg_value_reader * reader;
 
 	if (!v)
 		return;
 
-	if (v->Writer == s->Current) {
+	if (*v && (*v)->Writer == s->Current) {
 		/* The instruction reads and writes to a register component.
 		 * In this case, we only want to increment dependencies by one.
 		 */
@@ -608,16 +858,28 @@ static void scan_read(void * data, struct rc_instruction * inst,
 
 	reader = memory_pool_malloc(&s->C->Pool, sizeof(*reader));
 	reader->Reader = s->Current;
-	reader->Next = v->Readers;
-	v->Readers = reader;
-	v->NumReaders++;
-
-	s->Current->NumDependencies++;
+	if (!*v) {
+		/* In this situation, the instruction reads from a register
+		 * that hasn't been written to or read from in the current
+		 * block. */
+		*v = memory_pool_malloc(&s->C->Pool, sizeof(struct reg_value));
+		memset(*v, 0, sizeof(struct reg_value));
+		(*v)->Readers = reader;
+	} else {
+		reader->Next = (*v)->Readers;
+		(*v)->Readers = reader;
+		/* Only update the current instruction's dependencies if the
+		 * register it reads from has been written to in this block. */
+		if ((*v)->Writer) {
+			s->Current->NumDependencies++;
+		}
+	}
+	(*v)->NumReaders++;
 
 	if (s->Current->NumReadValues >= 12) {
 		rc_error(s->C, "%s: NumReadValues overflow\n", __FUNCTION__);
 	} else {
-		s->Current->ReadValues[s->Current->NumReadValues++] = v;
+		s->Current->ReadValues[s->Current->NumReadValues++] = *v;
 	}
 }
 
@@ -652,6 +914,16 @@ static void scan_write(void * data, struct rc_instruction * inst,
 	}
 }
 
+static void is_rgb_to_alpha_possible_normal(
+	void * userdata,
+	struct rc_instruction * inst,
+	struct rc_src_register * src)
+{
+	struct rc_reader_data * reader_data = userdata;
+	reader_data->Abort = 1;
+
+}
+
 static void schedule_block(struct r300_fragment_program_compiler * c,
 		struct rc_instruction * begin, struct rc_instruction * end)
 {
@@ -683,6 +955,11 @@ static void schedule_block(struct r300_fragment_program_compiler * c,
 
 		if (!s.Current->NumDependencies)
 			instruction_ready(&s, s.Current);
+
+		/* Get global readers for possible RGB->Alpha conversion. */
+		rc_get_readers(s.C, inst, &s.Current->GlobalReaders,
+				is_rgb_to_alpha_possible_normal,
+				is_rgb_to_alpha_possible, NULL);
 	}
 
 	/* Temporarily unlink all instructions */
@@ -711,8 +988,13 @@ static int is_controlflow(struct rc_instruction * inst)
 
 void rc_pair_schedule(struct radeon_compiler *cc, void *user)
 {
+	struct schedule_state s;
+
 	struct r300_fragment_program_compiler *c = (struct r300_fragment_program_compiler*)cc;
 	struct rc_instruction * inst = c->Base.Program.Instructions.Next;
+
+	memset(&s, 0, sizeof(s));
+	s.C = &c->Base;
 	while(inst != &c->Base.Program.Instructions) {
 		struct rc_instruction * first;
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
index c549be5218..fc05366f50 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_pair_translate.c
@@ -280,9 +280,12 @@ static void set_pair_instruction(struct r300_fragment_program_compiler *c,
 			pair->RGB.DestIndex = inst->DstReg.Index;
 			pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ;
 		}
+
 		if (needalpha) {
-			pair->Alpha.DestIndex = inst->DstReg.Index;
 			pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
+			if (pair->Alpha.WriteMask) {
+				pair->Alpha.DestIndex = inst->DstReg.Index;
+			}
 		}
 	}
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program.c b/src/mesa/drivers/dri/r300/compiler/radeon_program.c
index 24b685fbeb..fe5756ebc4 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program.c
@@ -30,6 +30,7 @@
 #include <stdio.h>
 
 #include "radeon_compiler.h"
+#include "radeon_dataflow.h"
 
 
 /**
@@ -70,58 +71,98 @@ void rc_local_transform(
 	}
 }
 
+struct get_used_temporaries_data {
+	unsigned char * Used;
+	unsigned int UsedLength;
+};
+
+static void get_used_temporaries_cb(
+	void * userdata,
+	struct rc_instruction * inst,
+	rc_register_file file,
+	unsigned int index,
+	unsigned int mask)
+{
+	struct get_used_temporaries_data * d = userdata;
+
+	if (file != RC_FILE_TEMPORARY)
+		return;
+
+	if (index >= d->UsedLength)
+		return;
+
+	d->Used[index] |= mask;
+}
+
 /**
- * Left multiplication of a register with a swizzle
+ * This function fills in the parameter 'used' with a writemask that
+ * represent which components of each temporary register are used by the
+ * program.  This is meant to be combined with rc_find_free_temporary_list as a
+ * more efficient version of rc_find_free_temporary.
+ * @param used The function does not initialize this parameter.
  */
-struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg)
+void rc_get_used_temporaries(
+	struct radeon_compiler * c,
+	unsigned char * used,
+	unsigned int used_length)
+{
+	struct rc_instruction * inst;
+	struct get_used_temporaries_data d;
+	d.Used = used;
+	d.UsedLength = used_length;
+
+	for(inst = c->Program.Instructions.Next;
+			inst != &c->Program.Instructions; inst = inst->Next) {
+
+		rc_for_all_reads_mask(inst, get_used_temporaries_cb, &d);
+		rc_for_all_writes_mask(inst, get_used_temporaries_cb, &d);
+	}
+}
+
+/* Search a list of used temporaries for a free one
+ * \sa rc_get_used_temporaries
+ * @note If this functions finds a free temporary, it will mark it as used
+ * in the used temporary list (param 'used')
+ * @param used list of used temporaries
+ * @param used_length number of items in param 'used'
+ * @param mask which components must be free in the temporary index that is
+ * returned.
+ * @return -1 If there are no more free temporaries, otherwise the index of
+ * a temporary register where the components specified in param 'mask' are
+ * not being used.
+ */
+int rc_find_free_temporary_list(
+	struct radeon_compiler * c,
+	unsigned char * used,
+	unsigned int used_length,
+	unsigned int mask)
 {
-	struct rc_src_register tmp = srcreg;
 	int i;
-	tmp.Swizzle = 0;
-	tmp.Negate = 0;
-	for(i = 0; i < 4; ++i) {
-		rc_swizzle swz = GET_SWZ(swizzle, i);
-		if (swz < 4) {
-			tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3);
-			tmp.Negate |= GET_BIT(srcreg.Negate, swz) << i;
-		} else {
-			tmp.Swizzle |= swz << (i*3);
+	for(i = 0; i < used_length; i++) {
+		if ((~used[i] & mask) == mask) {
+			used[i] |= mask;
+			return i;
 		}
 	}
-	return tmp;
+	return -1;
 }
 
 unsigned int rc_find_free_temporary(struct radeon_compiler * c)
 {
-	char used[RC_REGISTER_MAX_INDEX];
-	unsigned int i;
-	struct rc_instruction * rcinst;
+	unsigned char used[RC_REGISTER_MAX_INDEX];
+	int free;
 
 	memset(used, 0, sizeof(used));
 
-	for (rcinst = c->Program.Instructions.Next; rcinst != &c->Program.Instructions; rcinst = rcinst->Next) {
-		const struct rc_sub_instruction *inst = &rcinst->U.I;
-		const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->Opcode);
-		unsigned int k;
-
-		for (k = 0; k < opcode->NumSrcRegs; k++) {
-			if (inst->SrcReg[k].File == RC_FILE_TEMPORARY)
-				used[inst->SrcReg[k].Index] = 1;
-		}
-
-		if (opcode->HasDstReg) {
-			if (inst->DstReg.File == RC_FILE_TEMPORARY)
-				used[inst->DstReg.Index] = 1;
-		}
-	}
+	rc_get_used_temporaries(c, used, RC_REGISTER_MAX_INDEX);
 
-	for (i = 0; i < RC_REGISTER_MAX_INDEX; i++) {
-		if (!used[i])
-			return i;
+	free = rc_find_free_temporary_list(c, used, RC_REGISTER_MAX_INDEX,
+								RC_MASK_XYZW);
+	if (free < 0) {
+		rc_error(c, "Ran out of temporary registers\n");
+		return 0;
 	}
-
-	rc_error(c, "Ran out of temporary registers\n");
-	return 0;
+	return free;
 }
 
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program.h b/src/mesa/drivers/dri/r300/compiler/radeon_program.h
index f0a77d7b53..df6c94b35f 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program.h
@@ -159,47 +159,6 @@ struct rc_program {
 	struct rc_constant_list Constants;
 };
 
-static inline rc_swizzle get_swz(unsigned int swz, rc_swizzle idx)
-{
-	if (idx & 0x4)
-		return idx;
-	return GET_SWZ(swz, idx);
-}
-
-static inline unsigned int combine_swizzles4(unsigned int src,
-		rc_swizzle swz_x, rc_swizzle swz_y, rc_swizzle swz_z, rc_swizzle swz_w)
-{
-	unsigned int ret = 0;
-
-	ret |= get_swz(src, swz_x);
-	ret |= get_swz(src, swz_y) << 3;
-	ret |= get_swz(src, swz_z) << 6;
-	ret |= get_swz(src, swz_w) << 9;
-
-	return ret;
-}
-
-static inline unsigned int combine_swizzles(unsigned int src, unsigned int swz)
-{
-	unsigned int ret = 0;
-
-	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_X));
-	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_Y)) << 3;
-	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_Z)) << 6;
-	ret |= get_swz(src, GET_SWZ(swz, RC_SWIZZLE_W)) << 9;
-
-	return ret;
-}
-
-struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg);
-
-static inline void reset_srcreg(struct rc_src_register* reg)
-{
-	memset(reg, 0, sizeof(struct rc_src_register));
-	reg->Swizzle = RC_SWIZZLE_XYZW;
-}
-
-
 /**
  * A transformation that can be passed to \ref rc_local_transform.
  *
@@ -222,6 +181,17 @@ void rc_local_transform(
 	struct radeon_compiler *c,
 	void *user);
 
+void rc_get_used_temporaries(
+	struct radeon_compiler * c,
+	unsigned char * used,
+	unsigned int used_length);
+
+int rc_find_free_temporary_list(
+	struct radeon_compiler * c,
+	unsigned char * used,
+	unsigned int used_length,
+	unsigned int mask);
+
 unsigned int rc_find_free_temporary(struct radeon_compiler * c);
 
 struct rc_instruction *rc_alloc_instruction(struct radeon_compiler * c);
@@ -233,4 +203,5 @@ unsigned int rc_recompute_ips(struct radeon_compiler * c);
 
 void rc_print_program(const struct rc_program *prog);
 
+rc_swizzle rc_mask_to_swizzle(unsigned int mask);
 #endif
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
index 39408845d5..c8063171b8 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
@@ -36,6 +36,7 @@
 #include "radeon_program_alu.h"
 
 #include "radeon_compiler.h"
+#include "radeon_compiler_util.h"
 
 
 static struct rc_instruction *emit1(
@@ -84,16 +85,6 @@ static struct rc_instruction *emit3(
 	return fpi;
 }
 
-static struct rc_dst_register dstreg(int file, int index)
-{
-	struct rc_dst_register dst;
-	dst.File = file;
-	dst.Index = index;
-	dst.WriteMask = RC_MASK_XYZW;
-	dst.RelAddr = 0;
-	return dst;
-}
-
 static struct rc_dst_register dstregtmpmask(int index, int mask)
 {
 	struct rc_dst_register dst = {0};
@@ -186,6 +177,38 @@ static struct rc_src_register swizzle_wwww(struct rc_src_register reg)
 	return swizzle_smear(reg, RC_SWIZZLE_W);
 }
 
+static int is_dst_safe_to_reuse(struct rc_instruction *inst)
+{
+	const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode);
+	unsigned i;
+
+	assert(info->HasDstReg);
+
+	if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY)
+		return 0;
+
+	for (i = 0; i < info->NumSrcRegs; i++) {
+		if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY &&
+		    inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index)
+			return 0;
+	}
+
+	return 1;
+}
+
+static struct rc_dst_register try_to_reuse_dst(struct radeon_compiler *c,
+					       struct rc_instruction *inst)
+{
+	unsigned tmp;
+
+	if (is_dst_safe_to_reuse(inst))
+		tmp = inst->U.I.DstReg.Index;
+	else
+		tmp = rc_find_free_temporary(c);
+
+	return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask);
+}
+
 static void transform_ABS(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
@@ -209,10 +232,26 @@ static void transform_CEIL(struct radeon_compiler* c,
 	 *     ceil(x) = x+frac(-x)
 	 */
 
-	int tempreg = rc_find_free_temporary(c);
-	emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]));
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+	emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, negate(inst->U.I.SrcReg[0]));
 	emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg));
+		inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index));
+	rc_remove_instruction(inst);
+}
+
+static void transform_CLAMP(struct radeon_compiler *c,
+	struct rc_instruction *inst)
+{
+	/* CLAMP dst, src, min, max
+	 *    into:
+	 * MIN tmp, src, max
+	 * MAX dst, tmp, min
+	 */
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+	emit2(c, inst->Prev, RC_OPCODE_MIN, 0, dst,
+		inst->U.I.SrcReg[0], inst->U.I.SrcReg[2]);
+	emit2(c, inst->Prev, RC_OPCODE_MAX, inst->U.I.SaturateMode, inst->U.I.DstReg,
+		srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1]);
 	rc_remove_instruction(inst);
 }
 
@@ -258,10 +297,10 @@ static void transform_DST(struct radeon_compiler* c,
 static void transform_FLR(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
-	emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0]);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
+	emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dst, inst->U.I.SrcReg[0]);
 	emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
+		inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
 	rc_remove_instruction(inst);
 }
 
@@ -351,14 +390,14 @@ static void transform_LIT(struct radeon_compiler* c,
 static void transform_LRP(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
 	emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
-		dstreg(RC_FILE_TEMPORARY, tempreg),
+		dst,
 		inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
 	emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
 		inst->U.I.DstReg,
-		inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[2]);
+		inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[2]);
 
 	rc_remove_instruction(inst);
 }
@@ -366,9 +405,8 @@ static void transform_LRP(struct radeon_compiler* c,
 static void transform_POW(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
-	struct rc_dst_register tempdst = dstreg(RC_FILE_TEMPORARY, tempreg);
-	struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempreg);
+	struct rc_dst_register tempdst = try_to_reuse_dst(c, inst);
+	struct rc_src_register tempsrc = srcreg(RC_FILE_TEMPORARY, tempdst.Index);
 	tempdst.WriteMask = RC_MASK_W;
 	tempsrc.Swizzle = RC_SWIZZLE_WWWW;
 
@@ -388,11 +426,11 @@ static void transform_RSQ(struct radeon_compiler* c,
 static void transform_SEQ(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_zero, builtin_one);
+		negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_zero, builtin_one);
 
 	rc_remove_instruction(inst);
 }
@@ -407,11 +445,11 @@ static void transform_SFL(struct radeon_compiler* c,
 static void transform_SGE(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
+		srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
 
 	rc_remove_instruction(inst);
 }
@@ -419,11 +457,11 @@ static void transform_SGE(struct radeon_compiler* c,
 static void transform_SGT(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
+		srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
 
 	rc_remove_instruction(inst);
 }
@@ -431,11 +469,11 @@ static void transform_SGT(struct radeon_compiler* c,
 static void transform_SLE(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, negate(inst->U.I.SrcReg[0]), inst->U.I.SrcReg[1]);
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
+		srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_zero, builtin_one);
 
 	rc_remove_instruction(inst);
 }
@@ -443,11 +481,11 @@ static void transform_SLE(struct radeon_compiler* c,
 static void transform_SLT(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
+		srcreg(RC_FILE_TEMPORARY, dst.Index), builtin_one, builtin_zero);
 
 	rc_remove_instruction(inst);
 }
@@ -455,11 +493,11 @@ static void transform_SLT(struct radeon_compiler* c,
 static void transform_SNE(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dst, inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
 	emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
-		negate(absolute(srcreg(RC_FILE_TEMPORARY, tempreg))), builtin_one, builtin_zero);
+		negate(absolute(srcreg(RC_FILE_TEMPORARY, dst.Index))), builtin_one, builtin_zero);
 
 	rc_remove_instruction(inst);
 }
@@ -473,12 +511,13 @@ static void transform_SSG(struct radeon_compiler* c,
 	 *   CMP tmp1, x, 1, 0
 	 *   ADD result, tmp0, -tmp1;
 	 */
-	unsigned tmp0, tmp1;
+	struct rc_dst_register dst0;
+	unsigned tmp1;
 
 	/* 0 < x */
-	tmp0 = rc_find_free_temporary(c);
+	dst0 = try_to_reuse_dst(c, inst);
 	emit3(c, inst->Prev, RC_OPCODE_CMP, 0,
-	      dstregtmpmask(tmp0, inst->U.I.DstReg.WriteMask),
+	      dst0,
 	      negate(inst->U.I.SrcReg[0]),
 	      builtin_one,
 	      builtin_zero);
@@ -495,7 +534,7 @@ static void transform_SSG(struct radeon_compiler* c,
 	/* result = tmp0 - tmp1 */
 	emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
 	      inst->U.I.DstReg,
-	      srcreg(RC_FILE_TEMPORARY, tmp0),
+	      srcreg(RC_FILE_TEMPORARY, dst0.Index),
 	      negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
 
 	rc_remove_instruction(inst);
@@ -517,15 +556,15 @@ static void transform_SWZ(struct radeon_compiler* c,
 static void transform_XPD(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
-	emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstreg(RC_FILE_TEMPORARY, tempreg),
+	emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dst,
 		swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
 		swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
 	emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
 		swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
 		swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
-		negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
+		negate(srcreg(RC_FILE_TEMPORARY, dst.Index)));
 
 	rc_remove_instruction(inst);
 }
@@ -553,6 +592,7 @@ int radeonTransformALU(
 	switch(inst->U.I.Opcode) {
 	case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
 	case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
+	case RC_OPCODE_CLAMP: transform_CLAMP(c, inst); return 1;
 	case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
 	case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 	case RC_OPCODE_DST: transform_DST(c, inst); return 1;
@@ -592,7 +632,7 @@ static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 {
 	/* There is no decent CMP available, so let's rig one up.
 	 * CMP is defined as dst = src0 < 0.0 ? src1 : src2
-	 * The following sequence consumes two temps and two extra slots
+	 * The following sequence consumes zero to two temps and two extra slots
 	 * (the second temp and the second slot is consumed by transform_LRP),
 	 * but should be equivalent:
 	 *
@@ -600,18 +640,18 @@ static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 	 * LRP dst, tmp0, src1, src2
 	 *
 	 * Yes, I know, I'm a mad scientist. ~ C. & M. */
-	int tempreg0 = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 
 	/* SLT tmp0, src0, 0.0 */
 	emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
-		dstreg(RC_FILE_TEMPORARY, tempreg0),
+		dst,
 		inst->U.I.SrcReg[0], builtin_zero);
 
 	/* LRP dst, tmp0, src1, src2 */
 	transform_LRP(c,
 		emit3(c, inst->Prev, RC_OPCODE_LRP, 0,
 		      inst->U.I.DstReg,
-		      srcreg(RC_FILE_TEMPORARY, tempreg0), inst->U.I.SrcReg[1],  inst->U.I.SrcReg[2]));
+		      srcreg(RC_FILE_TEMPORARY, dst.Index), inst->U.I.SrcReg[1],  inst->U.I.SrcReg[2]));
 
 	rc_remove_instruction(inst);
 }
@@ -642,24 +682,25 @@ static void transform_r300_vertex_DP3(struct radeon_compiler* c,
 static void transform_r300_vertex_fix_LIT(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
-	int tempreg = rc_find_free_temporary(c);
+	struct rc_dst_register dst = try_to_reuse_dst(c, inst);
 	unsigned constant_swizzle;
 	int constant = rc_constants_add_immediate_scalar(&c->Program.Constants,
 							 0.0000000000000000001,
 							 &constant_swizzle);
 
 	/* MOV dst, src */
+	dst.WriteMask = RC_MASK_XYZW;
 	emit1(c, inst->Prev, RC_OPCODE_MOV, 0,
-		dstreg(RC_FILE_TEMPORARY, tempreg),
+		dst,
 		inst->U.I.SrcReg[0]);
 
-	/* MAX dst.z, src, 0.00...001 */
+	/* MAX dst.y, src, 0.00...001 */
 	emit2(c, inst->Prev, RC_OPCODE_MAX, 0,
-		dstregtmpmask(tempreg, RC_MASK_Y),
-		srcreg(RC_FILE_TEMPORARY, tempreg),
+		dstregtmpmask(dst.Index, RC_MASK_Y),
+		srcreg(RC_FILE_TEMPORARY, dst.Index),
 		srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
 
-	inst->U.I.SrcReg[0] = srcreg(RC_FILE_TEMPORARY, tempreg);
+	inst->U.I.SrcReg[0] = srcreg(RC_FILE_TEMPORARY, dst.Index);
 }
 
 static void transform_r300_vertex_SEQ(struct radeon_compiler *c,
@@ -743,12 +784,13 @@ static void transform_r300_vertex_SSG(struct radeon_compiler* c,
 	 *   SLT tmp1, x, 0;
 	 *   ADD result, tmp0, -tmp1;
 	 */
-	unsigned tmp0, tmp1;
+	struct rc_dst_register dst0 = try_to_reuse_dst(c, inst);
+	unsigned tmp1;
 
 	/* 0 < x */
-	tmp0 = rc_find_free_temporary(c);
+	dst0 = try_to_reuse_dst(c, inst);
 	emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
-	      dstregtmpmask(tmp0, inst->U.I.DstReg.WriteMask),
+	      dst0,
 	      builtin_zero,
 	      inst->U.I.SrcReg[0]);
 
@@ -763,7 +805,7 @@ static void transform_r300_vertex_SSG(struct radeon_compiler* c,
 	/* result = tmp0 - tmp1 */
 	emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
 	      inst->U.I.DstReg,
-	      srcreg(RC_FILE_TEMPORARY, tmp0),
+	      srcreg(RC_FILE_TEMPORARY, dst0.Index),
 	      negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
 
 	rc_remove_instruction(inst);
@@ -781,6 +823,7 @@ int r300_transform_vertex_alu(
 	switch(inst->U.I.Opcode) {
 	case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
 	case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
+	case RC_OPCODE_CLAMP: transform_CLAMP(c, inst); return 1;
 	case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
 	case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
 	case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h
index 9dcd44c522..45f79ece5b 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_constants.h
@@ -181,4 +181,9 @@ static inline int rc_presubtract_src_reg_count(rc_presubtract_op op){
 		return 0;
 	}
 }
+
+#define RC_SOURCE_NONE  0x0
+#define RC_SOURCE_RGB   0x1
+#define RC_SOURCE_ALPHA 0x2
+
 #endif /* RADEON_PROGRAM_CONSTANTS_H */
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c
index a21fe8d3df..5905d26e52 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c
@@ -27,6 +27,9 @@
 
 #include "radeon_program_pair.h"
 
+#include "radeon_compiler_util.h"
+
+#include <stdlib.h>
 
 /**
  * Return the source slot where we installed the given register access,
@@ -204,24 +207,37 @@ void rc_pair_foreach_source_that_rgb_reads(
 	}
 }
 
-/*return 0 for rgb, 1 for alpha -1 for error. */
-
-unsigned int rc_source_type_that_arg_reads(
-	unsigned int source,
-	unsigned int swizzle)
+struct rc_pair_instruction_source * rc_pair_get_src(
+	struct rc_pair_instruction * pair_inst,
+	struct rc_pair_instruction_arg * arg)
 {
-	unsigned int chan;
-	unsigned int swz = RC_SWIZZLE_UNUSED;
-	unsigned int ret = RC_PAIR_SOURCE_NONE;
-
-	for(chan = 0; chan < 3; chan++) {
-		swz = GET_SWZ(swizzle, chan);
-		if (swz == RC_SWIZZLE_W) {
-			ret |= RC_PAIR_SOURCE_ALPHA;
-		} else if (swz == RC_SWIZZLE_X || swz == RC_SWIZZLE_Y
-						|| swz == RC_SWIZZLE_Z) {
-			ret |= RC_PAIR_SOURCE_RGB;
+	unsigned int i, type;
+	unsigned int channels = 0;
+
+	for(i = 0; i < 3; i++) {
+		if (arg == pair_inst->RGB.Arg + i) {
+			channels = 3;
+			break;
 		}
 	}
-	return ret;
+
+	if (channels == 0) {
+		for (i = 0; i < 3; i++) {
+			if (arg == pair_inst->Alpha.Arg + i) {
+				channels = 1;
+				break;
+			}
+		}
+	}
+
+	assert(channels > 0);
+	type = rc_source_type_swz(arg->Swizzle, channels);
+
+	if (type & RC_SOURCE_RGB) {
+		return &pair_inst->RGB.Src[arg->Source];
+	} else if (type & RC_SOURCE_ALPHA) {
+		return &pair_inst->Alpha.Src[arg->Source];
+	} else {
+		return NULL;
+	}
 }
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
index 54d44a2098..ccf7a0070c 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
@@ -55,10 +55,6 @@ struct radeon_compiler;
  */
 #define RC_PAIR_PRESUB_SRC 3
 
-#define RC_PAIR_SOURCE_NONE  0x0
-#define RC_PAIR_SOURCE_RGB   0x1
-#define RC_PAIR_SOURCE_ALPHA 0x2
-
 struct rc_pair_instruction_source {
 	unsigned int Used:1;
 	unsigned int File:3;
@@ -115,9 +111,9 @@ void rc_pair_foreach_source_that_rgb_reads(
 	void * data,
 	rc_pair_foreach_src_fn cb);
 
-unsigned int rc_source_type_that_arg_reads(
-	unsigned int source,
-	unsigned int swizzle);
+struct rc_pair_instruction_source * rc_pair_get_src(
+	struct rc_pair_instruction * pair_inst,
+	struct rc_pair_instruction_arg * arg);
 /*@}*/
 
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c
index 618ab5a099..ae13f6742f 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_print.c
@@ -129,6 +129,7 @@ static char rc_swizzle_char(unsigned int swz)
 	case RC_SWIZZLE_HALF: return 'H';
 	case RC_SWIZZLE_UNUSED: return '_';
 	}
+	fprintf(stderr, "bad swz: %u\n", swz);
 	return '?';
 }
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
index 530afa5e08..f9d9f34b6a 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_tex.c
@@ -28,6 +28,8 @@
 
 #include "radeon_program_tex.h"
 
+#include "radeon_compiler_util.h"
+
 /* Series of transformations to be done on textures. */
 
 static struct rc_src_register shadow_ambient(struct r300_fragment_program_compiler *compiler,
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c
index 5f67f536f6..7d76585a59 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_remove_constants.c
@@ -87,8 +87,9 @@ void rc_remove_unused_constants(struct radeon_compiler *c, void *user)
 		rc_for_all_reads_src(inst, mark_used, &d);
 	}
 
-	/* Pass 2: If there is relative addressing, mark all externals as used. */
-	if (has_rel_addr) {
+	/* Pass 2: If there is relative addressing or dead constant elimination
+	 * is disabled, mark all externals as used. */
+	if (has_rel_addr || !c->remove_unused_constants) {
 		for (unsigned i = 0; i < c->Program.Constants.Count; i++)
 			if (constants[i].Type == RC_CONSTANT_EXTERNAL)
 				const_used[i] = 1;
@@ -119,7 +120,7 @@ void rc_remove_unused_constants(struct radeon_compiler *c, void *user)
 	/*  is_identity ==> new_count == old_count
 	 * !is_identity ==> new_count <  old_count */
 	assert( is_identity || new_count <  c->Program.Constants.Count);
-	assert(!(has_rel_addr && are_externals_remapped));
+	assert(!((has_rel_addr || !c->remove_unused_constants) && are_externals_remapped));
 
 	/* Pass 4: Redirect reads of all constants to their new locations. */
 	if (!is_identity) {
@@ -127,7 +128,6 @@ void rc_remove_unused_constants(struct radeon_compiler *c, void *user)
 		     inst != &c->Program.Instructions; inst = inst->Next) {
 			rc_remap_registers(inst, remap_regs, inv_remap_table);
 		}
-
 	}
 
 	/* Set the new constant count. Note that new_count may be less than
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c
index 60e228be5b..88165f7895 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_rename_regs.c
@@ -33,100 +33,51 @@
 
 #include "radeon_compiler.h"
 #include "radeon_dataflow.h"
-
-struct reg_rename {
-	int old_index;
-	int new_index;
-	int temp_index;
-};
-
-static void rename_reg(void * data, struct rc_instruction * inst,
-			rc_register_file * file, unsigned int * index)
-{
-	struct reg_rename *r = data;
-
-	if(r->old_index == *index && *file == RC_FILE_TEMPORARY) {
-		*index = r->new_index;
-	}
-	else if(r->new_index == *index && *file == RC_FILE_TEMPORARY) {
-		*index = r->temp_index;
-	}
-}
-
-static void rename_all(
-	struct radeon_compiler *c,
-	struct rc_instruction * start,
-	unsigned int old,
-	unsigned int new,
-	unsigned int temp)
-{
-	struct rc_instruction * inst;
-	struct reg_rename r;
-	r.old_index = old;
-	r.new_index = new;
-	r.temp_index = temp;
-	for(inst = start; inst != &c->Program.Instructions;
-						inst = inst->Next) {
-		rc_remap_registers(inst, rename_reg, &r);
-	}
-}
+#include "radeon_program.h"
 
 /**
  * This function renames registers in an attempt to get the code close to
  * SSA form.  After this function has completed, most of the register are only
- * written to one time, with a few exceptions.  For example, this block of code
- * will not be modified by this function:
- * Mov Temp[0].x Const[0].x
- * Mov Temp[0].y Const[0].y
- * Basically, destination registers will be renamed if:
- * 1. There have been no previous writes to that register
- * or
- * 2. If the instruction is writting to the exact components (no more, no less)
- * of a register that has been written to by previous instructions.
+ * written to one time, with a few exceptions.
  *
  * This function assumes all the instructions are still of type
  * RC_INSTRUCTION_NORMAL.
  */
 void rc_rename_regs(struct radeon_compiler *c, void *user)
 {
-	unsigned int cur_index = 0;
-	unsigned int icount;
+	unsigned int i, used_length;
+	int new_index;
 	struct rc_instruction * inst;
-	unsigned int * masks;
+	struct rc_reader_data reader_data;
+	unsigned char * used;
 
-	/* The number of instructions in the program is also the maximum
-	 * number of temp registers that could potentially be used. */
-	icount = rc_recompute_ips(c);
-	masks = memory_pool_malloc(&c->Pool, icount * sizeof(unsigned int));
-	memset(masks, 0, icount * sizeof(unsigned int));
+	used_length = 2 * rc_recompute_ips(c);
+	used = memory_pool_malloc(&c->Pool, sizeof(unsigned char) * used_length);
+	memset(used, 0, sizeof(unsigned char) * used_length);
 
+	rc_get_used_temporaries(c, used, used_length);
 	for(inst = c->Program.Instructions.Next;
 					inst != &c->Program.Instructions;
 					inst = inst->Next) {
-		const struct rc_opcode_info * info;
-		unsigned int old_index, temp_index;
-		struct rc_dst_register * dst;
-		if(inst->Type != RC_INSTRUCTION_NORMAL) {
-			rc_error(c, "%s only works with normal instructions.",
-								__FUNCTION__);
-			return;
-		}
-		dst = &inst->U.I.DstReg;
-		info = rc_get_opcode_info(inst->U.I.Opcode);
-		if(!info->HasDstReg || dst->File != RC_FILE_TEMPORARY) {
+
+		if (inst->U.I.DstReg.File != RC_FILE_TEMPORARY)
 			continue;
+
+		rc_get_readers(c, inst, &reader_data, NULL, NULL, NULL);
+
+		if (reader_data.Abort || reader_data.ReaderCount == 0)
+			continue;
+
+		new_index = rc_find_free_temporary_list(c, used, used_length,
+						RC_MASK_XYZW);
+		if (new_index < 0) {
+			rc_error(c, "Ran out of temporary registers\n");
+			return;
 		}
-		if(dst->Index >= icount || !masks[dst->Index] ||
-					masks[dst->Index] == dst->WriteMask) {
-			old_index = dst->Index;
-			/* We need to set dst->Index here so get free temporary
-			 * will work. */
-			dst->Index = cur_index++;
-			temp_index = rc_find_free_temporary(c);
-			rename_all(c, inst->Next, old_index,
-						dst->Index, temp_index);
+
+		reader_data.Writer->U.I.DstReg.Index = new_index;
+		for(i = 0; i < reader_data.ReaderCount; i++) {
+			reader_data.Readers[i].U.Src->Index = new_index;
 		}
-		assert(dst->Index < icount);
-		masks[dst->Index] |= dst->WriteMask;
 	}
 }
diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c
index 0116c5d2fa..ed9955b05d 100644
--- a/src/mesa/drivers/dri/r300/r300_texstate.c
+++ b/src/mesa/drivers/dri/r300/r300_texstate.c
@@ -428,6 +428,7 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 	uint32_t internalFormat, type, format;
+	gl_format texFormat;
 
 	type = GL_BGRA;
 	format = GL_UNSIGNED_BYTE;
@@ -467,9 +468,6 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	radeon_miptree_unreference(&t->mt);
 	radeon_miptree_unreference(&rImage->mt);
 
-	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
-				   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
-	texImage->RowStride = rb->pitch / rb->cpp;
 	rImage->bo = rb->bo;
 	radeon_bo_ref(rImage->bo);
 	t->bo = rb->bo;
@@ -481,22 +479,35 @@ void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format
 	pitch_val = rb->pitch;
 	switch (rb->cpp) {
 	case 4:
-		if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
+		if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
+			texFormat = MESA_FORMAT_RGB888;
 			t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
-		else
+		}
+		else {
+			texFormat = MESA_FORMAT_ARGB8888;
 			t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
+		}
 		pitch_val /= 4;
 		break;
 	case 3:
 	default:
+		texFormat = MESA_FORMAT_RGB888;
 		t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
 		pitch_val /= 4;
 		break;
 	case 2:
+		texFormat = MESA_FORMAT_RGB565;
 		t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
 		pitch_val /= 2;
 		break;
 	}
+
+	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+				   rb->base.Width, rb->base.Height, 1, 0,
+				   rb->cpp, texFormat);
+	texImage->RowStride = rb->pitch / rb->cpp;
+
+
 	pitch_val--;
 	t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
 			| ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT))));
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c
index 2c9e4e2b84..53dacbfdf3 100644
--- a/src/mesa/drivers/dri/r600/evergreen_chip.c
+++ b/src/mesa/drivers/dri/r600/evergreen_chip.c
@@ -286,7 +286,11 @@ static void evergreenSetupVTXConstants(struct gl_context  * ctx,
     if (!paos->bo)
 	    return;
 
-	r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
+    if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_CEDAR) ||
+	(context->radeon.radeonScreen->chip_family == CHIP_FAMILY_PALM))
+	    r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, TC_ACTION_ENA_bit);
+    else
+	    r700SyncSurf(context, paos->bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
 
     //uSQ_VTX_CONSTANT_WORD0_0
     uSQ_VTX_CONSTANT_WORD0_0 = paos->offset;
diff --git a/src/mesa/drivers/dri/r600/evergreen_state.c b/src/mesa/drivers/dri/r600/evergreen_state.c
index a77be183a1..076a608573 100644
--- a/src/mesa/drivers/dri/r600/evergreen_state.c
+++ b/src/mesa/drivers/dri/r600/evergreen_state.c
@@ -1461,6 +1461,14 @@ static void evergreenInitSQConfig(struct gl_context * ctx)
         uMaxThreads = 248;
         uMaxStackEntries = 512;
 	    break;
+    case CHIP_FAMILY_PALM:
+	    uSqNumCfInsts       = 1;
+        bVC_ENABLE = GL_FALSE;
+        uMaxGPRs = 256;
+        uPSThreadCount = 96;
+        uMaxThreads = 192;
+        uMaxStackEntries = 256;
+	    break;
     default:
         uSqNumCfInsts       = 2;
         bVC_ENABLE = GL_TRUE;
diff --git a/src/mesa/drivers/dri/r600/evergreen_tex.c b/src/mesa/drivers/dri/r600/evergreen_tex.c
index 58420ed123..3b5448a0e4 100644
--- a/src/mesa/drivers/dri/r600/evergreen_tex.c
+++ b/src/mesa/drivers/dri/r600/evergreen_tex.c
@@ -31,9 +31,7 @@
 #include "main/enums.h"
 #include "main/image.h"
 #include "main/teximage.h"
-#include "main/mipmap.h"
 #include "main/simple_list.h"
-#include "main/texstore.h"
 #include "main/texobj.h"
 
 #include "texmem.h"
@@ -1024,15 +1022,15 @@ static GLboolean evergreen_setup_hardware_state(struct gl_context * ctx, struct
 	SETfield(t->SQ_TEX_RESOURCE5, t->maxLod - t->minLod, LAST_LEVEL_shift, LAST_LEVEL_mask);
     
 	SETfield(t->SQ_TEX_SAMPLER1,
-		     EG_S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 6),
+		     EG_S_FIXED(CLAMP(t->base.MinLod - t->minLod, 0, 15), 8),
 		     EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift, 
              EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask);
 	SETfield(t->SQ_TEX_SAMPLER1,
-		     EG_S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 6),
+		     EG_S_FIXED(CLAMP(t->base.MaxLod - t->minLod, 0, 15), 8),
 		     EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift, 
              EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask);
 	SETfield(t->SQ_TEX_SAMPLER2,
-		     EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 6),
+		     EG_S_FIXED(CLAMP(ctx->Texture.Unit[unit].LodBias + t->base.LodBias, -16, 16), 8),
 		     EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift, 
              EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask);
 
@@ -1152,6 +1150,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 	uint32_t internalFormat, type, format;
+	gl_format texFormat;
 
 	type = GL_BGRA;
 	format = GL_UNSIGNED_BYTE;
@@ -1191,10 +1190,6 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 	radeon_miptree_unreference(&t->mt);
 	radeon_miptree_unreference(&rImage->mt);
 
-	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
-				   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
-	texImage->RowStride = rb->pitch / rb->cpp;
-
 	rImage->bo = rb->bo;
 	radeon_bo_ref(rImage->bo);
 	t->bo = rb->bo;
@@ -1205,6 +1200,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 	switch (rb->cpp) {
 	case 4:
 		if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) {
+			texFormat = MESA_FORMAT_RGB888;
 			SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
 				     EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, 
                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
@@ -1218,6 +1214,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
 				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		} else {
+			texFormat = MESA_FORMAT_ARGB8888;
 			SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
 				     EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, 
                      EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
@@ -1236,6 +1233,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 	case 3:
 	default:
 		// FMT_8_8_8 ???
+		texFormat = MESA_FORMAT_RGB888;
 		SETfield(t->SQ_TEX_RESOURCE7, FMT_8_8_8_8,
 			     EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, 
                  EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
@@ -1251,6 +1249,7 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 		pitch_val /= 4;
 		break;
 	case 2:
+		texFormat = MESA_FORMAT_RGB565;
 		SETfield(t->SQ_TEX_RESOURCE7, FMT_5_6_5,
 			     EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift, 
                  EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask);
@@ -1267,6 +1266,11 @@ void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_textur
 		break;
 	}
 
+	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+				   rb->base.Width, rb->base.Height, 1, 0,
+				   rb->cpp, texFormat);
+	texImage->RowStride = rb->pitch / rb->cpp;
+
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c
index b6443bf0c5..aa1891eac3 100644
--- a/src/mesa/drivers/dri/r600/r600_context.c
+++ b/src/mesa/drivers/dri/r600/r600_context.c
@@ -259,7 +259,7 @@ static void r600InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
     R700_CHIP_CONTEXT *r700    = (R700_CHIP_CONTEXT*)(&context->hw);
 
     if(  (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_CEDAR)
-       &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_HEMLOCK) )
+       &&(context->radeon.radeonScreen->chip_family <= CHIP_FAMILY_PALM) )
     {
         r700->bShaderUseMemConstant = GL_TRUE;
     }
@@ -285,8 +285,13 @@ static void r600InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
 	ctx->Const.MaxTextureMaxAnisotropy = 16.0;
 	ctx->Const.MaxTextureLodBias = 16.0;
 
-	ctx->Const.MaxTextureLevels = 13; /* hw support 14 */
-	ctx->Const.MaxTextureRectSize = 4096; /* hw support 8192 */
+	if (screen->chip_family >= CHIP_FAMILY_CEDAR) {
+		ctx->Const.MaxTextureLevels = 15;
+		ctx->Const.MaxTextureRectSize = 16384;
+	} else {
+		ctx->Const.MaxTextureLevels = 14;
+		ctx->Const.MaxTextureRectSize = 8192;
+	}
 
 	ctx->Const.MinPointSize   = 0x0001 / 8.0;
 	ctx->Const.MinPointSizeAA = 0x0001 / 8.0;
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 3869768bf0..aafa687577 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -1001,6 +1001,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 	uint32_t internalFormat, type, format;
+        gl_format texFormat;
 
 	type = GL_BGRA;
 	format = GL_UNSIGNED_BYTE;
@@ -1046,10 +1047,6 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	radeon_miptree_unreference(&t->mt);
 	radeon_miptree_unreference(&rImage->mt);
 
-	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
-				   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
-	texImage->RowStride = rb->pitch / rb->cpp;
-
 	rImage->bo = rb->bo;
 	radeon_bo_ref(rImage->bo);
 	t->bo = rb->bo;
@@ -1060,6 +1057,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	switch (rb->cpp) {
 	case 4:
 		if (glx_texture_format == __DRI_TEXTURE_FORMAT_RGB) {
+			texFormat = MESA_FORMAT_RGB888;
 			SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 				 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
@@ -1072,6 +1070,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 			SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
 				 SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
 		} else {
+			texFormat = MESA_FORMAT_ARGB8888;
 			SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 				 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
@@ -1089,6 +1088,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 	case 3:
 	default:
 		// FMT_8_8_8 ???
+		texFormat = MESA_FORMAT_RGB888;
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
@@ -1103,6 +1103,7 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 		pitch_val /= 4;
 		break;
 	case 2:
+		texFormat = MESA_FORMAT_RGB565;
 		SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
 			 SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
 
@@ -1118,6 +1119,11 @@ void r600SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
 		break;
 	}
 
+	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+				   rb->base.Width, rb->base.Height, 1, 0,
+				   rb->cpp, texFormat);
+	texImage->RowStride = rb->pitch / rb->cpp;
+
 	pitch_val = (pitch_val + R700_TEXEL_PITCH_ALIGNMENT_MASK)
 		& ~R700_TEXEL_PITCH_ALIGNMENT_MASK;
 
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 2bf24096a0..bee9c3bc6d 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1134,7 +1134,7 @@ GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
              EG_VTX_WORD1__DST_SEL_W_shift,
              EG_VTX_WORD1__DST_SEL_W_mask);
     
-    SETfield(vfetch_instruction_ptr->m_Word1.val, 0, /* use format here, in r6/r7, format used set in const, need to use same */
+    SETfield(vfetch_instruction_ptr->m_Word1.val, 1, 
              EG_VTX_WORD1__UCF_shift,
              EG_VTX_WORD1__UCF_bit);
     SETfield(vfetch_instruction_ptr->m_Word1.val, data_format,
@@ -3334,7 +3334,14 @@ GLboolean assemble_CMP(r700_AssemblerBase *pAsm)
         return GL_FALSE;
     }
 
-    pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE;
+    if(8 == pAsm->unAsic)
+    {
+	pAsm->D.dst.opcode = EG_OP3_INST_CNDGE;
+    }
+    else
+    {
+	pAsm->D.dst.opcode = SQ_OP3_INST_CNDGE;
+    }
     pAsm->D.dst.op3     = 1;  
 
     tmp = (-1);
@@ -3416,8 +3423,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode)
     checkop1(pAsm);
 
     tmp = gethelpr(pAsm);
-
-    pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    }
     pAsm->D.dst.op3    = 1;
 
     setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -3457,7 +3470,14 @@ GLboolean assemble_TRIG(r700_AssemblerBase *pAsm, BITS opcode)
     {
         return GL_FALSE;
     }
-    pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    }
     pAsm->D.dst.op3    = 1;
 
     setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -4742,7 +4762,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm)
 
     tmp = gethelpr(pAsm);
 
-    pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    }
     pAsm->D.dst.op3    = 1;
 
     setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -4782,7 +4809,14 @@ GLboolean assemble_SCS(r700_AssemblerBase *pAsm)
     {
         return GL_FALSE;
     }
-    pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_MULADD;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_MULADD;
+    }
     pAsm->D.dst.op3    = 1;
 
     setaddrmode_PVSDST(&(pAsm->D.dst), ADDR_ABSOLUTE);
@@ -5010,7 +5044,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm)
     
     GLuint tmp = gethelpr(pAsm);
     /* tmp = (src > 0 ? 1 : src) */
-    pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
+    }
     pAsm->D.dst.op3    = 1;
     pAsm->D.dst.rtype = DST_REG_TEMPORARY;
     pAsm->D.dst.reg   = tmp;
@@ -5033,7 +5074,14 @@ GLboolean assemble_SSG(r700_AssemblerBase *pAsm)
     }
 
     /* dst = (-tmp > 0 ? -1 : tmp) */
-    pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
+    if(8 == pAsm->unAsic)
+    {
+        pAsm->D.dst.opcode = EG_OP3_INST_CNDGT;
+    }
+    else
+    {
+        pAsm->D.dst.opcode = SQ_OP3_INST_CNDGT;
+    }
     pAsm->D.dst.op3    = 1;
 
     if( GL_FALSE == assemble_dst(pAsm) )
diff --git a/src/mesa/drivers/dri/radeon/radeon_chipset.h b/src/mesa/drivers/dri/radeon/radeon_chipset.h
index 61106fbc43..82789cec5e 100644
--- a/src/mesa/drivers/dri/radeon/radeon_chipset.h
+++ b/src/mesa/drivers/dri/radeon/radeon_chipset.h
@@ -440,6 +440,11 @@
 #define PCI_CHIP_HEMLOCK_689C           0x689C
 #define PCI_CHIP_HEMLOCK_689D           0x689D
 
+#define PCI_CHIP_PALM_9802              0x9802
+#define PCI_CHIP_PALM_9803              0x9803
+#define PCI_CHIP_PALM_9804              0x9804
+#define PCI_CHIP_PALM_9805              0x9805
+
 enum {
    CHIP_FAMILY_R100,
    CHIP_FAMILY_RV100,
@@ -483,6 +488,7 @@ enum {
    CHIP_FAMILY_JUNIPER,
    CHIP_FAMILY_CYPRESS,
    CHIP_FAMILY_HEMLOCK,
+   CHIP_FAMILY_PALM,
    CHIP_FAMILY_LAST
 };
 
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index a436ec112c..ca6ab46ca4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -99,6 +99,7 @@ static const char* get_chip_family_name(int chip_family)
 	case CHIP_FAMILY_JUNIPER: return "JUNIPER";
 	case CHIP_FAMILY_CYPRESS: return "CYPRESS";
 	case CHIP_FAMILY_HEMLOCK: return "HEMLOCK";
+	case CHIP_FAMILY_PALM: return "PALM";
 	default: return "unknown";
 	}
 }
@@ -246,16 +247,9 @@ GLboolean radeonInitContext(radeonContextPtr radeon,
 	        DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
 
 	if (IS_R600_CLASS(radeon->radeonScreen)) {
-		int chip_family = radeon->radeonScreen->chip_family;
-		if (chip_family >= CHIP_FAMILY_CEDAR) {
-			radeon->texture_row_align = 512;
-			radeon->texture_rect_row_align = 512;
-			radeon->texture_compressed_row_align = 512;
-		} else {
-			radeon->texture_row_align = radeon->radeonScreen->group_bytes;
-			radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
-			radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
-		}
+		radeon->texture_row_align = radeon->radeonScreen->group_bytes;
+		radeon->texture_rect_row_align = radeon->radeonScreen->group_bytes;
+		radeon->texture_compressed_row_align = radeon->radeonScreen->group_bytes;
 	} else if (IS_R200_CLASS(radeon->radeonScreen) ||
 		   IS_R100_CLASS(radeon->radeonScreen)) {
 		radeon->texture_row_align = 32;
@@ -741,10 +735,9 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,
 						buffers[i].flags);
 
 			if (bo == NULL) {
-
 				fprintf(stderr, "failed to attach %s %d\n",
 					regname, buffers[i].name);
-
+				continue;
 			}
 
 			ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
index 088f970172..a68a976877 100644
--- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
+++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h
@@ -49,7 +49,7 @@ struct _radeon_mipmap_level {
 };
 
 /* store the max possible in the miptree */
-#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 13
+#define RADEON_MIPTREE_MAX_TEXTURE_LEVELS 15
 
 /**
  * A mipmap tree contains texture images in the layout that the hardware
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 1ea52f96d7..94e56c2ade 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -1155,6 +1155,14 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
        screen->chip_flags = RADEON_CHIPSET_TCL;
        break;
 
+    case PCI_CHIP_PALM_9802:
+    case PCI_CHIP_PALM_9803:
+    case PCI_CHIP_PALM_9804:
+    case PCI_CHIP_PALM_9805:
+       screen->chip_family = CHIP_FAMILY_PALM;
+       screen->chip_flags = RADEON_CHIPSET_TCL;
+       break;
+
    default:
       fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
 	      device_id);
@@ -1323,7 +1331,11 @@ radeonCreateScreen( __DRIscreen *sPriv )
 	   screen->chip_flags |= RADEON_CLASS_R600;
 
    /* set group bytes for r6xx+ */
-   screen->group_bytes = 256;
+   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+	   screen->group_bytes = 512;
+   else
+	   screen->group_bytes = 256;
+
    screen->cpp = dri_priv->bpp / 8;
    screen->AGPMode = dri_priv->AGPMode;
 
@@ -1568,9 +1580,13 @@ radeonCreateScreen2(__DRIscreen *sPriv)
    else
 	   screen->chip_flags |= RADEON_CLASS_R600;
 
-   /* r6xx+ tiling, default to 256 group bytes */
-   screen->group_bytes = 256;
-   if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6)) {
+   /* r6xx+ tiling, default group bytes */
+   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
+	   screen->group_bytes = 512;
+   else
+	   screen->group_bytes = 256;
+   if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 6) &&
+       (screen->chip_family < CHIP_FAMILY_CEDAR)) {
 	   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
 	   if (ret)
 		   fprintf(stderr, "failed to get tiling info\n");
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
index dd8ecdd500..32c021cb54 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -653,6 +653,7 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_form
 	radeonTexObjPtr t;
 	uint32_t pitch_val;
 	uint32_t internalFormat, type, format;
+	gl_format texFormat;
 
 	type = GL_BGRA;
 	format = GL_UNSIGNED_BYTE;
@@ -692,10 +693,6 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_form
 	radeon_miptree_unreference(&t->mt);
 	radeon_miptree_unreference(&rImage->mt);
 
-	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
-				   rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
-	texImage->RowStride = rb->pitch / rb->cpp;
-
 	rImage->bo = rb->bo;
 	radeon_bo_ref(rImage->bo);
 	t->bo = rb->bo;
@@ -705,23 +702,34 @@ void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_form
 	t->override_offset = 0;
 	switch (rb->cpp) {
 	case 4:
-		if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
+		if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
 			t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
-		else
+			texFormat = MESA_FORMAT_RGB888;
+		}
+		else {
 			t->pp_txformat = tx_table[MESA_FORMAT_ARGB8888].format;
+			texFormat = MESA_FORMAT_ARGB8888;
+		}
 		t->pp_txfilter |= tx_table[MESA_FORMAT_ARGB8888].filter;
 		break;
 	case 3:
 	default:
+		texFormat = MESA_FORMAT_RGB888;
 		t->pp_txformat = tx_table[MESA_FORMAT_RGB888].format;
 		t->pp_txfilter |= tx_table[MESA_FORMAT_RGB888].filter;
 		break;
 	case 2:
+		texFormat = MESA_FORMAT_RGB565;
 		t->pp_txformat = tx_table[MESA_FORMAT_RGB565].format;
 		t->pp_txfilter |= tx_table[MESA_FORMAT_RGB565].filter;
 		break;
 	}
 
+	_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
+				   rb->base.Width, rb->base.Height, 1, 0,
+				   rb->cpp, texFormat);
+	texImage->RowStride = rb->pitch / rb->cpp;
+
 	t->pp_txpitch &= (1 << 13) -1;
 	pitch_val = rb->pitch;
 
diff --git a/src/mesa/drivers/dri/sis/server/sis_dri.h b/src/mesa/drivers/dri/sis/server/sis_dri.h
index f0171f3c0f..7d8f507115 100644
--- a/src/mesa/drivers/dri/sis/server/sis_dri.h
+++ b/src/mesa/drivers/dri/sis/server/sis_dri.h
@@ -72,13 +72,4 @@ typedef struct {
   int dummy;
 } SISDRIContextRec, *SISDRIContextPtr;
 
-#ifdef XFree86Server
-
-#include "screenint.h"
-
-Bool SISDRIScreenInit(ScreenPtr pScreen);
-void SISDRICloseScreen(ScreenPtr pScreen);
-Bool SISDRIFinishScreenInit(ScreenPtr pScreen);
-
-#endif
 #endif
diff --git a/src/mesa/drivers/dri/swrast/swrast.c b/src/mesa/drivers/dri/swrast/swrast.c
index 52ba3acf65..c7940e9c0d 100644
--- a/src/mesa/drivers/dri/swrast/swrast.c
+++ b/src/mesa/drivers/dri/swrast/swrast.c
@@ -48,7 +48,6 @@
 #include "utils.h"
 
 #include "main/teximage.h"
-#include "main/texfetch.h"
 #include "main/texformat.h"
 #include "main/texstate.h"
 
@@ -69,6 +68,7 @@ static void swrastSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
     struct gl_texture_object *texObj;
     struct gl_texture_image *texImage;
     uint32_t internalFormat;
+    gl_format texFormat;
 
     dri_ctx = pDRICtx->driverPrivate;
 
@@ -82,15 +82,13 @@ static void swrastSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
 
     sPriv->swrast_loader->getDrawableInfo(dPriv, &x, &y, &w, &h, dPriv->loaderPrivate);
 
-    _mesa_init_teximage_fields(&dri_ctx->Base, target, texImage,
-			       w, h, 1, 0, internalFormat);
-
     if (texture_format == __DRI_TEXTURE_FORMAT_RGB)
-	texImage->TexFormat = MESA_FORMAT_XRGB8888;
+	texFormat = MESA_FORMAT_XRGB8888;
     else
-	texImage->TexFormat = MESA_FORMAT_ARGB8888;
+	texFormat = MESA_FORMAT_ARGB8888;
 
-    _mesa_set_fetch_functions(texImage, 2);
+    _mesa_init_teximage_fields(&dri_ctx->Base, target, texImage,
+			       w, h, 1, 0, internalFormat, texFormat);
 
     sPriv->swrast_loader->getImage(dPriv, x, y, w, h, (char *)texImage->Data,
 				   dPriv->loaderPrivate);
diff --git a/src/mesa/drivers/dri/tdfx/tdfx_context.h b/src/mesa/drivers/dri/tdfx/tdfx_context.h
index fb38419dcd..7e2f0e00a8 100644
--- a/src/mesa/drivers/dri/tdfx/tdfx_context.h
+++ b/src/mesa/drivers/dri/tdfx/tdfx_context.h
@@ -41,11 +41,7 @@
 
 #include <sys/time.h>
 #include "dri_util.h"
-#ifdef XFree86Server
-#include "GL/xf86glx.h"
-#else
 #include "main/glheader.h"
-#endif
 #if defined(__linux__)
 #include <signal.h>
 #endif
diff --git a/src/mesa/drivers/dri/unichrome/server/via_dri.h b/src/mesa/drivers/dri/unichrome/server/via_dri.h
index b47397d572..c6eed03c1c 100644
--- a/src/mesa/drivers/dri/unichrome/server/via_dri.h
+++ b/src/mesa/drivers/dri/unichrome/server/via_dri.h
@@ -35,9 +35,7 @@
 #define VIA_DRIDDX_VERSION_MINOR  0
 #define VIA_DRIDDX_VERSION_PATCH  0
 
-#ifndef XFree86Server
 typedef int Bool;
-#endif
 
 typedef struct {
     drm_handle_t handle;
author	Christoph Bumiller <e0425955@student.tuwien.ac.at>	2010-12-19 21:46:33 +0100
committer	Christoph Bumiller <e0425955@student.tuwien.ac.at>	2010-12-19 21:46:33 +0100
commit	0f68236a2487dbeb0396b996debcda595b0b54a1 (patch)
tree	938ae3b779349b6dba6f5a891550604f9a9ca895 /src/mesa/drivers/dri
parent	d047168d81cfeb39a98f3ae16416872facc6237c (diff)
parent	237880463d5168cad8df0bae6018b5fd76617777 (diff)